Service Manuals, User Guides, Schematic Diagrams or docs for : Compal Compal_LA-4114P
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A B C D E
1 1
2
Compal confidential 2
Schematics Document
Mobile AMD S1G2 CPU with ATI
3
RX781(NB) & SB700(SB) core logic 3
2008-11-07
REV:0.1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/11 Deciphered Date 200810/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4114P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, November 06, 2008 Sheet 1 of 54
A B C D E
A B C D E
Compal Confidential
OPP Rachman AMD 14" Discrete - LA-4112P
Accelerometer Thermal Sensor
72QFN
1
LIS3LV02DL-TR ADM1032ARMZ AMD S1G2 CPU DDR2-SO-DIMM X2 1
Page 37 Page 6
DDR2 800MHz 1.8V BANK 0, 1, 2, 3 Page 8, 9 Clock Generator
Dual Channel PC2-5300 (DDR2/667) SLG8SP626VTR
VRAM
Fan conn
638-PIN uFCPGA 638 PC2-6400 (DDR2/800) Page 22
256MB/512MB Page 4
Page 4, 5, 6, 7
page 19, 20
DDR2 400MHz Hyper Transport Link
16X16
Discrete PCI-E Lane*16
ATI M82-SCE
Page 15,16,17,18,21
ATI RS780, RX781
LVDS Panel RS780MN/CE
Interface Page 24
Page 10, 11, 12, 13, 14
2 2
USB2.0 X12
CRT USB conn x3
Page 38
Page 23
1600x1200 max resolution at 75Hz A-Link Express II
4X PCI-E
HDMI BT Conn daughter board
Page 38
Page 25
PCI-E BUS*5 Azalia (HDA I/F)
USB WebCam
SATA Master-1 Chicony CNF7047 daughter board
ATI SB700 SATA Master-2
Page 24
SATA Slave
CardReader-JM385 Realtek Mini-Card* 1
SATA Slave
5 in 1 8102EL(10/100M) WLAN Card
802.11a/b/g/n Page 26,27,28,29,30
Page 34 Page 32 Page 34
MDC V1.5 daughter board
Page 41
3
CardReader CONN RJ45/11 CONN LPC BUS Audio CKT 3
Page 32
Codec_IDT9271B7 AMP & Audio Jack
Page 34
Page 35 TPA6017A2 Page 36
5 in 1:SD/MMC/MS/MSPro/XS
Support for RS-MMC, Memory Stick Duo and Memory Stick
Duo Pro, Micro-M2, Mini-SD, and MicroSD KBC SATA HDD Connector
ENE KB926 Page 31
Page 40
LED SATA ODD Connector
Page 31
Page 41 Touch Pad CONN. Int.KBD
Page 41 Page 40
RTC CKT.
Page 26
Consumer IR SPI SPI ROM e-SATA Connector
25LF080A
Page 36/42 Page 39 Page 38
4 4
Vista 32&64 bit supporttive
Power On/Off CKT. Energy star 4.0/EPEAT request compliant
P41
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/11 Deciphered Date 200810/11 Title
DC/DC Interface CKT. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Page 43 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4114P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 10, 2008 Sheet 2 of 54
A B C D E
A B C D E
O MEANS ON X MEANS OFF Symbol Note :
Voltage Rails
1 1
: means Digital Ground
+5VS
+3VS : means Analog Ground
+2.5VS
power
plane +1.8VS @ : means just reserve , no build
+1.5VS DEBUG@ : means just reserve for debug.
+5VALW +1.8V +1.1VS
+B +VGA_CORE
+0.9V
+3VL +3VALW +1.2V_HT
+5VL +CPU_CORE_0
+1.2VALW
State +CPU_CORE_1
+CPU_CORE_NB
ZZZ
2 ZZZ 2
S0
O O O O
X76-VRAM
X76-VRAM PCB-MB
S1 X7613432L04 LA-4114P
O O O O
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X
SMBUS Control Table
THERMAL THERMAL WL
SENSOR SERIAL SENSOR
3
SOURCE VGA M82-SE BATT EEPROM CPU & SODIMM CLK CHIP MINI CARD LCD HDMI CRT G-Sensor 3
ADM1032 ADM1032 I / II Slot 1
I2C / SMBUS ADDRESSING
SMB_EC_CK1
SMB_EC_DA1
KB926 X V X X X X X X X X X
DEVICE HEX ADDRESS SMB_EC_CK2
DDR SO-DIMM 0 A0 10100000 SMB_EC_DA2
KB926
V X X V X X X X X X X
DDR SO-DIMM 1 A4 10100100 SCL
CLOCK GENERATOR (EXT.) D2 11010010 SDA
VGA
M82-SE
X X X X X X X V X X X
ACCELEROMETER 3A 00111010 DDC4CLK
DDC4DATA
VGA
M82-SE
X X X X X X X X V X X
EC SM Bus1 address EC SM Bus2 address DDC3CLK
Device HEX Address Device HEX Address
DDC3DATA
VGA
M82-SE
X X X X X X X X X V X
SCL0
Smart Battery 16H 0001 011X b ADI1032-2 CPU 9AH 1001 101X b SDA0
SB700 X X X X V V X X X X V
24C16 A0H 1010 000X b ADI1032-1 VGA 98H 1001 100X b SCL1
CPU SIC interface 98H 1001 100X b SDA1
SB700 X X X X X X V X X X X
SCL2
4
SDA2
SB700 X X X X X X X X X X X 4
SCL3
SDA3
SB700 X X X X X X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/11 Deciphered Date 200810/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4114P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 10, 2008 Sheet 3 of 54
A B C D E
A B C D E
1 1
+1.2V_HT
VLDT CAP.
250 mil
1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
<10> H_CADIN[0..15] H_CADON[0..15] <10>
Near CPU Socket
+1.2V_HT
1.5A(+-60mV_dc, JCPUA
+-75mV_ac)
D1 VLDT_A0 HT LINK VLDT_B0 AE2 +VLDT_B 1 2
D2 AE3 C7 4.7U_0805_10V4Z
VLDT_A1 VLDT_B1 If VLDT is connected only on one side, one
D3 VLDT_A2 VLDT_B2 AE4
D4 AE5 4.7uF cap should be added to the island
VLDT_A3 VLDT_B3 side.
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
2 H_CADIP3 H_CADOP3 2
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
H_CADIN3 H1 AA3 H_CADON3
H_CADIP4 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP4
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
H_CADIN5 L2 U1 H_CADON5
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H_CADIN6 M1 U3 H_CADON6
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
H_CADIN9 F4 AC5 H_CADON9
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
H_CADIN11 H4 AA5 H_CADON11
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
H_CADIN12 K4 W5 H_CADON12
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 L0_CADIN_H13 L0_CADOUT_H13 V4
H_CADIN13 M5 V3 H_CADON13
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14
M3 L0_CADIN_H14 L0_CADOUT_H14 V5
H_CADIN14 M4 U5 H_CADON14
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 H_CADON15 +5VS
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
J3 Y1
<10>
<10>
H_CLKIP0
H_CLKIN0 J2
J5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKOUT_H0
L0_CLKOUT_L0 W1
Y4
H_CLKOP0
H_CLKON0
<10>
<10> PWM Fan Control circuit JP2
<10> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 <10>
1
<10> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <10> 1 1 1 1
C8 @ C9 2
3 D1 0.1U_0402_16V4Z 2 3
<10> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <10>
P1 R3 CH751H-40PT_SOD323-2 4.7U_0805_10V4Z 3
<10> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <10> 2 2 GND
<10> H_CTLIP1 P3 T5 H_CTLOP1 <10> 4
2
L0_CTLIN_H1 L0_CTLOUT_H1 GND
<10> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <10>
ACES_88231-02001
+VCC_FAN CONN@
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
1
2
5
6
1
Athlon 64 S1
Processor Socket D Q1 @ D2
G
3 RLZ5.1B_LL34
<40> FAN_PWM S SI3456BDV-T1-E3_TSOP6
2
4
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/11 Deciphered Date 200810/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4114P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, November 06, 2008 Sheet 4 of 54
A B C D E
A B C D E
Processor DDR2 Memory Interface
PLACE CLOSE TO PROCESSOR
1 WITHIN 1.5 INCH JCPUC 1
<9> DDR_B_D[63..0]
MEM:DATA
DDR_A_D[63..0] <8>
DDR_A_CLK0 DDR_B_D0 C11 G12 DDR_A_D0
DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1
1 A11 MB_DATA1 MA_DATA1 F12
DDR_B_D2 A14 H14 DDR_A_D2
C10 DDR_B_D3 MB_DATA2 MA_DATA2 DDR_A_D3
B14 MB_DATA3 MA_DATA3 G14
1.5P_0402_50V9C DDR_B_D4 G11 H11 DDR_A_D4
DDR_A_CLK#0 2 DDR_B_D5 MB_DATA4 MA_DATA4 DDR_A_D5
E11 MB_DATA5 MA_DATA5 H12
DDR_B_D6 D12 C13 DDR_A_D6
DDR_A_CLK1 DDR_B_D7 MB_DATA6 MA_DATA6 DDR_A_D7
A13 MB_DATA7 MA_DATA7 E13
1 DDR_B_D8 A15 H15 DDR_A_D8
DDR_B_D9 MB_DATA8 MA_DATA8 DDR_A_D9
A16 MB_DATA9 MA_DATA9 E15
C11 DDR_B_D10 A19 E17 DDR_A_D10
1.5P_0402_50V9C DDR_B_D11 MB_DATA10 MA_DATA10 DDR_A_D11
A20 MB_DATA11 MA_DATA11 H17
DDR_A_CLK#1 2 DDR_B_D12 DDR_A_D12
C14 MB_DATA12 MA_DATA12 E14
+1.8V DDR_B_D13 D14 F14 DDR_A_D13
DDR_B_D14 MB_DATA13 MA_DATA13 DDR_A_D14
C18 MB_DATA14 MA_DATA14 C17
DDR_B_CLK0 DDR_B_D15 D18 G17 DDR_A_D15
MB_DATA15 MA_DATA15
2
1 DDR_B_D16 D20 G18 DDR_A_D16
R1 DDR_B_D17 MB_DATA16 MA_DATA16 DDR_A_D17
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