Service Manuals, User Guides, Schematic Diagrams or docs for : Compal Compal_LA-4961P_r10
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A B C D E
1 1
2
Compal confidential 2
Schematics Document
Mobile AMD S1G3 CPU with ATI
3
RS880M(NB) & SB710(SB) core logic 3
2009-08-27
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/03/23 Deciphered Date 2010/03/23 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4961P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 27, 2009 Sheet 1 of 54
A B C D E
A B C D E
Compal Confidential TAG UMA
Accelerometer Thermal Sensor Caspian 72QFN
ST LIS302DLTR ADM1032 AMD S1G3 CPU DDR2-SO-DIMM X2 Clock Generator
Page 30 Page 4 DDR2 800MHz 1.8V BANK 0, 1, 2, 3 Page 8, 9
ICS9LPRS476E
Dual Channel
1
Fan conn
638-PIN uFCPGA 638 Page 15 1
Page 4
Page 4, 5, 6, 7
Hyper Transport Link Side-Port DDR2 SDRAM
16X16
512Mbits(32Mbx16)-64MB
LVDS Panel Page 13
Interface Page 17
DDR2 400MHz
WWAN USB X 1
CRT
ATI RS880M Page 27
Page 16
USB x2(Docking)Page 33
Display Port Page 10, 11, 12, 13, 14 FingerPrinter VFM451
Page 18 daughter board
daughter board USBx1 Page 30
2
A-Link Express II 2
Mini Card UWB 4X PCI-E USB conn x 2(For I/O)
Express Card 54 PCIE X 1 BT Conn USB x 1Page 30
PCIE X1 + USB X1
USB2.0
Page 31
Page 27
USB ConnX2 daughter board
Azalia Page 31
ATI SB710 SATA0
sub BD
USB x1(Camara)
Page 17
SATA1
PCI-E BUS
Page 19, 20, 21 ,22, 23
WLAN Card MDC V1.5 RJ11
10/100/1000 LAN Rico R5U230 Page 28 Page 28
USB + PCIE X1
88E8072
Controller Audio CKT TPA6041A
Page 27
Page 25 Page 31 92HD75 Page 31 AMP & Audio Jack Page 31
daughter board
3
RJ45 CONN SATA ODD Connector 3
Page 24
1394 port Smart Card P38
Page 26 Docking CONN.
LPC BUS 2.5" SATA HDD Connector
Page 24
(1) PCI Express x1 channels
daughter board (2) PS/2 Interfaces
(2) USB 2.channels
(2) SATA Channels
(2) Display Port Channels
SMSC Super I/O (1) Serial Port
TPM1.2 SMSC KBC 1098 (1) Parallel Port
SLB9635TT ITE IT8305 35
Page
(1) Line In
Page 29 page 34 (1) Line Out
Power OK CKT. (1) RJ45 (10/100/1000)
page 36 C OM1 LPT (1) VGA
TrackPoint CONN. Int.KBD ( Docking ) ( Docking ) (1) 2 LAN indicator LED's
LED CKT. Page 28
Page 28 Page 33 Page 33 (1) Power Button
4
Power On/Off CKT. (1) I2C interface 4
Page 31
page 28 Touch Pad CONN. SPI ROM
Page 31
RTC CKT. 2 MB Page 29
DC/DC Interface CKT.
Page 31
Page 33 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4961P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 27, 2009 Sheet 2 of 54
A B C D E
A B C D E
O MEANS ON X MEANS OFF
Voltage Rails Symbol Note :
1 1
: means Digital Ground
+5VS
+3VS : means Analog Ground
+1.5VS
power
plane +0.9V
+CPU_CORE_0
+5VALW +1.8V +2.5VS
+B +1.8VS
Layout Notes
+3VALW +NB_VDDC
VL
+VDDA11PCIE
: Question Area Mark.(Wait check)
State +3VL
"*" as default BOM setting
@ : means just reserve , no build
45@ : Install when 45 level Assy.
2 CONN@:means ME part 2
S0
O O O O
S1
O O O O
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X
3 3
SMBUS Control Table
THERMAL
SOURCE INVERTER BATT EEPROM SENSOR SODIMM CLK CHIP MINI CARD LCD HDMI G-Sensor
CPU &
SERIAL ADM1032 I / II Slot 2
SMB_CK_CLK0
SMB_CK_DAT0
SB710 X X X V V X X X X V
SMB_CK_CLK1
SMB_CK_DAT1
SB710 X X X X X X X X X X
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4961P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 27, 2009 Sheet 3 of 54
A B C D E
A B C D E
1 1
+1.2V_HT
VLDT CAP.
250 mil
1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 10U_0805_10V4Z 10U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
<10> H_CADIN[0..15] H_CADON[0..15] <10>
change 4.7U to 10U for AMD S1G3 request. HP 12/8 Near CPU Socket
+1.2V_HT +1.2V_HT
JCPU1A
VLDT=500mA D1
VLDT_A0 HT LINK VLDT_B0
AE2 1 2
D2 AE3 C7 10U_0805_10V4Z
D3
D4
VLDT_A1
VLDT_A2
VLDT_B1
VLDT_B2 AE4
AE5
Thermal Sensor EMC1402
VLDT_A3 VLDT_B3
H_CADIP0 E3 AD1 H_CADOP0 +3VS U1
H _CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 AC1
H_CADIP1 L0_CADIN_L0 L0_CADOUT_L0 H_CADOP1
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2
H _CADIN1 F1 AC3 H_CADON1 1 8
L0_CADIN_L1 L0_CADOUT_L1 VDD SMCLK SMB_CK_CLK0 <6,8,9,15,21,30>
0.1U_0402_16V4Z
H_CADIP2 G3 AB1 H_CADOP2 1
H _CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2 NB_THERMAL_DA
G2 AA1 2 7 SMB_CK_DAT0 <6,8,9,15,21,30>
2 H_CADIP3 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP3 C8 C9 DP SMDATA 2
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
H _CADIN3 H1 AA3 H_CADON3 12 NB_THERMAL_DC 3 6 FAN_PWM_R
H_CADIP4 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP4 2 2200P_0402_50V7K DN ALERT#
J1 W2
H _CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4 CPU_THERMTRIP#_R 4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3 <6> CPU_THERMTRIP#_R THERM# GND 5
H_CADIP5 L3 V1 H_CADOP5
H _CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5 HP 3/30
L2 U1
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H _CADIN6 M1 U3 H_CADON6 EMC1402-1-ACZL-TR_MSOP8
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H _CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H _CADIN8 F5 AD3 H_CADON8 change from ADM1032 to EMC1402 12/1
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9 NB_THERMAL_DA
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 <11> NB_THERMAL_DA
H _CADIN9 F4 AC5 H_CADON9 NB_THERMAL_DC address: 4C
L0_CADIN_L9 L0_CADOUT_L9 <11> NB_THERMAL_DC
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 AB3
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 AB5
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 AA5
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 Y5
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
M5 V3
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14
M3 V5
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 T4
H_CADIN15 P5
L0_CADIN_H15
L0_CADIN_L15
L0_CADOUT_H15
L0_CADOUT_L15
T3 H_CADON15 PWM Fan Control
<10>
<10>
H_CLKIP0
H_CLKIN0
J3
J2
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKOUT_H0
L0_CLKOUT_L0
Y1
W1
H_CLKOP0
H_CLKON0
<10>
<10>
circuit
<10> H_CLKIP1 J5 Y4 H_CLKOP1 <10>
L0_CLKIN_H1 L0_CLKOUT_H1
<10> H_CLKIN1 K5 Y3 H_CLKON1 <10>
L0_CLKIN_L1 L0_CLKOUT_L1
3 3
<10> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <10>
<10> H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 <10>
<10> H_CTLIP1 P3 T5 H_CTLOP1 <10>
L0_CTLIN_H1 L0_CTLOUT_H1 +5VS
<10> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <10> +1.8V +5VS
FOX_PZ6382A-284S-41F_GRIFFIN
1
CONN@
Athlon 64 S1
0_0603_5%
1
1
Processor Socket
9/20 SP07000DM00/SP07000EQ00 30K_0402_5% R471
10K_0402_5%
2
R556 R557 +3VS
C10
2
2
1 2 conn@
5
U2 @ 0.1U_0402_10V6K JP1
2
B
Q108 2 1 FAN_PWM_R 1 1
P
<33> FAN_PWM INB 1
R1 3K_0402_5% 4 2 1 2 4
O 2 G1
E
C
3 1 2 R534 2.2K_0402_5% 3 5
<6,46> H_PROCHOT# INA 3 G2
G
PMBT3904_SOT23 for RF, HP 12/10 ACES_85204-03001
3
TC7SH00FU_SSOP5
for Fan shake issue when in 70 degree. Compal 3/23
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4961P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 27, 2009 Sheet 4 of 54
A B C D E
A B C D E
Processor DDR2 Memory Interface
1 JCPU1C 1
<9> DDR_B_D[63..0]
MEM:DATA
DDR_B_D0 DDR_A_D0 DDR_A_D[63..0] <8>
C11 MB_DATA0 MA_DATA0 G12
DDR_B_D1 A11 F12 DDR_A_D1
DDR_B_D2 MB_DATA1 MA_DATA1 DDR_A_D2
A14 H14
DDR_B_D3 MB_DATA2 MA_DATA2 DDR_A_D3
B14 MB_DATA3 MA_DATA3 G14
DDR_B_D4 G11 H11 DDR_A_D4
DDR_B_D5 MB_DATA4 MA_DATA4 DDR_A_D5
E11 MB_DATA5 MA_DATA5 H12
DDR_B_D6 D12 C13 DDR_A_D6
DDR_B_D7 MB_DATA6 MA_DATA6 DDR_A_D7
A13 E13
DDR_B_D8 MB_DATA7 MA_DATA7 DDR_A_D8
A15 MB_DATA8 MA_DATA8 H15
DDR_B_D9 A16 E15 DDR_A_D9
DDR_B_D10 MB_DATA9 MA_DATA9 DDR_A_D10
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