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A B C D E
1 1
Compal Confidential
Schematics Document
2
Arrandale/Clarksfield 2
with Intel IBEX PEAK-M core logic
3
NIWBA 3
REV:0.1
4 4
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NIWBA_LA5371P
Date: Tuesday, March 24, 2009 Sheet 1 of 52
A B C D E
A B C D E
ZZZ1
Compal confidential POWER BD Slide Bar LED X 10 (B) RIGHT BD
File Name : Power on X1 USER-DEFINED (W) VOLUME UP X1
LED X1 (G) DOLBY (W) VOLUME DOWN X1
15.6W_PCB_LA5371P
:POWER LED X 3 MUTE X1
NOVO X1 WIRELESS LED (G) MUTE LED X1(G)
VRAM 64*16 intel BLUETOOTH LED (G)
DDR3*8 Arrandale/Clarksfield 3G LED (G)
1
page20 Clock Generator HDD LED (G)
1
PCI-E X16 (UMA/DIS) (DIS) ICS9LRS3199AKLFT
NVidia N10M-GS page12
NVidia N10P-GS Socket-rPGA989
page19~25
37.5mm*37.5mm DDR3-SO-DIMM X2
switchable level shift IC page5~9 BANK 0, 1, 2, 3 page 10,11
HDMI graphic Dual Channel
CONN 8110T DDR3-800(1.5V) UP TO 8G
page26 page27 100MHz FDI *8 DMI *4
page26 2.7GT/s DDR3-1067(1.5V)
switchable
CRT cable graphic
page28
page28
SPK amplifier 2Channel Speaker
page35 page36
2
LVDS switchable Intel Ibex Peak M 2
graphic WOOFER amplifier 1Channel Speaker
Connector page29
page29
page36
page36
FCBGA 951
PCI Express AZALIA Audio Codec
6*PCI-E BUS 25mm*25mm Realtek ALC272 HP X 1+
Mini card Slot 1 14*USB2.0 MIC_Ext X1page36
page30 page35
PCI Express 2Channel MIC_Int
6*SATA serial page36
Mini card Slot 2
page 13~18 CMOS Camera
page40
page30
PCI Express SPI ROM BlueTooth CONN
BIOS page38 LPC BUS page40
Mini card Slot 3
3
page30 USB CONN X1 3
page40
BCM57790/57780
EC
ENE KB926D New Card X1
SIM Card 10/100/1G LAN page37 page29
page31
Realtek 5159E
page30
M-PCIE CONN X 3 MS/MS
page29
pro/SD/SD
RJ45 CONN Int.KBD pro/mmc/XD page33
page32 page38
Touch Pad SPI ROM
page39
page39 ESATA HDD AND USB CONN
page34
SATA HDD CONN
4
page34 4
SATA ODD CONN
page34
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/24 Deciphered Date 2008/04/ Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NIWBA_LA5371P
Date: Tuesday, March 24, 2009 Sheet 2 of 52
A B C D E
A B C D E
DDR3 Voltage Rails
SMBUS Control Table
N10x NEW
WLAN Thermal Cap sensor CARD PCH
SOURCE RAM M2 BATT KE926 SODIMM CLK CHIP WWAN N10x board
+5VS Sensor
+3VS SMB_EC_CK1
power
+1.5VS SMB_EC_DA1
KB926 X V
+3VALW
X X X X X X X X X
plane +3VALW
+VCCP SMB_EC_CK2
1
+5VALW +1.5V +CPU_CORE SMB_EC_DA2
KB926 X X X X X X X X X X V 1
+3VALW +3VALW
+B +VGA_CORE SMBCLK
+3VALW +1.8VS SMBDATA
PCH V X X V
+3VS +3VS
V X X X X +3VS
V X
+3VALW +3VALW
+0.75VS SML0CLK
State +1.05VS SML0DATA
PCH
+3VALW
X X X X X X X X X X X
SML1CLK
SML1DATA
PCH
+3VALW
X X V X X X +3VS
V X V
+3VS
X X
+3VALW
S0
O O O O
I2C / SMBUS ADDRESSING
S3
O O O X
2
S5 S4/AC DEVICE HEX ADDRESS 2
O O X X
DDR SO-DIMM 0 A0 10100000
S5 S4/ Battery only DDR SO-DIMM 1 A4 10100100
O X X X
CLOCK GENERATOR (EXT.) D2 11010010
S5 S4/AC & Battery
don't exist X X X X
@ FUNCTION
EVT NON-USE
45@ (45 BOM)
GIGA@ (GIGA LAN) 100@ (100 LAN)
PCIE PORT LIST USB PORT LIST
NO_TVSW@ (NON TV POWER SW) TVSW@ (TV POWER SW)
3 PORT DEVICE PORT DEVICE 3
ARRAY@ (ARRAY MIC) MONO@ (MONO MIC)
1 NEW CARD 0 LEFT SIDE
S512@ FOR X76 BOM 2 WLAN 1 RIGHT SIDE
H512@ FOR X76 BOM 3 LAN 2 CMOS
4 3G 3
S1024@ FOR X76 BOM 5 4 RIGHT SIDE
H1024@ FOR X76 BOM 6 TV TUNNER 5 CARD READER
7 6
X76@ (X76 BOM) 8 7
M1@ (DDR M1 MODE) 8 WIRELESS
9 TV TUNNER
3G@ (3G MODE) 10 NEW CARD
10M@ FOR 10M CHIP 11 BT
12
10P@ FOR 10P CHIP 13 3G
4
UMA@ FOR Auberndale 4
FOR Auberndale/Clarksfield
DIS@
VGA@ FOR NVIDIA PART
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/24 Deciphered Date 2008/04/ Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NIWBA_LA5371P
Date: Tuesday, March 24, 2009 Sheet 3 of 52
A B C D E
A B C D E
VGA and DDR3 Voltage Rails (N10x GPIO) Performance Mode P0 TDP at Tj = 102 C* (DDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.5V) (1.5V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 N/A N/A Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO1 IN - Hot plug detect for IFP link C N10P-GS
128bit 21.07 6.67 TBD TBD 18.25 17.34 2.06 3.09 4.09 6.14 850 0.89 75 0.14 63 0.07 55 0.18
1024MB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) DDR3
1 1
GPIO3 OUT H Panel Power Enable N10P-GE
128bit 20.97 6.73 TBD TBD 19.17 17.25 2.03 3.05 4.09 6.14 840 0.88 75 0.14 63 0.07 55 0.18
1024MB
GPIO4 OUT H Panel Back-Light On/Off (PWM) DDR3
GPIO5 OUT - GPU VID0 N10P-LP
128bit 15.48 6.44 TBD TBD 13.95 11.86 1.90 2.85 3.99 5.99 810 0.85 75 0.14 63 0.07 55 0.18
1024MB
GPIO6 OUT - GPU VID1 DDR3
GPIO7 OUT - GPU VID2
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO8 I/O L Thermal Catastrophic Overtemp
FBVDDQ PCI Express I/O and I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
GPIO9 OUT L Thermal Alert (4) (1,5) /MCLK NVVDD (1.5V) (1.5V) (6) (1.8V) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO10 OUT Memory VREF switch
N10M-GE
GPIO11 I/O L SLI raster sync 64bit 13.36 2.93 TBD TBD 11.89 10.70 0.66 0.99 2.16 3.24 792 0.83 75 0.14 63 0.07 100 0.33
512MB
DDR3
GPIO12 IN - AC power detect pin
N10M-GS
2
GPIO13 OUT - MEM_VID orPower supply control 64bit 14.29 3.10 TBD TBD 11.53 11.53 0.70 1.05 2.28 3.42 817 0.86 75 0.14 63 0.07 100 0.33 2
512MB
DDR3
GPIO14 OUT - Power supply control
N10M-LP
GPIO15 IN - Hot plug detect for IFP Link E 64bit 8.28 2.91 TBD TBD 6.60 5.61 0.62 0.93 2.20 3.3 782 0.82 75 0.14 63 0.07 100 0.33
512MB
DDR3
GPIO16 OUT - Programmable Fan Control
GPIO17 IN - The ramp time for any rail must be more than 40us
Power Sequence
GPIO18 IN -
GPIO19 IN - Hot plug detect for IFP Link D
GPIO20 IN - (+3VS) VDD33
GPIO21 IN - Hot plug detect for IFP link F
PEX_VDD can ramp up any time
GPIO22 IN - SLI swap ready signal
(1.1VS) PEX_VDD
GPIO23 I/O
tNVVDD
3 3
(+VGA_CORE) NVVDD
GPIO6 GPIO5 N10M-GS N10P-GS
GPU_VID1 GPU_VID0 VGA_CORE P-State tNV-IFPAB_IOVDD
0 0 0.8V 12
0 1 0.85V 12 IFPAB_IOVDD
1 1 0.9V 0, 10
tNV-FBVDDQ
(1.8VS) FBVDDQ
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/03/16 Deciphered Date 2010/03/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4602P
Date: Tuesday, March 24, 2009 Sheet 4 of 52
A B C D E
5 4 3 2 1
D
Layout rule 10mil width trace
length < 0.5", spacing 20mil
D
JCPU1B
20_0402_1% 1 R833 2COMP3 AT23 COMP3
A16 CLK_CPU_BCLK DDR3 Compensation Signals
BCLK CLK_CPU_BCLK <16>
MISC
20_0402_1% 1 R834 2COMP2 AT24 B16 CLK_CPU_BCLK#
COMP2 BCLK# CLK_CPU_BCLK# <16>
49.9_0402_1% 1 R835 2COMP1 SM_RCOMP0
CLOCKS
G16 COMP1 BCLK_ITP AR30 1 2
AT30 R836 100_0402_1%
BCLK_ITP#
49.9_0402_1% 1 R837 2COMP0 AT26 COMP0
SM_RCOMP1 1 2
E16 CLK_EXP R838 24.9_0402_1%
PEG_CLK CLK_EXP <14>
D16 CLK_EXP# SM_RCOMP2 1 2
PEG_CLK# CLK_EXP# <14>
TP_SKTOCC# AH24 R839 130_0402_1%
SKTOCC#
DPLL_REF_SSCLK A18 pins unused by Layout Note:Please these
A17
2 1 H_CATERR# AK14
DPLL_REF_SSCLK# Clarksfield on the resistors near Processor
+VCCP CATERR#
THERMAL
50_0402_1% R840 rPGA989 Package
R841 0_0402_5% F6
SM_DRAMRST# DRAMRST# <10,11>
<16> H_PECI 1 2 H_PECI_ISO AT15 PECI
AL1 SM_RCOMP0
SM_RCOMP[0] SM_RCOMP1 +VCCP
+VCCP 2 R842 1 68_0402_5% SM_RCOMP[1] AM1
AN1 SM_RCOMP2
H_PROCHOT# SM_RCOMP[2] PM_EXTTS#0
<51> H_PROCHOT# AN26 PROCHOT# 1 2
AN15 PM_EXTTS#0 R843 10K_0402_5%
PM_EXT_TS#[0]
DDR3
MISC
AP15 PM_EXTTS#1 1 2 PM_EXTTS#1 1 2
PM_EXT_TS#[1] PM_EXTTS#1_R <10,11>
R844 0_0402_5% R845 10K_0402_5%
H_THERMTRIP#_R AK15
<16> H_THERMTRIP# THERMTRIP#
PRDY# AT28
C AP27 XDP_PREQ# XDP_PREQ# R846 1 @ 2 51_0402_1% C
PREQ#
AN28 XDP_TCK XDP_TMS R847 1 @ 2 51_0402_1%
TCK
+VCCP 2 1 H_CPURST#_R AP26 RESET_OBS# TMS AP28 XDP_TMS
PWR MANAGEMENT
PWR MANAGEMENT
68_0402_5% R848 AT27 XDP_TRST# XDP_TDI R849 1 @ 2 51_0402_1%
TRST#
JTAG & BPM
+1.5V 1 R850 2 H_PM_SYNC_R AL15 AT29 XDP_TDI XDP_TDO R851 1 2 51_0402_5%
<15> H_PM_SYNC PM_SYNC TDI
0_0402_5% AR27 XDP_TDO
TDO
TDI_M AR29
2
1 R852 2 VCCPWRGOOD_1 AN14 VCCPWRGOOD_1 TDO_M AP29 R853 2 1 0_0402_5% XDP_TCK R854 1 @ 2 51_0402_1%
R855 0_0402_5%
4.75K_0402_1% AN25 XDP_DBRESET# XDP_TRST# R856 1 2 51_0402_5%
DBR#
<16> H_CPUPWRGD 1 R857 2 VCCPWRGOOD_0 AN27 VCCPWRGOOD_0
0_0402_5%
1
AJ22 XDP_BPM#0
VDDPWRGOOD_R BPM#[0]
1.07V <15> PM_DRAM_PWRGD 1 R858 2 VDDPWRGOOD_R AK13 SM_DRAMPWROK BPM#[1] AK22 XDP_BPM#1 R859
0_0402_5% AK24 XDP_BPM#2 XDP_DBRESET# 1 @ 2 1K_0402_5% +3VS
BPM#[2] XDP_BPM#3
BPM#[3] AJ24
1
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