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A B C D E
1 1
Compal confidential
2
Hamburg 10AD 2
NALAE LA-6053P Schematics Document
Mobile AMD S1G4/ RS880M / SB820M
3 3
2009-02-04 Rev. 0.2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6053
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401870 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 1 of 42
A B C D E
A B C D E
Compal Confidential Thermal Sensor Fan Control AMD S1G4 CPU
Memory BUS(DDRIII)
200pin DDRIII-SO-DIMM X2
page 5 Dual Channel
ADM1032ARMZ page 7 BANK 0, 1, 2, 3 page 9,10
Model Name : NALAE uFCPGA-638 Package 1.5V DDRIII 1066/1333MHZ
File Name : LA-6053P page 5,6,7,8
1 Hyper Transport Link 2.6GHz 1
16X16 PCI-e Mini Card WLAN
PCIe Port 2
CRT
page 17 USB Port 8 page 28
AMD
LCD Conn.
page 18 RS880M PCIe 4x
1.5V 2.5GHz(250MB/s)
HDMI Conn.
page 19
page 11,12,13,14,15
RTL 8105E 10/100M RJ45
PCIe port 3 page 26
2 2
A-Link Express II page 26
4X PCI-E
SATA port 0 SATA HDD
5V 1.5GHz(150MB/s) page 25
AMD
USB/B Card Reader
USB port 0,1 USB port 5 SATA port 1 SATA ODD
page 28 page 27
USB
SB820M 5V 1.5GHz(150MB/s) page 25
5V 480MHz
BT conn Int. Camera SATA port 3
USB port 6 USB port 9 5V 1.5GHz(150MB/s)
page 28 page 18 eSATA
USB port 2 page 25
5V 480MHz
page 20,21,22,23,24
3 3
Clock Generator
SLG8SP626 HD Audio 3.3V 24.576MHz/48Mhz
page 16
LPC BUS
3.3V 33 MHz
RTC CKT. ODD/B MDC 1.5 Conn HDA Codec
page 20 Page 25 ALC259Q
Debug Port ENE KB926 D3 page 32 page 29
page 32 page 31
Power On/Off CKT. Power/B
Page 33
page 33
Audio & USB/B Int.KBD SPI ROM Int.
MIC CONN MIC CONN HP CONN SPK CONN
DC/DC Interface CKT. Page 33 page 32 page 32 page 18 page 30 page 30 page 30
page 34
LED/B
Page 33
Power Circuit DC/DC
4
page 35,36,37.38,39 Touch Pad/B 4
40,41 Page 33
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6053
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401870 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 2 of 42
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.1A +3VL
DESIGN CURRENT 0.1A +5VL
B+
RT8205EGQW Ipeak = 5A, Imax = 3.5A, Iocp_min = 7.7A DESIGN CURRENT 5A +3VALW
Ipeak = 5A, Imax = 3.5A, Iocp_min = 7.9A DESIGN CURRENT 5A +5VALW
SUSP
D D
N-CHANNEL DESIGN CURRENT 2A +5VS
SI4800
SUSP#
DESIGN CURRENT 2.5A +1.8VS
MP2121DQ
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
SUSP
DESIGN CURRENT 1.5A +3VS
N-CHANNEL
SI4800
ENVDD
P-CHANNEL DESIGN CURRENT 1A +LCD_VDD
C C
AO-3413
NALAE Hamburg AMD UMA
BT_PWR#
P-CHANNEL DESIGN CURRENT 180mA +BT_VCC
AO-3413
DESIGN CURRENT 300mA +2.5VS
APL5508
POK
Ipeak = 12A, Imax = 8.4A, Iocp_min = 18.7A DESIGN CURRENT 12A +1.1VALW
RT8209BGQW
VLDT_EN#
N-CHANNEL DESIGN CURRENT 3.5A +1.1VS
IRF8113
VLDT_EN#
N-CHANNEL DESIGN CURRENT 6A +NB_CORE
VR_ON
B IRF8113 B
Ipeak = 36A, Imax = 25.2A, Iocp_min = 54A DESIGN CURRENT 36A +CPU_CORE0
ISL6265A DESIGN CURRENT 4A +VDDNB
SYSON
Ipeak = 7.5A, Imax = 5.25A, Iocp_min = 8.7A DESIGN CURRENT 7.5A +1.5V
RT8209BGQW SUSP
N-CHANNEL DESIGN CURRENT 1A +1.5VS
IRF8113
SUSP
DESIGN CURRENT 1A +0.75VS
APL5331KAC
VR_ON#
A DESIGN CURRENT 1.5A A
+1.05VS
APL5331KAC
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6053
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401870 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 3 of 42
5 4 3 2 1
A B C D E
Voltage Rails
Platform CPU NB VGA SB Comment
O : ON
S1G4 RS880M NA SB820M
X : OFF Danube
+5VS
1 1
power +3VS @ : just reserve , no build
plane +2.5VS
+1.8VS
+1.5VS
B+ +5VALW +1.1VS
+3VL +1.05VS
+3VALW +1.5V
+5VL +0.75VS
State
+RTCVCC +1.1VALW +VDDNB
+CPU_CORE
+NB_CORE
S0 O O O O
S1 O O O O BTO (Build-To-Order) Option Table
2 2
S3 Function BLUE TOOTH HDMI
O O O X
Description (B) (Y)
S5 S4/AC O O X X Explain
S5 S4/ Battery only O X X X BTO BT@ H@
S5 S4/AC & Battery
don't exist X X X X
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS SMBUS Control Table
3
DDR SO-DIMM 0 A0 10100000 CPU 3
SOURCE BATT SODIMM CLK LCD HDMI
DDR SO-DIMM 1 A2 10100010 THERMAL GEN WLAN DDC DDC
I / II
CLOCK GENERATOR (EXT.) D2 11010010 SENSOR ROM ROM
EC_SMB_CK1
KB926
EC_SMB_DA1 V
EC_SMB_CK2
KB926
EC_SMB_DA2 V
EC SM Bus1 address EC SM Bus2 address I2C_CLK
RS880M
I2C_DATA V
Device HEX Address Device HEX Address
DDC_CLK0
Smart Battery 16H 0001 011X b ADI1032-1 CPU 98H 1001 100X b RS880M
DDC_DATA0 V
HDMI-CEC 34H 0011 010X b ADI1032-2 VGA 9AH 1001 101X b
SCL0
EC KB926D3 EC KB926D3 SB820
SDA0 V V
SCL1
SB820
SDA1 V
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6053
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401870 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 4 of 42
A B C D E
A B C D E
+1.1VS
250 mil VLDT CAP. Near CPU Socket
1 1 1 1 1 1
C1 C2 C3 C4 C5 C6 H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADOP[0..15] <11>
10U_0805_10V4Z 10U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J H_CADIN[0..15] H_CADON[0..15]
2 2 2 2 2 2 <11> H_CADIN[0..15] H_CADON[0..15] <11>
1 1
+1.1VS
+1.1VS
JCPUA
C7
D1 HT LINK AE2 +VLDT_B 1 2 10U_0805_10V4Z < VLDT_A & VLDT_B : HyperTransport I/O ring power >
VLDT_A0 VLDT_B0
VLDT=500mA D2 VLDT_A1 VLDT_B1 AE3
D3 VLDT_A2 VLDT_B2 AE4 C7 close to cpu pin
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
2 H_CADIP6 H_CADOP6 2
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H_CADIN6 M1 U3 H_CADON6
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
< From NB > F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 < To NB >
H_CADIN9 F4 AC5 H_CADON9
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
H_CADIN11 H4 AA5 H_CADON11
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
H_CADIN12 K4 W5 H_CADON12
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 L0_CADIN_H13 L0_CADOUT_H13 V4
H_CADIN13 M5 V3 H_CADON13
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14
M3 L0_CADIN_H14 L0_CADOUT_H14 V5
H_CADIN14 M4 U5 H_CADON14
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15
<11> H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 <11>
<11> H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 <11>
<11> H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 <11>
<11> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <11>
<11> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <11>
<11> H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 <11>
<11> H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 <11>
<11> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <11>
3 FOX_PZ6382A-284S-41F_Champlian 3
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
1A
2
+FAN1 C1119
JFAN +3VS
1
C1120 10U_0805_10V4Z +FAN1 1
1 1
2 2
1
10U_0805_10V4Z 2 3
2 U31 C1121 3 R795
1 8 @ 4
EN GND 1000P_0402_25V8J GND 10K_0402_5%
2 VIN GND 7 5 GND
1
3 6
2
VOUT GND @ ACES_85204-0300N
<30> EN_DFAN1 4 VSET GND 5 FAN_SPEED1 <30>
2
4 APL5607KI-TRG_SO8 C1122 4
@
0.01U_0402_25V7K
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6053
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401870 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 5 of 42
A B C D E
A B C D E
< DDR3 VREF is 0.5 ratio > < Processor DDR3 Memory Interface >
+1.5V
Close to CPU
2
R1 JCPUC
<10> DDR_B_D[63..0]
MEM:DATA
DDR_A_D[63..0] <9>
1K_0402_1% < From/To SO_DIMMB > DDR_B_D0 C11 G12 DDR_A_D0
DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1
A11 F12 < From/To SO_DIMMA >
1
+MCH_REF DDR_B_D2 MB_DATA1 MA_DATA1 DDR_A_D2
A14 MB_DATA2 MA_DATA2 H14
DDR_B_D3 B14 G14 DDR_A_D3
MB_DATA3 MA_DATA3
2
1 1 DDR_B_D4 G11 H11 DDR_A_D4
R2 C9 C8 DDR_B_D5 MB_DATA4 MA_DATA4 DDR_A_D5
E11 MB_DATA5 MA_DATA5 H12
1 DDR_B_D6 DDR_A_D6 1
D12 MB_DATA6 MA_DATA6 C13
1K_0402_1% 0.1U_0402_16V7K 1000P_0402_25V8J DDR_B_D7 A13 E13 DDR_A_D7
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