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A B C D E
ZZZ2 JDCIN1 ZZZ1 ZZZ3 ZZZ4 ZZZ5 ZZZ6
PCB DCIN Cable LA-6101P LS-6101P LS-6102P LS-6103P LS-6104P
DAZ@ 45@ M/B FUN/B FP/B LED/B PWR/B
DA2@ DA2@ DA2@ DA2@ DA2@
11/03 Add DC-IN Cable P/N : DC301009N00 12/04 Change PJP1 to JDCIN1
1 1
11/18 Change PCB P/N from DA60000G300 to DA60000G200
02/26 Change LA-6101P P/N from DA60000G200 to DA60000G210
02/26 Add DAZ P/N and other small board P/N
02/26 Change DAZ P/N from DAZ0D9001001 to DAZ0D900101
Compal Confidential
2 NAU00 LA-6101P Schematics Document 2
Intel Arrandale Processor with DDRIII + Ibex Peak-M
SV M/B
3
2010-03-09 3
Rev : 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 1 of 48
A B C D E
A B C D E
Compal Confidential
Model Name : NAU00
File Name : LA-6101P
1
Intel Memory Bus (DDRIII)
1
Clock Generator Fan Control Dual Channel 204 Pin DDRIII SO-DIMM x2
Arrandale
IDT: 9LRS3199AKLFT Page 37 SV 1.5V DDRIII 800/1066/1333 BANK 0, 1, 2, 3
SILEGO: SLG8SP587
Processor 6.4G/8.5G/10.6G
133/120/100/96/14.318MHZ to PCH Page 10,11
100M/133M/166M(CFD)
48MHZ to CardReader
Page 12 rPGA988A
Page 4,5,6,7,8,9
HDMI Conn. CRT Conn. LVDS Conn.
Page 24 Page 23 Page 22
FDI x8 DMI x4 USB Conn.x3 CardReader Bluetooth Camera FingerPrint
100MHz 100MHz Port 0,3 (USB) Realtek RTS5138 Port 11 Port 2 UPEK TCS5BB6A2
1GB/s x4 2.7GT/s Port 1 (eSATA) Port 5 Port 9
Page 31 Page 28 Page 35 Page 22 Page 36
2
HDMI Level Shifter 2
ASmedia AM1442T LVDS USB
Page 24
3.3V 48MHz
Intel
CRT HD Audio 3.3V 24MHz
Ibex Peak-M
HDMI SATA Gen1 1.5GT/S ,Gen2 3GT/S 100MHz 3G Card
PCH Port 13
100MHz ABD PCIE Gen1 2.5GT/S PCI-Express X1 FCBGA 1071Pin SPI Page 32
Port Port Port Page 13,14,15,16,17,18,19,20,21
New Card Mini Card LAN(GbE) BIOS ROM HDD SSD e-SATA Conn.
Port 3 WLAN Atheros 8151
Page 37
4MB Port 0 Port 1,5 Port 4
Port 2 Port 1
Page 32 Page 26 LPC Mini card slot
Page 13 Page 25 Page 32 Page 31
3 33MHz 3
HDA Codec
Realtek ALC259
RJ-45 Page 29
Page 27
CPU XDP ENE KB926E0
Page 35 Page 33
Small Board
Int. Speaker
Phone Jack x 2
Int. Digital MIC
RTC Ckt. Power/B Thinklight/B Page 30 Page 30
Page 35 Touch Pad Int.KBD
Page 35 Page 36
LS-6104P LS-6103P
Power On/Off Ckt.
Page 34
EC I/O Buffer EC ROM Function/B FP/B
Page 33 128kB Page 36 LS-6101P LS-6102P
4
DC/DC Interface Ckt. 4
Page 38
Power Ckt. G-Sensor Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
Page 34 Page 25 Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Friday, February 26, 2010 Sheet 2 of 48
A B C D E
A B C D E
Voltage Rails SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON ON OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+1.05VS 1.05V switched power rail for PCH ON OFF OFF
+1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.5V 1.5V power rail for DDRIII ON ON OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8VS 1.8V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+3VALW 3.3V always on power rail ON ON ON* Vcc 3.3V +/- 5%
+3V 3.3V power rail for PCH ON ON ON Ra/Rc/Re 100K +/- 5%
+3V_LAN 3.3V power rail for LAN ON ON ON* Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+5VALW 5V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5V 5V power rail for PCH ON ON ON 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+VSB VSB always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+RTCVCC RTC power ON ON ON 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
7 NC 2.500 V 3.300 V 3.300 V
2 2
BOARD ID Table
Board ID PCB Revision
External PCI Devices * 0 0.1
Device IDSEL# REQ#/GNT# Interrupts 1
2
3
4
5
6
7
EC SM Bus1 address EC SM Bus2 address
3 3
Device Address Device Address
Smart Battery 0001 011X b
Ibex SM Bus address
Device Address
Clock Generator 1101 0010b
(9LRS3199AKLFT, SLG8SP587)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
ISL90727 0101 1100b
ISL90728 0111 1100b
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Friday, February 26, 2010 Sheet 3 of 48
A B C D E
5 4 3 2 1
JCPU1E
JCPU1A R1 AJ13
PEG_IRCOMP RSVD32
PEG_ICOMPI B26 1 2 49.9_0402_1% RSVD33 AJ12
PEG_ICOMPO A26
DMI_PTX_HRX_N0 A24 B27 R2 AP25
DMI_PTX_HRX_N1 DMI_RX#[0] PEG_RCOMPO EXP_RBIAS RSVD1
C23 DMI_RX#[1] PEG_RBIAS A25 1 2 750_0402_1% AL25 RSVD2 RSVD34 AH25
DMI_PTX_HRX_N2 B22 AL24 AK26
DMI_PTX_HRX_N3 DMI_RX#[2] RSVD3 RSVD35
A21 DMI_RX#[3] PEG_RX#[0] K35 AL22 RSVD4
PEG_RX#[1] J34 AJ33 RSVD5 RSVD36 AL26
DMI_PTX_HRX_P0 B24 J33 AG9 AR2
DMI_PTX_HRX_P1 DMI_RX[0] PEG_RX#[2] RSVD6 RSVD_NCTF_37
D23 DMI_RX[1] PEG_RX#[3] G35 M27 RSVD7
DMI
DMI_PTX_HRX_P2 B23 G32 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 J17 SA_DIMM_VREF (CFD Only) RSVD39 AJ27 D
PEG_RX#[6] F31 H17 SB_DIMM_VREF (CFD Only)
DMI_HTX_PRX_N0 D24 D35 G25
DMI_HTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] RSVD11
G24 DMI_TX#[1] PEG_RX#[8] E33 G17 RSVD12
DMI_HTX_PRX_N2 F23 C33 E31 AP1
DMI_HTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] RSVD13 RSVD_NCTF_40
H23 DMI_TX#[3] PEG_RX#[10] D32 E30 RSVD14 RSVD_NCTF_41 AT2
PEG_RX#[11] B32
DMI_HTX_PRX_P0 D25 C31 AT3
DMI_HTX_PRX_P1 DMI_TX[0] PEG_RX#[12] RSVD_NCTF_42
F24 DMI_TX[1] PEG_RX#[13] B28 RSVD_NCTF_43 AR1
DMI_HTX_PRX_P2 E23 B30
DMI_HTX_PRX_P3 DMI_TX[2] PEG_RX#[14]
G23 DMI_TX[3] PEG_RX#[15] A31
PEG_RX[0] J35 RSVD45 AL28
PEG_RX[1] H34 AM30 CFG[0] RSVD46 AL29
PEG_RX[2] H33 AM28 CFG[1] RSVD47 AP30
H_FDI_TXN0 E22 F35 AP31 AP32
H_FDI_TXN1 FDI_TX#[0] PEG_RX[3] CFG[2] RSVD48
D21 FDI_TX#[1] PEG_RX[4] G33 AL32 CFG[3] RSVD49 AL27
H_FDI_TXN2 D19 E34 AL30 AT31
H_FDI_TXN3 FDI_TX#[2] PEG_RX[5] CFG[4] RSVD50
D18 FDI_TX#[3] PEG_RX[6] F32 AM31 CFG[5] RSVD51 AT32
H_FDI_TXN4 G21 D34 AN29 AP33
H_FDI_TXN5 FDI_TX#[4] PEG_RX[7] CFG[6] RSVD52
PCI EXPRESS -- GRAPHICS
E19 FDI_TX#[5] PEG_RX[8] F33 AM32 CFG[7] RSVD53 AR33
H_FDI_TXN6 F21 B33 AK32 AT33
FDI_TX#[6] PEG_RX[9] CFG[8] RSVD_NCTF_54
Intel(R) FDI
H_FDI_TXN7 G18 D31 AK31 AT34
RESERVED
FDI_TX#[7] PEG_RX[10] CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 11/12 Delete R3(@),R4(@),R5(@),R6(@) AK28 CFG[10] RSVD_NCTF_56 AP35
PEG_RX[12] C30 AJ28 CFG[11] RSVD_NCTF_57 AR35
H_FDI_TXP0 D22 A28 AN30 AR32
H_FDI_TXP1 FDI_TX[0] PEG_RX[13] CFG[12] RSVD58
C21 FDI_TX[1] PEG_RX[14] B29 AN32 CFG[13]
H_FDI_TXP2 D20 A30 AJ32
H_FDI_TXP3 FDI_TX[2] PEG_RX[15] CFG[14]
C18 FDI_TX[3] AJ29 CFG[15] RSVD_TP_59 E15
C H_FDI_TXP4 G22 L33 AJ30 F15 C
H_FDI_TXP5 FDI_TX[4] PEG_TX#[0] CFG[16] RSVD_TP_60
E20 FDI_TX[5] PEG_TX#[1] M35 AK30 CFG[17] KEY A2
H_FDI_TXP6 F20 M33 H16 D15 11/17 Delete R7,R8
H_FDI_TXP7 FDI_TX[6] PEG_TX#[2] RSVD_TP_86 RSVD62
G19 FDI_TX[7] PEG_TX#[3] M30 RSVD63 C15
PEG_TX#[4] L31 RSVD64 AJ15
<15> H_FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32 RSVD65 AH15
<15> H_FDI_FSYNC1 E17 FDI_FSYNC[1] PEG_TX#[6] M29
PEG_TX#[7] J31 B19 RSVD15
<15> H_FDI_INT C17 FDI_INT PEG_TX#[8] K29 11/17 Delete R9,R10 A19 RSVD16
PEG_TX#[9] H30
<15> H_FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29 A20 RSVD17
<15> H_FDI_LSYNC1 D17 FDI_LSYNC[1] PEG_TX#[11] F29 B20 RSVD18
PEG_TX#[12] E28 RSVD_TP_66 AA5
PEG_TX#[13] D29 U9 RSVD19 RSVD_TP_67 AA4
PEG_TX#[14] D27 T9 RSVD20 RSVD_TP_68 R8
PEG_TX#[15] C26 RSVD_TP_69 AD3
AC9 RSVD21 RSVD_TP_70 AD2
PEG_TX[0] L34 AB9 RSVD22 RSVD_TP_71 AA2
PEG_TX[1] M34 RSVD_TP_72 AA1
PEG_TX[2] M32 RSVD_TP_73 R9
PEG_TX[3] L30 RSVD_TP_74 AG7
PEG_TX[4] M31 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
PEG_TX[5] K31 A3 RSVD_NCTF_24
PEG_TX[6] M28
PEG_TX[7] H31 RSVD_TP_76 V4
PEG_TX[8] K28 RSVD_TP_77 V5
PEG_TX[9] G30 RSVD_TP_78 N2
PEG_TX[10] G29 J29 RSVD26 RSVD_TP_79 AD5
PEG_TX[11] F28 J28 RSVD27 RSVD_TP_80 AD7
B B
PEG_TX[12] E27 RSVD_TP_81 W3
PEG_TX[13] D28 A34 RSVD_NCTF_28 RSVD_TP_82 W2
PEG_TX[14] C27 A33 RSVD_NCTF_29 RSVD_TP_83 N3
PEG_TX[15] C25 RSVD_TP_84 AE5
C35 RSVD_NCTF_30 RSVD_TP_85 AD9
B35 RSVD_NCTF_31
IC,AUB_CFD_rPGA,R1P0 AP34
CONN@ VSS
DMI_PTX_HRX_N[0..3] <15>
DMI_PTX_HRX_P[0..3] <15>
IC,AUB_CFD_rPGA,R1P0
DMI_HTX_PRX_N[0..3] <15>
CONN@
DMI_HTX_PRX_P[0..3] <15>
H_FDI_TXN[0..7] <15>
H_FDI_TXP[0..7] <15> CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence
*1:Single PEG *1:Disabled; No Physical Display Port
0:Bifurcation enabled attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
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