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A B C D E
1 1
2
Compal Confidential 2
QAZ00 (Shuriken 13.3) M/B Schematics Document
Intel Sandy Bridge ULV Processor with DDRIII + Cougar Point PCH SFF
3 LA-7531P Date : 2011/04/10 3
Version 0.1 modify
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/03 Deciphered Date Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-7531P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, April 10, 2011 Sheet 1 of 45
A B C D E
A B C D E
Memory BUS(DDRIII)
Compal Confidential Intel
1.5V DDRIII 1066/1333/1600 for CR
1.5V DDRIII 1066/1333 for HR
1 1
Model Name :QAZ00 Shuriken 13.3 Sandy & Ivy Bridge Channel A SODIMM
SP07000NN00
SA000042410 Page 11
File Name : LA-7531P eDP (Reserved)
ULV Processor
FCBGA 1023
2011/04/10 Page 4~10
FDI x8 DMI x4
LVDS Conn. 100MHz USB 2.0 or
100MHz
HDMI Conn. 1GB/s x4 3.0 X1
Page 20 Page 23 2.7GT/s
Power USB 1W CMOS
LVDS(UMA) USB 3.0 x4 X1 X1
Camera
Intel Page 23
HDMI(UMA) USB 2.0 x14
2 PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
CP & PP -M 3.3V 48MHz X1
2
100MHz
SA000043Z00 HD Audio 3.3V 24MHz
X1
X1 X1 100MHz
PCH SFF
X1 X1 1017 pin BGA USB 2.0 X1
SATA x 6 (GEN1 Page 12~19 SPI
1.5GT/S ,GEN2 3GT/S) HDA Codec AUDIO HP
LAN(Gbe) ALC269Q & MIC
Card Reader RTL8111E-VL
MINI Card x1 MINI Card x1 mSATA(MINI Page 29
WLAN WWAN (3G) BIOS SPI ROM x1,
RTS5209 Card) SATA 4MB,U48 Power Page 26
Page 21 Page 22 mSATA
Page 25
Page22 Conn. Page 24 Page 12 Button LS-7531P
JMINI3 JMINI2 JMINI1 Mic1 (Analog)
X1 X1 X1 USB 2.0 Bus Page 29
LPC BUS
33MHz
RJ45 Power
Page 21 ENE KB930
3
PS2 Button 3
/9012 Page 27 Page 28
SMBus SPI
Touch Pad
Int.KBD EC ROM
HID Sensor Page 28 -SPI
Page 27
LEDs
4
LS-7532P 4
Page 28
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/05/28 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7531P
Date: Sunday, April 10, 2011 Sheet 2 of 45
A B C D E
A B C D E
QAZ00 (LA-7531P Ver:0.1)
Voltage Rails
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
VIN Adapter power supply (19V) N/A N/A N/A
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1 +CPU_CORE Core voltage for CPU ON OFF OFF 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS_VCCP +V1.05SP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+VCCP +VCCP (1.05V ) power for PCH ON OFF OFF
+1.5V +1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V) ON ON OFF
+1.5VS +1.5VS switched power rail ON OFF OFF
+1.8VS (+5VALW ) to 1.8V switched power rail to PCH & GPU ON OFF OFF
+3VALW +3VALW always on power rail ON ON ON*
+3VALW_EC +3VALW always to KBC ON ON ON*
+LAN_IO +3VALW to +LAN_IO power rail for LAN ON ON ON*
+3V_PCH +3VALW to +3V_PCH power rail for PCH (Short Jumper) ON ON ON*
EC SM Bus1 address
+3VS +3VALW to +3VS power rail ON OFF OFF
+5VALW +5VALWP to +5VALW power rail ON ON ON* Device Address EC SM Bus2 address
+5V_PCH +5VALW to +5V_PCH power rail for PCH (Short resister) ON ON ON* Smart Battery 0001 011X b
Device Address
+5VS +5VALW to +5VS switched power rail ON OFF OFF
PCH (Reserve) 1010 0110b
2 +VSB B+ to +VSB always on power rail for sequence control ON ON ON* 2
PCH SM Bus address
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Device Address
DDR DIMM0 1010 0000b
Mini Card1
Mini Card2
Mini Card3
SMBUS Control Table 2011/04/07 Modify
EC_SMB_CK2 PCH_SMBCLK
BATT CLKOUT DESTINATION
SOURCE MIINI1 MINI2 MINI3 SODIMM PCH_SMBDATA PCH_SMBDATA
PCI0 PCH_LPBACK
EC_SMB_CK1
EC_SMB_DA1
KB930 V X X X X X X
PCI1 PCI_LPC
EC_SMB_CK2
EC_SMB_DA2
KB930 X X X X X O V USB Port Table 2011/04/09 Check
PCI2 None
PCH_SMBCLK 2 External
PCH_SMBDATA PCH X V V V V V O PCI3 None
USB 2.0 USB 1.1 Port
USB Port
3
SATA DESTINATION 0 3
PCH_SMLCLK PCH UHCI0
PCH_SMLDATA X X X X X X X PCI4 None
SATA0 m-SATA,JMINI1
1 USB/B (Right Side)
2
UHCI1
3 Camera
SATA1 m-SATA,JMINI2 EHCI1
4 Mini Card(WLAN)
UHCI2
5 WWAN (3G)
SATA2 None 6
UHCI3
DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION 7 mSATA
SATA3 None 8
UHCI4
CLKOUT_PCIE0 None CLKOUTFLEX0 None 9 USB/B (Right Side)
SATA4 None 10
EHCI2 UHCI5
CLKOUT_PCIE1 10/100/1G LAN CLKOUTFLEX1 None 11
SATA5 None 12
UHCI6
CLKOUT_PCIE2 CARD READER CLKOUTFLEX2 None 13
CLKOUT_PCIE3 MINI CARD WLAN CLKOUTFLEX3 None 2 External
CLK Option @ HDMI@ EMI@
USB 3.0 Port
USB Port
UMA X X V X X 1
CLKOUT_PCIE4 None
Symbol Note : 2 USB/B (Right Side)
4
CLKOUT_PCIE5 None : means Digital Ground 3 4
4
CLKOUT_PCIE6 None
: means Analog Ground
CLKOUT_PCIE7 None
Security Classification Compal Secret Data Compal Electronics, Inc.
2009/08/01 2010/05/28 Title
CLKOUT_PEG_B None Issued Date Deciphered Date
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-7531P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, April 09, 2011 Sheet 3 of 45
A B C D E
5 4 3 2 1
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+V1.05S_VCCP impedance = 43 mohms
D PEG_ICOMPO signals should be routed with - D
1
max length = 500 mils
RC1
24.9_0402_1% - typical impedance = 14.5 mohms
UCPU1A
2
G3 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO G1
14 DMI_CRX_PTX_N0 M2 DMI_RX#[0] PEG_RCOMPO G4
14 DMI_CRX_PTX_N1 P6 DMI_RX#[1]
14 DMI_CRX_PTX_N2 P1 DMI_RX#[2]
14 DMI_CRX_PTX_N3 P10 DMI_RX#[3] PEG_RX#[0] H22
PEG_RX#[1] J21
14 DMI_CRX_PTX_P0 N3 DMI_RX[0] PEG_RX#[2] B22
14 DMI_CRX_PTX_P1 P7 DMI_RX[1] PEG_RX#[3] D21
DMI
DMI
14 DMI_CRX_PTX_P2 P3 DMI_RX[2] PEG_RX#[4] A19
14 DMI_CRX_PTX_P3 P11 DMI_RX[3] PEG_RX#[5] D17
PEG_RX#[6] B14
14 DMI_CTX_PRX_N0 K1 DMI_TX#[0] PEG_RX#[7] D13
14 DMI_CTX_PRX_N1 M8 DMI_TX#[1] PEG_RX#[8] A11
14 DMI_CTX_PRX_N2 N4 DMI_TX#[2] PEG_RX#[9] B10
14 DMI_CTX_PRX_N3 R2 DMI_TX#[3] PEG_RX#[10] G8
PEG_RX#[11] A8
14 DMI_CTX_PRX_P0 K3 DMI_TX[0] PEG_RX#[12] B6
14 DMI_CTX_PRX_P1 M7 DMI_TX[1] PEG_RX#[13] H8
14 DMI_CTX_PRX_P2 P4 DMI_TX[2] PEG_RX#[14] E5
14 DMI_CTX_PRX_P3 T3 DMI_TX[3] PEG_RX#[15] K7
PEG_RX[0] K22
PEG_RX[1] K19
PEG_RX[2] C21
14 FDI_CTX_PRX_N0 U7 FDI0_TX#[0] PEG_RX[3] D19
C C
14 FDI_CTX_PRX_N1 W11 FDI0_TX#[1] PEG_RX[4] C19
14 FDI_CTX_PRX_N2 W1 FDI0_TX#[2] PEG_RX[5] D16
PCI EXPRESS -- GRAPHICS
14 FDI_CTX_PRX_N3 AA6 FDI0_TX#[3] PEG_RX[6] C13
14 FDI_CTX_PRX_N4 W6 FDI1_TX#[0] PEG_RX[7] D12
14 FDI_CTX_PRX_N5 V4 FDI1_TX#[1] PEG_RX[8] C11
14 FDI_CTX_PRX_N6 Y2 FDI1_TX#[2] PEG_RX[9] C9
Intel(R) FDI
Intel(R) FDI
14 FDI_CTX_PRX_N7 AC9 FDI1_TX#[3] PEG_RX[10] F8
PEG_RX[11] C8
PEG_RX[12] C5
14 FDI_CTX_PRX_P0 U6 FDI0_TX[0] PEG_RX[13] H6
14 FDI_CTX_PRX_P1 W10 FDI0_TX[1] PEG_RX[14] F6
14 FDI_CTX_PRX_P2 W3 FDI0_TX[2] PEG_RX[15] K6
14 FDI_CTX_PRX_P3 AA7 FDI0_TX[3]
14 FDI_CTX_PRX_P4 W7 FDI1_TX[0] PEG_TX#[0] G22
14 FDI_CTX_PRX_P5 T4 FDI1_TX[1] PEG_TX#[1] C23
14 FDI_CTX_PRX_P6 AA3 FDI1_TX[2] PEG_TX#[2] D23
14 FDI_CTX_PRX_P7 AC8 FDI1_TX[3] PEG_TX#[3] F21
PEG_TX#[4] H19
+V1.05S_VCCP AA11 C17
14 FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
14 FDI_FSYNC1 AC12 FDI1_FSYNC PEG_TX#[6] K15
PEG_TX#[7] F17
14 FDI_INT U11 FDI_INT PEG_TX#[8] F14
PEG_TX#[9] A15
1
14 FDI_LSYNC0 AA10 FDI0_LSYNC PEG_TX#[10] J14
RC2 14 FDI_LSYNC1 AG8 H13
FDI1_LSYNC PEG_TX#[11]
24.9_0402_1% PEG_TX#[12] M10
PEG_TX#[13] F10
D9
2
PEG_TX#[14]
eDP_COMPIO and ICOMPO signals PEG_TX#[15] J4
EDP_COMP AF3
should be shorted near balls eDP_COMPIO
AD2 eDP_ICOMPO PEG_TX[0] F22
B
and routed with typical 23 EDP_HPD# AG11 eDP_HPD PEG_TX[1] A23
B
D24
impedance <25 mohms PEG_TX[2]
E21
PEG_TX[3]
23 EDP_AUXN AG4 eDP_AUX# PEG_TX[4] G19
23 EDP_AUXP AF4 eDP_AUX PEG_TX[5] B18
PEG_TX[6] K17
DP
DP
PEG_TX[7] G17
23 EDP_TXN0 AC3 eDP_TX#[0] PEG_TX[8] E14
23 EDP_TXN1 AC4 eDP_TX#[1] PEG_TX[9] C15
PAD EDP_TXN2 AE11 K13
T1 @ eDP_TX#[2] PEG_TX[10]
PAD EDP_TXN3 AE7 G13
T2 @ eDP_TX#[3] PEG_TX[11]
PEG_TX[12] K10
23 EDP_TXP0 AC1 eDP_TX[0] PEG_TX[13] G10
23 EDP_TXP1 AA4 eDP_TX[1] PEG_TX[14] D8
PAD EDP_TXP2 AE10 K4
T3 @ eDP_TX[2] PEG_TX[15]
PAD EDP_TXP3 AE6
T4 @ eDP_TX[3]
SANDY-BRIDGE_BGA1023~D
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/04/26 Deciphered Date 2010/05/28 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7531P
Date: Sunday, April 10, 2011 Sheet 4 of 45
5 4 3 2 1
5 4 3 2 1
+3VS Buffered reset to CPU
+V1.05S_VCCP
1
CC1
0.1U_0402_16V4Z
1
2 RC3
75_0402_5%
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