Service Manuals, User Guides, Schematic Diagrams or docs for : Compal Compal_LA-7811P
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A B C D E
ZZZ2 ZZZ1 ZZZ3 ZZZ4 ZZZ5 ZZZ6 ZZZ7 ZZZ8 http://adf.ly/3o8pJ
PCB LA-7811P LS-6951P LS-6953P LS-6955P LS-6956P LS-6957P LS-6958P
DAZ@ DA2@ DA2@ DA2@ DA2@ DA2@ DA2@ DA2@
1 1
Compal Confidential
2
QLA01 LA7811P Schematics Document 2
Intel Sandy Bridge Processor with DDRIII + Cougar Point
AIO M/B
3 3
2011-06-02
REV:0.1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 09, 2011 Sheet 1 of 63
A B C D E
5 4 3 2 1
Compal Confidential http://adf.ly/3o8pJ
VRAM 512MB *1* :2D Display
Model Name : QLAO1 VRAM 1 GB
File Name : LA7811P
DDR3 x4 *2* :3D Display
P.28~30 DDR3-SO-DIMM DDR3-SO-DIMM
Intel CPU BANK 0, 1 BANK 0, 1
P.10 P.11
D Sandy Bridge D
23 LCD VGA 1066/1333MHz 1.5V 1066/1333MHz 1.5V
PEGx16 Desktop Channel A Channel B
NVdia N12P-GV
17W HDMI
OUT
65W F B-CAS
LVDS conn SPI ROM
W25X40BVSNIG 29mm x 29mm B LGA1155
RF IN
P.34 SOIC 8P 37.5mm x 37.5mm
P.21~27
P.33 P.4~9
Option
DVI from dGPU
DTV
FDIx8 DMIx4 USB USB2.0 x2 Touch BT Recorder TV Tuner
HDMI OUT
100 MHz 100 MHz WebCAM Side port A Screen
P.34 P.46
Conn
P.46
On Mini Card
P.34 P.44 P.42
G
DVI from UMA PCH USB2.0 x11
Port 11
Port 5
Scalar Cougar Point 3.3V 48MHz Port 5 Port 0,1 Port 2,3,8,9 Port 4 Port 10 Port 11
DVI
C
Realtek H61 PCIEx4 100MHz 2.5/5.0 GT/S
C
RTD2667 Port 2 Port 6 Port 1
HD_Audio
3.3V 24MHz
FCBGA-942 SATAx3 SATA 1.5/3.0 GT/S
Port 4
P.33 HP conn 27mm x 27mm Port 0 SATA2.0 Port 1 SATA2.0
P.41
P.12~20
HP_SCA_LEFT HP_RIGHT
3.5" SATA ODD Realtek Card Reader WLAN
HP_SCA_RIGHT HP_LEFT SATA HDD Conn LAN RT5209 On Mini Card
Conn RTL8111E-VL 7 in 1 or better
P.35 P.35 P.38 P.37 P.42
HP_2932_LEFT HP AMP Audio Codec SPI ROM
HP_2932_RIGHT APA2176A MX25L3206 Slim BD support 3D GIGA
I2S P.41 ALC663-GR EM2I-12G LAN
P.39 (4MB) P.13
SPI ROM
LPC MX25L1005
33MHz AMC-12G
P.44
A E F
B
IO Board P.36 B
AMP x1 INT EXT KBC
APA_106
P.40
MIC
P.36
MIC
P.41
E PS/2
ENE KB930-A1
P.43
RJ45 USB3.0 x2
NEC uPD720200A HDMI IN Antenna Jack
Conn
P.38 P.38
SPK 3W x2 USB2.0 AV-IN
USB3.0 PS/2
P.40
JPWR1
ATV & HTV Board USB2.0 x2 USB2.0/3.0 HDMI OUT
CVBS AIN-L AIN-R
Conn x2 Conn P.38
DVI
G
HDMI
IN SW1
4 ch. LVDS Scalar Control C B C D-1 D-2
Power ENE Touch D AV
IN
CVBS
A
D-1 Button SB3534 Button AIN SW AIN
A
TS5A23157
P.32 P.48 P.46 H P.47
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 2011/07/20 Title
23.6" LCD Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
120Hz LCD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom QLA01 M/B LA-7811P Schematic
1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 09, 2011 Sheet 2 of 63
5 4 3 2 1
5 4 3 2 1
DMI_PTX_HRX_N[0..3] 14
http://adf.ly/3o8pJ PEG_GTX_C_HRX_P[0..15] 22
DMI_PTX_HRX_P[0..3] 14 PEG_GTX_C_HRX_N[0..15] 22
DMI_HTX_PRX_N[0..3] 14 PEG_HTX_C_GRX_P[0..15] 22
DMI_HTX_PRX_P[0..3] 14 PEG_HTX_C_GRX_N[0..15] 22
SKT_H2
JCPU1C Note:Use 0.1uF now; If need to support to Gen3, need change C1~C32 to 0.22uF.
PEG_GTX_C_HRX_P15 B11 C13 PEG_HTX_GRX_P15 C1 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P15
PEG_GTX_C_HRX_N15 PEG_RX[0] PEG_TX[0] PEG_HTX_GRX_N15 C2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N15
B12 PEG_RX#[0] PEG_TX#[0] C14 1 2
D PEG_GTX_C_HRX_P14 D12 E14 PEG_HTX_GRX_P14 C3 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P14 D
PEG_GTX_C_HRX_N14 PEG_RX[1] PEG_TX[1] PEG_HTX_GRX_N14 C4 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N14
D11 PEG_RX#[1] PEG_TX#[1] E13 1 2
PEG_GTX_C_HRX_P13 C10 G14 PEG_HTX_GRX_P13 C5 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P13
PEG_GTX_C_HRX_N13 PEG_RX[2] PEG_TX[2] PEG_HTX_GRX_N13 C6 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N13
C9 PEG_RX#[2] PEG_TX#[2] G13 1 2
PEG_GTX_C_HRX_P12 E10 F12 PEG_HTX_GRX_P12 C7 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P12
PEG_GTX_C_HRX_N12 PEG_RX[3] PEG_TX[3] PEG_HTX_GRX_N12 C8 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N12
E9 PEG_RX#[3] PEG_TX#[3] F11 1 2
PEG_GTX_C_HRX_P11 B8 J14 PEG_HTX_GRX_P11 C9 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P11
PEG_GTX_C_HRX_N11 PEG_RX[4] PEG_TX[4] PEG_HTX_GRX_N11 C10 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N11
B7 PEG_RX#[4] PEG_TX#[4] J13 1 2
PEG_GTX_C_HRX_P10 C6 D8 PEG_HTX_GRX_P10 C11 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P10
PEG_GTX_C_HRX_N10 PEG_RX[5] PEG_TX[5] PEG_HTX_GRX_N10 C12 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N10
C5 PEG_RX#[5] PEG_TX#[5] D7 1 2
PEG_GTX_C_HRX_P9 A5 D3 PEG_HTX_GRX_P9 C13 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P9
PEG_GTX_C_HRX_N9 PEG_RX[6] PEG_TX[6] PEG_HTX_GRX_N9 C14 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N9
A6 PEG_RX#[6] PEG_TX#[6] C3 1 2
PEG
PEG_GTX_C_HRX_P8 E2 E6 PEG_HTX_GRX_P8 C15 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P8
PEG_GTX_C_HRX_N8 PEG_RX[7] PEG_TX[7] PEG_HTX_GRX_N8 C16 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N8
E1 PEG_RX#[7] PEG_TX#[7] E5 1 2
PEG_GTX_C_HRX_P7 F4 F8 PEG_HTX_GRX_P7 C17 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P7
PEG_GTX_C_HRX_N7 PEG_RX[8] PEG_TX[8] PEG_HTX_GRX_N7 C18 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N7
F3 PEG_RX#[8] PEG_TX#[8] F7 1 2
PEG_GTX_C_HRX_P6 G2 G10 PEG_HTX_GRX_P6 C19 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P6
PEG_GTX_C_HRX_N6 PEG_RX[9] PEG_TX[9] PEG_HTX_GRX_N6 C20 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N6
G1 PEG_RX#[9] PEG_TX#[9] G9 1 2
PEG_GTX_C_HRX_P5 H3 G5 PEG_HTX_GRX_P5 C21 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P5
PEG_GTX_C_HRX_N5 PEG_RX[10] PEG_TX[10] PEG_HTX_GRX_N5 C22 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N5
H4 PEG_RX#[10] PEG_TX#[10] G6 1 2
PEG_GTX_C_HRX_P4 J1 K7 PEG_HTX_GRX_P4 C23 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P4
PEG_GTX_C_HRX_N4 PEG_RX[11] PEG_TX[11] PEG_HTX_GRX_N4 C24 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N4
J2 PEG_RX#[11] PEG_TX#[11] K8 1 2
PEG_GTX_C_HRX_P3 K3 J5 PEG_HTX_GRX_P3 C25 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P3
PEG_GTX_C_HRX_N3 PEG_RX[12] PEG_TX[12] PEG_HTX_GRX_N3 C26 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N3
K4 PEG_RX#[12] PEG_TX#[12] J6 1 2
PEG_GTX_C_HRX_P2 L1 M8 PEG_HTX_GRX_P2 C27 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P2
PEG_GTX_C_HRX_N2 PEG_RX[13] PEG_TX[13] PEG_HTX_GRX_N2 C28 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N2
L2 PEG_RX#[13] PEG_TX#[13] M7 1 2
PEG_GTX_C_HRX_P1 M3 L6 PEG_HTX_GRX_P1 C29 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P1
PEG_GTX_C_HRX_N1 PEG_RX[14] PEG_TX[14] PEG_HTX_GRX_N1 C30 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N1
M4 PEG_RX#[14] PEG_TX#[14] L5 1 2
PEG_GTX_C_HRX_P0 N1 N5 PEG_HTX_GRX_P0 C31 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P0
C PEG_GTX_C_HRX_N0 PEG_RX[15] PEG_TX[15] PEG_HTX_GRX_N0 C32 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N0 C
N2 PEG_RX#[15] PEG_TX#[15] N6 1 2
DMI_PTX_HRX_P0 W5 V7 DMI_HTX_PRX_P0
DMI_PTX_HRX_N0 DMI_RX[0] DMI_TX[0] DMI_HTX_PRX_N0
W4 DMI_RX#[0] DMI_TX#[0] V6
DMI_PTX_HRX_P1 V3 W7 DMI_HTX_PRX_P1
DMI_PTX_HRX_N1 DMI_RX[1] DMI_TX[1] DMI_HTX_PRX_N1
V4 DMI_RX#[1] DMI_TX#[1] W8
DMI_PTX_HRX_P2 Y3 Y6 DMI_HTX_PRX_P2
DMI_PTX_HRX_N2 DMI_RX[2] DMI_TX[2] DMI_HTX_PRX_N2
DMI
Y4 DMI_RX#[2] DMI_TX#[2] Y7
DMI_PTX_HRX_P3 AA4 AA7 DMI_HTX_PRX_P3
DMI_PTX_HRX_N3 DMI_RX_3 DMI_TX[3] DMI_HTX_PRX_N3
AA5 DMI_RX#[3] DMI_TX#[3] AA8
P3 PE_RX[0] PE_TX[0] P8
P4 PE_RX#[0] PE_TX#[0] P7
R2 PE_RX[1] PE_TX[1] T7
R1 PE_RX#[1] PE_TX#[1] T8 7/20 PE_TX[0~3]/PE_TX#[0~3] only use on
7/20 PE_RX[0~3]/PE_RX#[0~3] only use on T4 PE_RX[2] PE_TX[2] R6 Workstation.
GEN
Workstation. T3 PE_RX#[2] PE_TX#[2] R5
U2 PE_RX[3] PE_TX[3] U5
U1 PE_RX#[3] PE_TX#[3] U6
+1.05VCCIO
24.9_0402_1% 2 1 R1 PEG_IRCOMP B5 PEG_ICOMPO H_FDI_TXN[0..7] 16
C4 PEG_RCOMPO H_FDI_TXP[0..7] 16
B4 PEG_ICOMPI SKT_H2
JCPU1D
LOTES_ACAZIF096P01_SANDYBRIDGE 3 OF 11
PEG_ICOMPI and RCOMPO signals should be shorted and CONN@ AC8 H_FDI_TXP0
FDI_TX[0] H_FDI_TXN0
FDI_TX#[0] AC7
B routed 16 H_FDI_FSYNC0 AC5 AC2 H_FDI_TXP1 B
FDI_FSYNC_0 FDI_TX[1] H_FDI_TXN1
with - max length = 500 mils - ;Width/Space= (4 mils/15mils) 16 H_FDI_LSYNC0 AC4 FDI_LSYNC_0 FDI_TX#[1] AC3
FDI_TX[0] AD2 H_FDI_TXP2
PEG_ICOMPO signals should be routed with - max length = FDI_TX[2] H_FDI_TXN2
FDI_TX#[2] AD1
AD4 H_FDI_TXP3
500 mils FDI_TX[3]
AD3 H_FDI_TXN3
FDI_TX#[3]
- Width/Space (12 mils/15mils)
AD7 H_FDI_TXP4
FDI_TX[4] H_FDI_TXN4
FDI_TX#[4] AD6
AE5 AE7 H_FDI_TXP5
16 H_FDI_FSYNC1 FDI_FSYNC_1 FDI_TX[5]
AE4 AE8 H_FDI_TXN5
16 H_FDI_LSYNC1 FDI_LSYNC_1 FDI_TX#[5]
AF3 H_FDI_TXP6
FDI_TX[6] H_FDI_TXN6
FDI_TX#[6] AF2
AG2 H_FDI_TXP7
FDI_TX[7] H_FDI_TXN7
FDI_TX#[7] AG1
1000P_0402_50V7K @ 2 1 C1007 H_FDI_FSYNC0
+1.05VCCIO 16 H_FDI_INT AG3 FDI_INT
1000P_0402_50V7K @ 2 1 C1008 H_FDI_LSYNC0 FDI
24.9_0402_1% 2 1 R2 FDI_ICOMP AE2 LINK
1000P_0402_50V7K @ FDI_COMPIO
2 1 C1009 H_FDI_FSYNC1 AE1 FDI_ICOMPO
1000P_0402_50V7K @ 2 1 C1010 H_FDI_LSYNC1
4 OF 11
LOTES_ACAZIF096P01_SANDYBRIDGE
1000P_0402_50V7K @ 2 1 C1011 H_FDI_INT CONN@
8/23 Add
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (1/6) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 4 of 63
5 4 3 2 1
5 4 3 2 1
http://adf.ly/3o8pJ +1.05VCCIO
SKT_H2
JCPU1E
H_CATERR# 1K_0402_5% 2 @ 1 R6
H_PECI 1K_0402_5% 2 @ 1 R7
XDP_TDO_R 51_0402_5% 2 1 R8
0_0402_5% 1 R656 CLK_CPU_DMI_R XDP_TDI_R 51_0402_5% R9
17 CLK_CPU_DMI 2 W2 BCLK[0] VCCIO_SELECT P33 2 1
0_0402_5% 1 R657 2 CLK_CPU_DMI#_R W1 P34 VCCSA_VID VCCSA_VID 53 XDP_TMS_R 51_0402_5% 2 1 R10
17 CLK_CPU_DMI# BCLK#[0] VCCSA_VID_0
D T2 VCCSA_SENSE VCCSA_SENSE 53 H_VIDALERT# 75_0402_1% 2 1 R11 D
H_VIDSCLK VCCSA_SENSE H_VIDSCLK 90.9_0402_1% @
57 H_VIDSCLK C37 VIDSCLK 2 1 R12
H_VIDSOUT B37 A36 VCCSENSE H_VIDSOUT 110_0402_1% 2 1 R13
57 H_VIDSOUT H_VIDALERT# R300 1 VIDSOUT VCC_SENSE VCCSENSE 57
57 H_VIDALERT# 2 43_0402_1% H_VIDALERT#_R A37
VIDALERT# VSS_SENSE B36 VSSSENSE
VSSSENSE 57
H_THERMTRIP#_R 51_0402_5% 2 @ 1 R501
H_PROCHOT# 51_0402_5% 2 1 R521
AB4 VCCIO_SENSE VCCIO_SENSE 54 H_THERMTRIP# 51_0402_5% 2 @ 1 R715
13 H_CPUPW RGD VCCIO_SENSE
H_CPUPW RGD J40 AB3
PM_SYS_PW RGD_BUF 2 R644 1 PM_SYS_PW RGD_R AJ19 UNCOREPWRGOOD VSSIO_SENSE
120_0402_5% H_RESET# SM_DRAMPWROK VGFX_VCCSENSE
F36 RESET# VCCAXG_SENSE L32 VGFX_VCCSENSE 57
M32 VGFX_VSSSENSE VGFX_VSSSENSE 57
H_PM_SYNC VSSAXG_SENSE XDP_TRST#_R 51_0402_5% 2 R14
12 H_PM_SYNC E38 PM_SYNC 1
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