Service Manuals, User Guides, Schematic Diagrams or docs for : Compal Compal_LA-9001P
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
>> Download Compal_LA-9001P documenatation <<
Text preview - extract from the document
A B C D E
1 1
Compal Confidential
2 2
VIUS5 LA-9001P M/B Schematics Document
AMD FP2 Processor with DDRIII + Husdon M3 FCH
AMD VGA Seymour XT
3
2012-05-31 3
REV:0.3
www.qdzbwx.com
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/01/15 Deciphered Date 2013/01/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VAUS5 LA9001P M/B
Date: Thursday, May 31, 2012 Sheet 1 of 50
A B C D E
A B C D E
Compal confidential
File Name :
AMD Seymour XT
1
VRAM PCIE x 8 Gen2 1
128x16, 64x16 Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X 1
DDR3 x 4 AMD FP2 APU Dual Channel BANK 0, 1 page 9
page 15,~21
1.5V DDRIII 1333MT/s
DP Port0 Trinity Upgradeable to 4G Memory
LVDS
translator
BGA 813 pin
RTD2132S HDMI Conn. DP Port2 27mm x 30mm
page 22 page 24
page 5,~8
4 * x1 PCI-E 2.0 x4 UMI Gen. 1 2Channel Speaker
page 30
LVDS Conn. 2.5GT/s per lane
page 23 GPP0
LAN(10/100/Giga) Single Digital MIC
Realtek IO Board page 32
2
8105E-VD (10/100)
8111F-CGT (Giga)
AZALIA Audio Codec 2
page 26
Hudson M3 RealTek Audio Combo Jack
ALC259-VC2
uFCBGA-656 page 30
(APPLE type)
Stereo
24.5mm x 24.5mm HeadPhone Output
Microphone Input
RJ45 CONN 1*USB3.0,6*USB2.0
page 27 IO Board page 32
page 10,~14 1*SATA serial
CMOS Camera page 23
PCI Express USB(reserve for WiMAX)
Mini card Slot 1 PCI-E(WLAN) LPC BUS USB PORT 3.0 x1(Left) page 33
WLAN page 25 page 32
Card Reader RTS 5178 (2in1) IO Board
3 SPI ROM EC 3
PCI Express SATA(SSD)
page 11
ENE KB9012 USB PORT 2.0 x2(Right)
page 32
IO Board
Mini card Slot 2 page 31
page 25
www.qdzbwx.com
Sub-borad
Int.KBD
page 32
POWER Board
Touch Pad
LED Board page 32
SATA1
SATA2.0 HDD CONN
page 29
IO Board
Thermal Sensor
page 28
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/01/15 Deciphered Date 2013/01/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VAUS5 LA9001P M/B
Date: Friday, May 25, 2012 Sheet 2 of 50
A B C D E
A B C D E
Voltage Rails
SIGNAL
STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
+5VS
+3VS Full ON HIGH HIGH ON ON ON ON
+2.5VS
S1(Power On Suspend) HIGH HIGH ON ON ON LOW
power +1.5VS
plane +1.2VS S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF
1
+1.1VS LOW 1
+5VALW +1.5V S4 (Suspend to Disk) HIGH ON OFF OFF OFF
+0.75VS
+B +1.5V_APU
+APU_CORE S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+3VALW
+APU_CORE_NB
+VGA_CORE
State +1.1VALW
+3.3VGS BOARD ID Table Board ID / SKU ID Table for AD channel
+1.8VGS
+1.5VGS
Board ID PCB Revision
0 ID BRD ID Ra Rb Vab
+1.0VGS
1 0.3 0 R10 MP x 0 0V
2 Ra = R1562
3 1 R03 PVT 100K 8.2K 0.25V Rb = R1564
S0 4
O O O O 2 R02 DVT 100K 18K 0.5V
5
6 3 R01 EVT 100K 33K 0.82V
S3 7
O O O X
2 2
S5 S4/AC
O O X X USB Port Table
4 External BOM Structure Table
S5 S4/ Battery only USB 2.0 USB 3.0 Port
O X X X USB Port BOM Structure BTO Item
0 USB Port (Right Side 1) A4R1@ A4 BGA APU (R1 compal part)
S5 S4/AC & Battery
don't exist X X X X 1 USB Port (Right Side 2) A4R3@ A4 BGA APU (R3 compal part)
2 Mini Card(WLAN) A6R1@ A6 BGA APU (R1 compal part)
3 Camera A6R3@ A6 BGA APU (R3 compal part)
elbaT lortnoC SUBMS 4 A8R1@ A8 BGA APU (R1 compal part)
lamrehT A8 BGA APU (R3 compal part)
NALW rosneS 5 CardReader A8R3@
ECRUOS AGV TTAB 2109BK NAWW MMIDOS HCF UPA 2312DTR A10 BGA APU (R1 compal part)
6 A10R1@
1KC_CE_BMS 7 A10R3@ A10 BGA APU (R3 compal part)
1AD_CE_BMS
2109BK
WLAV3+
X V
WLAV3+
X X X X X X X 8 SXTR1@ Seymour XT GPU (R1 compal part)
SUS_2KC_CE_BMS 9 SXTR3@ Seymour XT GPU (R3 compal part)
SUS_2AD_CE_BMS
2109BK
WLAV3+
X X X X X X X V
V5.1+
X 0 10 USB Port (Left Side) A70MR1@ A70 Hudson M3 FCH (R1 compal part)
0KLCS_HCF 1 11 A70MR3@ A70 Hudson M3 FCH (R3 compal part)
HCF X X X V V X X X X XHCI Common VGA circuit
3 0ATADS_HCF SV3+ SV3+ SV3+ 2 12 PX@ 3
3 13 CMOS@ CMOS Camera part
2KC_CE_BMS
2109BK V X X X X V V UMA@ UMA strap pin
2AD_CE_BMS SV3+ X X USB OC MAPPING GAS@ Gastube
www.qdzbwx.com
)retfihs VL( RTL8105E
8105@
OC# USB Port RTL8111F
GIGA@
0 USB20 port10 USB30 port0 HDMI@ HDMI part
EC SM Bus1 address EC SM Bus2 address 1 USB20 port0 port1 NONAOAC@ No AOAC function
2 AOAC@ support AOAC function
Device Address Device Address
3 ME@ ME part
Smart Battery 0001 011X b Thermal Sensor 1001_101xb
DEBUG@ Debug Switch (MP will remove)
SB-TSI(default) 1001_100xb
@ Unpop
VGA(thermal) 1000_001xb APU PCIE PORT LIST FCH PCIE PORT LIST
SSD@ SSD part
FCH SM Bus address RTD2132S 1010_1000b Port Device Port Device
Device Address
1 LAN 1
DDR DIMM1 1001 000Xb
2 WLAN 2
4 3 3 4
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/01/15 Deciphered Date 2013/01/15 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VAUS5 LA9001P M/B
Date: Tuesday, May 29, 2012 Sheet 3 of 50
A B C D E
A B C D E
Without BACO option :
Power-Up/Down Sequence PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
"Thames" has the following requirements with regards to power-supply sequencing
to avoid damaging the ASIC: BACO option :
All the ASIC supplies, except for VDDR3, must fully reach their respective PE_GPIO0 : High ->Normal operation (dGPU is not reset on BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
nominal voltages within 20 ms of the start of the ramp-up sequence, though a
shorter ramp-up duration is preferred. There is no timing requirement on the dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
1 ramp up of VDDR3 relative to other power rails. PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA 1
The external pull-up resistors on the DDC/AUX signals (if applicable) should
ramp up before or after both VDDC and VDD_CT have ramped up.
DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa). For BACO
DPLL_PVDD, MPV18, and SPV18
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 775mA
enabled designs, VDDC must ramp up before VDD_CT at system power up. SPV10
For power down, reversing the ramp-up sequence is recommended
PCIE_VDDC 1.0V OFF ON 1.1A
VDDR3 3.3V OFF ON 60mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
BACO mode) VDDC Same as
PCIE_VDDC
VDDR1 1.5V OFF OFF 1.2A
VDDR3(3.3VGS) VDDC/VDDCI TBD OFF OFF 28
PCIE_VDDC(1.0V)
VDDR1(1.5VGS)
2 2
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PERSTb
REFCLK
Straps Reset
Straps Valid
3 3
Global ASIC Reset
PX5.0
less than 20ms (Seymour) T4+16clock
PE_GPIO0(PXS_RST#)
+VGA_CORE
iGPU dGPU
BIF_VDDC
PE_GPIO1(PXS_PWREN)
www.qdzbwx.com
+3.3VALW +3.3VGS Short PX_MODE and PX_PWREN
MOS
1
B+ Regulator
+1.5VGS
+1.5V_IO +1.0VGS
PWM
2 3
4
+B Regulator
+VGA_CORE 4
+5VLAW +1.8VGS
Regulator
5 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/01/15 Deciphered Date 2013/01/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VAUS5 LA9001P M/B
Date: Friday, May 25, 2012 Sheet 4 of 50
A B C D E
A B C D E
<15> PCIE_CRX_GTX_P[0..7] PCIE_CTX_GRX_P[0..7] <15>
<15> PCIE_CRX_GTX_N[0..7] PCIE_CTX_GRX_N[0..7] <15>
UCPU1A
PCIE_CRX_GTX_P0 AP1 AN1 PCIE_CTX_C_GRX_P0 C1 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 AP2 P_GFX_RXP[0] P_GFX_TXP[0] AN2 PCIE_CTX_C_GRX_N0 C2 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N0
PCIE_CRX_GTX_P1 AM1 P_GFX_RXN[0] P_GFX_TXN[0] AM4 PCIE_CTX_C_GRX_P1 C3 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P1
PCIE_CRX_GTX_N1 AM2 P_GFX_RXP[1] P_GFX_TXP[1] AM3 PCIE_CTX_C_GRX_N1 C4 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N1
PCIE_CRX_GTX_P2 AK3 P_GFX_RXN[1] P_GFX_TXN[1] AK2 PCIE_CTX_C_GRX_P2 C5 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P2
1 PCIE_CRX_GTX_N2 AK4 P_GFX_RXP[2] P_GFX_TXP[2] AK1 PCIE_CTX_C_GRX_N2 C6 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N2 1
PCIE_CRX_GTX_P3 AJ1 P_GFX_RXN[2] P_GFX_TXN[2] AH1 PCIE_CTX_C_GRX_P3 C7 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P3
PCIE_CRX_GTX_N3 AJ2 P_GFX_RXP[3] P_GFX_TXP[3] AH2 PCIE_CTX_C_GRX_N3 C8 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N3
PCIE_CRX_GTX_P4 AH4 P_GFX_RXN[3] P_GFX_TXN[3] AF3 PCIE_CTX_C_GRX_P4 C9 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P4
PCIE_CRX_GTX_N4 AH3 P_GFX_RXP[4] P_GFX_TXP[4] AF4 PCIE_CTX_C_GRX_N4 C10 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N4
PCIE_CRX_GTX_P5 AF2 P_GFX_RXN[4] P_GFX_TXN[4] AE1 PCIE_CTX_C_GRX_P5 C11 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P5
PCIE_CRX_GTX_N5 AF1 P_GFX_RXP[5] P_GFX_TXP[5] AE2 PCIE_CTX_C_GRX_N5 C12 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N5
PCIE_CRX_GTX_P6 AD1 P_GFX_RXN[5] P_GFX_TXN[5] AD4 PCIE_CTX_C_GRX_P6 C13 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P6
PCIE_CRX_GTX_N6 AD2 P_GFX_RXP[6] P_GFX_TXP[6] AD3 PCIE_CTX_C_GRX_N6 C14 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N6
PCIE_CRX_GTX_P7 AB3 P_GFX_RXN[6] P_GFX_TXN[6] AB2 PCIE_CTX_C_GRX_P7 C15 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P7
GRAPHICS
PCIE_CRX_GTX_N7 AB4 P_GFX_RXP[7] P_GFX_TXP[7] AB1 PCIE_CTX_C_GRX_N7 C16 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N7
AA1 P_GFX_RXN[7] P_GFX_TXN[7] Y1
AA2 P_GFX_RXP[8] P_GFX_TXP[8] Y2
Y4 P_GFX_RXN[8] P_GFX_TXN[8] V3
Y3 P_GFX_RXP[9] P_GFX_TXP[9] V4
V2 P_GFX_RXN[9] P_GFX_TXN[9] U1
V1 P_GFX_RXP[10] P_GFX_TXP[10] U2
T1 P_GFX_RXN[10] P_GFX_TXN[10] T4
T2 P_GFX_RXP[11] P_GFX_TXP[11] T3
P3 P_GFX_RXN[11] P_GFX_TXN[11] P2
P4 P_GFX_RXP[12] P_GFX_TXP[12] P1
N1 P_GFX_RXN[12] P_GFX_TXN[12] M1
N2 P_GFX_RXP[13] P_GFX_TXP[13] M2
M4 P_GFX_RXN[13] P_GFX_TXN[13] K3
M3 P_GFX_RXP[14] P_GFX_TXP[14] K4
K2 P_GFX_RXN[14] P_GFX_TXN[14] J1
K1 P_GFX_RXP[15] P_GFX_TXP[15] J2
P_GFX_RXN[15] P_GFX_TXN[15]
AH5 AG7 PCIE_CTX_C_DRX_P0 C33 1 2 0.1U_0402_16V7K
<26> PCIE_CRX_DTX_P0 AH6 P_GPP_RXP[0] P_GPP_TXP[0] AG8 1 2 PCIE_CTX_DRX_P0 <26>
PCIE_CTX_C_DRX_N0 C34 0.1U_0402_16V7K LAN
<26> PCIE_CRX_DTX_N0 AG5 P_GPP_RXN[0] P_GPP_TXN[0] AE7 PCIE_CTX_C_DRX_P1 1 2 PCIE_CTX_DRX_N0 <26>
C35 0.1U_0402_16V7K
<25> PCIE_CRX_DTX_P1 AG6 P_GPP_RXP[1] P_GPP_TXP[1] AE8 PCIE_CTX_C_DRX_N1 1 2 PCIE_CTX_DRX_P1 <25>
C36 0.1U_0402_16V7K WLAN
2 <25> PCIE_CRX_DTX_N1 AE6 P_GPP_RXN[1] P_GPP_TXN[1] AD7 PCIE_CTX_DRX_N1 <25> 2
AE5 P_GPP_RXP[2] P_GPP_TXP[2] AD8
AD6 P_GPP_RXN[2] P_GPP_TXN[2] AB6
GPP
AD5 P_GPP_RXP[3] P_GPP_TXP[3] AB5
P_GPP_RXN[3] P_GPP_TXN[3]
AM10 AN6 UMI_TXP0_C C37 1 2 0.1U_0402_16V7K
<10> UMI_RXP0 AN10 P_UMI_RXP[0] P_UMI_TXP[0] AM6 1 2 UMI_TXP0 <10>
UMI_TXN0_C C38 0.1U_0402_16V7K
<10> UMI_RXN0 AN8 P_UMI_RXN[0] P_UMI_TXN[0] AP6 1 2 UMI_TXN0 <10>
UMI_TXP1_C C39 0.1U_0402_16V7K
<10> UMI_RXP1 AM8 P_UMI_RXP[1] P_UMI_TXP[1] AR6 UMI_TXN1_C 1 2 UMI_TXP1 <10>
C40 0.1U_0402_16V7K
<10> UMI_RXN1 AP8 P_UMI_RXN[1] P_UMI_TXN[1] AP4 UMI_TXP2_C 1 2 UMI_TXN1 <10>
C41 0.1U_0402_16V7K
<10> UMI_RXP2 AR8 P_UMI_RXP[2] P_UMI_TXP[2] AR4 UMI_TXN2_C 1 2 UMI_TXP2 <10>
C42 0.1U_0402_16V7K
<10> UMI_RXN2 AR7 P_UMI_RXN[2] P_UMI_TXN[2] AP3 1 2 UMI_TXN2 <10>
UMI_TXP3_C C43 0.1U_0402_16V7K
<10> UMI_RXP3 AP7 P_UMI_RXP[3] P_UMI_TXP[3] AR3 1 2 UMI_TXP3 <10>
UMI_TXN3_C C44 0.1U_0402_16V7K
UMI
<10> UMI_RXN3 P_UMI_RXN[3] P_UMI_TXN[3] UMI_TXN3 <10>
1 2 P_ZVDDP AR11 AP11 P_ZVSS 1 2
+1.2VS P_ZVDDP P_ZVSS
R1 196_0402_1% R2 196_0402_1%
TRINITY-A8-SERIES_BGA813
Compensation Resistor to VDDP Compensation Resistor to VSS
A8R3@
◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo