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A B C D E
1 1
VCUAA
2
Metis 10F/10FG 2
LA-9161P REV 1.0 Schematic
Intel Processor (Ivy Bridge) / PCH(Panther Point)
2012-08-07 Rev 1.0
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VCUAA
Date: Tuesday, October 16, 2012 Sheet 1 of 53
A B C D E
A B C D E
Intel CPU
PCI-Express 16X Gen2 Ivy Bridge Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
17W Dual Channel BANK 0, 1, 2, 3 page 11,12
1.5V DDRIII 1066/1333/1600 MT/s
BGA-1023 GCLK
1 1
31mm*24mm
SLG3NB300VTR page 34
page 5,6,7,8,9,10
VGA (DDR3)
nVIDIA N13P-GL with 2GB
FDI X8 DMI X4
2.7GT/s 5GT/s
page 13,14,15,16,17,18,19,20,21
USB30 2x
5V 5GT/s USB Left USB Right
USB20 port 2 USB20 port 0,1
USB20 3x USB30 port 1,2
page 37 page 37
LVDS Conn. 5V 480MHz
page 22
Intel PCH USB20 2x CardReader RTS5137 Int. Camera
2 HDMI Conn. Panther Point 5V 480MHz USB20 port 8 USB port 11 2
page 36 page 22
page 23
FCBGA-989
PCIe Gen1 1x PCIeMini Card
RJ45 RTL8105E-VD 10/100M PCIe Gen1 1x 25mm*25mm 1.5V 5GT/s
page 35 1.5V 5GT/s
WLAN PCIe port 2
page 34
PCIe port 1 page 35
SATA Gen3 port 0 SATA HDD
SATA port 0
5V 6GHz(600MB/s) page 33
SATA Gen3 port 1 SATA mSATA
5V 3GHz(300MB/s) SATA port 1
page 24,25,26,27,28,29,30,31,32 page 34
TP/B
page 41
3 LED+LID/B LPC BUS HD Audio 3
page 41
3.3V 33 MHz 3.3V 24MHz
RTC CKT. SPI ROM
page 24
Debug Port KB9012 HDA Codec
(4MB + 2MB)
page 24 page 41 page 40 ALC259
page 38
DC/DC Interface CKT.
page 42
Touch Pad Int.KBD SPK Conn JPIO
page 39
Power Circuit DC/DC page 41 page 41 (HP & MIC)
page 39
page 43,44,45,46,47,48,
49,50,51
Power On/Off CKT.
4
page 41 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VCUAA
Date: Tuesday, October 16, 2012 Sheet 2 of 53
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.1A +3VL
DESIGN CURRENT 0.1A +5VL
B+
Ipeak=8.13A, Imax=5.69A, Iocp min=8.7 DESIGN CURRENT 5A +5VALW
SUSP#
D D
DESIGN CURRENT 2A +1.8VS
SY8033BDBC
SUSP
N-CHANNEL DESIGN CURRENT 4A +5VS
SI4800
RT8205LZQW
VCCP_PWRGOOD
Ipeak=6A, Imax=4.A, Iocp min=8 DESIGN CURRENT 6A +VCCSA
SY8037
Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 5A +3VALW
C C
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800 LCD_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413
DGPU_PWR_EN
DESIGN CURRENT 60mA +3VS_DGPU
P-CHANNEL
AO-3413
DESIGN CURRENT 2A +3V_WLAN
VR_ON PJ6
DESIGN CURRENT 94A +CPU_CORE
NCP6132A DESIGN CURRENT 33A +GFX_CORE
SUSP#
B
Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A +1.05VS_VCCP B
TPS51212
VGA_PWROK
DESIGN CURRENT 60mA +1.05VS_DGPU
P-CHANNEL
AO-3413
SYSON
Ipeak=15A, Imax=10.5A, Iocp min=18A DESIGN CURRENT 10A +1.5V
RT8207M SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU
FDS6676AS
DESIGN CURRENT 2A +1.5VS
PJ1
SUSP or 0.75VR_EN#
DESIGN CURRENT 1.5A +0.75VS
VGA_PWROK
A DESIGN CURRENT 8.6A A
N-CHANNEL +VRAM_1.5VS
FDS6676AS
SUSP#
Ipeak=33.8A, Imax=23.4A, Iocp min=40A DESIGN CURRENT 20.5A +VGA_CORE
TPS51518RUKR
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VCUAA
Date: Tuesday, October 16, 2012 Sheet 3 of 53
5 4 3 2 1
A B C D E
( O MEANS ON X MEANS OFF )
Voltage Rails Platform SKU CPU PCH VGA
+5VS Ivy Bridge i3
+RTCVCC B+ +5VL +5VALW +1.5V HM77C1(HM77@)
+3VS (CPUI3@) nVIDIA N13P-GL
+3VL +3VALW Chief River HM77C1_R1(HM77R1@)
+1.8VS Ivy Bridge i5 (N13PGL@)
+VSB HM77C1_R3(HM77R3@)
power +1.5VS (CPUI5@)
plane +1.05VS
+0.75VS
1 BTO Option Table 1
+CPU_CORE
+VGA_CORE
Function SKU MIC LAN
+GFX_CORE
+VTT description
State
+VRAM_1.5VS
+3VS_DGPU
explain
+1.05VS_DGPU BTO
S0
O O O O O O
S1
O O O O O O
S3
O O O O O X
2
S5 S4/AC
Function 2
O O O O X X
description
S5 S4/ Battery only
O O O X X X explain
S5 S4/AC & Battery BTO
don't exist
O X X X X X
Function
PCH SM Bus Address description
explain
Power Device HEX Address
BTO
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
Function
description
3 3
explain
BTO
SIGNAL
EC SM Bus1 Address EC SM Bus2 Address STATE SLP_S3# SLP_S4# SLP_S5#
Full ON HIGH HIGH HIGH
Power Device HEX Address Power Device HEX Address
S1(Power On Suspend) HIGH HIGH HIGH
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b
+3VL Smart Charger 12 H 0001 0010 b +3VS NVIDIA GPU 9E H 1001 1010 b S3 (Suspend to RAM) LOW HIGH HIGH
S4 (Suspend to Disk) LOW LOW HIGH
Power Device HEX Address S5 (Soft OFF) LOW LOW LOW
G3 LOW LOW LOW
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VCUAA
Date: Tuesday, October 16, 2012 Sheet 4 of 53
A B C D E
A B C D E
UC1B 100 MHz
J3 CLK_CPU_DMI
BCLK CLK_CPU_DMI <25> +1.05VS_VCCP
H2 CLK_CPU_DMI#
BCLK# CLK_CPU_DMI# <25>
MISC
MISC
@
CLOCKS
1000P_0402_50V7K 2 1 CC62 PM_DRAM_PWRGD_R H_SNB_IVB# F49
<29> H_SNB_IVB# PROC_SELECT#
DPLL_REF_CLK AG3 DPLL_REF_CLK DPLL_REF_CLK# RC1571 2 1K_0402_5%
@
DPLL_REF_CLK# AG1 DPLL_REF_CLK#
1000P_0402_50V7K 2 1 CC63 H_PWRGOOD_R T1 PAD TP_SKTOCC# C57 DPLL_REF_CLK RC1581 2 1K_0402_5%
PROC_DETECT#
T2 PAD H_CATERR# C49 @
CATERR# H_DRAMRST# 1 2
THERMAL
THERMAL
1 CC34 180P_0402_50V8J 1
H_PECI A48 AT30 H_DRAMRST#
+1.05VS_VCCP <40> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
by ESD requestion and place near CPU
RC159 BF44 SM_RCOMP_0 RC56 2 1 140_0402_1% DDR3 Compensation Signals
DDR3
MISC
RC44 SM_RCOMP[0]
2 1 62_0402_5% H_PROCHOT# <40> H_PROCHOT# 1 2 H_PROCHOT#_R C45 PROCHOT# SM_RCOMP[1] BE43 SM_RCOMP_1 RC59 2 1 25.5_0402_1% Layout Note:Place these
56_0402_5% BG43 SM_RCOMP_2 RC61 2 1 200_0402_1% resistors near Processor
SM_RCOMP[2]
RC45 2 1 10K_0402_5% H_PWRGOOD H_THERMTRIP# D45
<29> H_THERMTRIP# THERMTRIP#
PRDY# N53
PREQ# N55
L56 XDP_TCK T3 PAD @
TCK XDP_TMS T4 PAD @
TMS L55
PWR MANAGEMENT
PWR MANAGEMENT
J58 XDP_TRST# 1 2 Routed as a single daisy chain
TRST# RC55 51_0402_5%
JTAG & BPM
@ <26> H_PM_SYNC H_PM_SYNC C48 M60 XDP_TDI
1000P_0402_50V7K 2 PM_SYNC TDI
1 CC70 H_PECI
TDO L59 XDP_TDO T6 PAD @
T7 PAD @
@
1000P_0402_50V7K 2 1 CC67 H_PM_SYNC <29> H_PWRGOOD 1 @ 2 H_PWRGOOD_R B46
RC183 0_0402_5% UNCOREPWRGOOD
DBR# K58
@
1000P_0402_50V7K 2 1 CC66 BUF_CPU_RST#
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R BE45 G58
RC170 130_0402_5% SM_DRAMPWROK BPM#[0]
BPM#[1] E55
BPM#[2] E59
2 Please place near JCPU BPM#[3] G55
G59 2
BUF_CPU_RST# BPM#[4]
D44 RESET# BPM#[5] H60
BPM#[6] J59
BPM#[7] J61
+3VALW_PCH
Close to CPU side
2 1 DRAMPWROK +3VALW_PCH
RC11 200_0402_5% +1.5V_CPU
2 1 IVY-BRIDGE_BGA1023
1
10K_0402_5% 0.1U_0402_10V7K
+3VS 2 RC13 1 CC33 RC14
UC3 200_0402_5%
5
74AHC1G09GW_TSSOP5
2
1 2 1
P
<26,40> PM_PWROK
RC12 @ 0_0402_5% B 4 PM_SYS_PWRGD_BUF
O
1
<26> DRAMPWROK 2 A
G
RC25
39_0402_5%
3
@
2
1 @ 2 0_0402_5%
RC184
1
QC2 D
<34,42,9> SUSP SUSP 2
G
2N7002KW_SOT323-3
S@
3
3 3
Buffered Rest to CPU XDP Connector FAN Control Circuit
+3VS
+5VS +3VS
1 0.1U_0402_10V7K
1
CC36 1A JFAN @
+1.05VS_VCCP 1 @ 2 +FAN1 R2 7
PLT_RST# <28,34,35,40,41> GND2
2 R1 0_0603_5% 10K_0402_5% 6
2 GND1
5 5
1
UC2 C3 4
2
PLT_RST# RC38 10U_0805_10V6K 4
1 OE# <40> FANPWM 3 3
5 75_0402_5% @ 1 2
VCC <40> FAN_SPEED1 2
1 +FAN1 1
RC35 C4 1
2
2
IN 43_0402_1% 0.01U_0402_25V7K ACES_88266-05001
4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# @
OUT 2
3 GND
1
74AHC1G125GW_SOT353-5 RC40
0_0402_5%
@
2
1
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