Service Manuals, User Guides, Schematic Diagrams or docs for : Dell 1088- vm9_a00_0725_uma
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VER : 1A
VM9/VM8 Block Diagram
A A
FAN & THERMAL POWER
Celeron M540 EMC1423-1-AIZL-TR
PG 31 REGULATOR CPU VR
POWER (478 Pin) +1.5V_RUN/+1.05V_VCCP
SYSTEM PG 37 PG 39
RESET CIRCUIT PG 35 CLOCK REGULATOR REGULATOR
SLG8SP513V +1.8V_SUS/+1.25V_RUN +3.3V_ALW/+5V_SUS/+15V_ALW
BATT (QFN-64)
PG 3,4 /+0.9V_DDR_VTT
AC/BATT CHARGER PG 36 PG 17 PG 38 PG 40
CONNECTOR 533 MHz FSB
RUN POWER SW
PG 42 +3.3V_SUS/+5V_SUS
+5V/+3.3V/+1.8V PG 41 LVDS Panel Connector
Crestline (WXGA) PG 18
965GM
B
VGA B
CRT CONN.
DDR2-SODIMM*2 533 MHZ DDR II 1299 uFCBGA PG 19
PG 15,16
PG 5,6,7,8,9,10
SATA-ODD SATA
DMI interface USB2.0 x 2
PG 28 USB conn x 2
PG 27
SATA-HDD SATA
PG 28
RTL8102EL RJ45/Magnetics
PCIE
ICH8-M (10/100) PG 34
PG 34
Bluetooth USB 2.0 676 BGA
C C
PG 26 PCIE MINI-CARD
WLAN
IHDA PG 26
PG 11,12,13,14
AUDIO/AMP
MODEM (AMOM) LPC 1394
CX20561-12Z 1394 CONN.
3-in-1 Card Reader PG 22
CX20548-11Z 33MHz PCI
TPA6017A2 PCMCIA
PG 32 PG 33 KBC IEEE1394 Card Reader CONN.
PG 21
ITE8512
18X8
Keyboard
Audio PG 23 R5C847 PG 20 PCMCIA CONN.
Audio SPK RJ-11conn PG 29 PG 21
Jacks x3
conn 2Wx1 SPI PS/2
PG 32 PG 33
PG 32
FLASH USER
Touchpad
D
2M bytes INTERFACE D
PG 20
PG 24 PG 29 QUANTA
Title
COMPUTER
Schematic Block Diagram
Size Document Number Rev
VM9/VM8 1A
Date: Wednesday, June 25, 2008 Sheet 1 of 53
1 2 3 4 5 6 7 8
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
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Table of Contents Power States
CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE PAGE DESCRIPTION SIGNAL ACTIVE IN
1 Schematic Block Diagram
2 Front Page +PWR_SRC 10V~+19V 4,26,32,34,46,48,49,51,52,56 MAIN POWER S0~S5
3-4 Merom
+RTC_CELL +3.0V~+3.3V 11,14,31,32 RTC S0~S5
5-10 Crestline
A 11-14 ICH8M +3.3V_ALW +3.3V 3,31,32,34,36,37,38,44,46,49,52,53,54 8051 POWER ALWON S0~S5 A
15-16 DDRII SO-DIMM(200P)
+5V_ALW +5V 35,36,46,48,49,52,53,54,56 LCD/CHARGE POWER ALWON S0~S5
17 Clock Generator
18 HDMI +15V_ALW +15V 26,36,37,52,53 LARGE POWER +5V_ALW S0~S5
23 LCD Conn. & SSP
+3.3V_LAN +3.3V 42,43 LAN POWER AUX_ON
24 CRT Conn
25 SATA Conn +5V_SUS +5V 14,38,51,53 SLP_S5# CTRLD POWER SUS_ON
26-27 CARD READER/Conn & 1394
+3.3V_SUS +3.3V 3,11,12,13,14,26,30,37,38,43,48,49,51,53 SLP_S5# CTRLD POWER 3.3V_SUS_ON
28 Express Card & Smart Card
29-30 Mini Card +1.8V_SUS +1.8V 6,8,9,15,48,49,53 SODIMM POWER DDR_ON
31 SIO (ITE8512)
+0.9V_DDR_VTT +0.9V 16,49,53 SODIMM POWER 0.9V_DDR_VTT_ON
32 FLASH/RTC
33 USB +5V_RUN +5V 14,18,27,36,37,38,39,40,41,53 SLP_S3# CTRLD POWER RUN_ON
35 TP / KEYBOARD 14,18,27,36,37,38,39,40,41,53
+3.3V_RUN +3.3V SLP_S3# CTRLD POWER 3.3V_RUN_ON
36 SWITCH /LED
B 37 FAN & Thermal +1.8V_RUN +1.8V 18,38,53 SDVO POWER RUN_ON B
38-39 Audio CODEC(ALC888)/Phone Jack
+1.5V_RUN +1.5V 4,9,14,30,33,34,48,53,56 CALISTOGA/ICH8 POWER 1.5V_RUN_ON
40-41 LOM / Switch
44 System Reset Circuit +1.25V_RUN +1.25V 6,9,14,49,53 CALISTOGA/ICH8 POWER 1.25V_RUN_ON
46 Battery Selector & Charger
+1.05V_VCCP +1.05V 3,4,5,6,8,9,11,14,48,56 CPU/CALISTOGA/ICH8 POWER 1.05V_RUN_ON
48 1.05VCCP / 1.5VRUJN
49 DDR2_1.8VSUS, 0.9V +VCC_CORE +0.7V~+1.77V 4,51,56 CPU CORE POWER IMVP_VR_ON
51 CPU_ISL6266(2phase) LCDVCC_TST_EN
+LCDVCC +3.3V 26 LCD Power & ENVDD
52 MAX8744 (+5.5V,+3,3V)
53 RUN Power Switch +5V_MOD +5V 36 Module Power MODC_EN#
54 DCIN,Batt
+5V_HDD +5V 36 HDD Power HDDC_EN#
55 PAD& SCREW
56 EMI CAP +PBATT +10V~+17V MAIN BATTERY CHG_PBATT
57 SMBUS BLOCK
+SBATT +10V~+17V SECOND BATTERY CHG_SBATT
58 Power Block Dianram
C C
GND PLANE PAGE DESCRIPTION
8731AGND
46
AGND_0.9V
49
AGND_DC/DC
52
AGND_DC2
48
AGND_DDR
49
AGND_ISL6260
51
GND ALL
D D
QUANTA
Title
COMPUTER
Index & Power Status
Size Document Number Rev
VM9/VM8 1A
Date: Wednesday, June 25, 2008 Sheet 2 of 53
1 2 3 4 5 6 7 8
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
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H_A#[3..16] U22A H_D#[0..63] U22B H_D#[0..63]
5 H_A#[3..16] 5 H_D#[0..63] H_D#[0..63] 5
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
H_A#4 A[3]# ADS# H_ADS# 5 H_D#1 D[0]# D[32]# H_D#33
L5 A[4]# BNR# E2 H_BNR# 5 F24 D[1]# D[33]# AB24
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
H_A#6 A[5]# BPRI# H_BPRI# 5 H_D#3 D[2]# D[34]# H_D#35
K5 A[6]# G22 D[3]# D[35]# V26
H_A#7 M3 H5 H_D#4 F23 V23 H_D#36
A[7]# DEFER# H_DEFER# 5 D[4]# D[36]#
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
H_A#9 A[8]# DRDY# H_DRDY# 5 H_D#6 D[5]# D[37]# H_D#38
J1 A[9]# DBSY# E1 H_DBSY# 5 E25 D[6]# D[38]# U25
H_A#10 N3 +1.05V_VCCP H_D#7 E23 U23 H_D#39
A[10]# H_BR0# 5 D[7]# D[39]#
ADDR GROUP 0
ADDR GROUP 0
DATA GRP 0
H_A#11 Layout Note: H_D#8 H_D#40
DATA GRP 2
P5 A[11]# BR0# F1 K24 D[8]# D[40]# Y25
H_A#12 P2 R62 56 Place R44 H_D#9 G24 W22 H_D#41
A[12]# D[9]# D[41]#
1
H_A#13 L2 D20 H_IERR# 1 2 H_D#10 J24 Y23 H_D#42
+1.05V_VCCP
CONTROL
A
H_A#14 P4
A[13]# IERR#
B3 R40 close to H_D#11 J23
D[10]# D[42]#
W24 H_D#43 A
A[14]# INIT# H_INIT# 11 CPU. D[11]# D[43]#
H_A#15 P1 51/F H_D#12 H22 W25 H_D#44
A[15]# H_LOCK# 5 D[12]# D[44]#
H_A#16 H_D#13 H_D#45
R1
M1
A[16]# LOCK# H4 10 H_D#14
F26
K22
D[13]# D[45]# AA23
AA24 H_D#46
5 H_ADSTB#0
2
H_REQ#[0..4] ADSTB[0]# R41 H_D#15 D[14]# D[46]# H_D#47
5 H_REQ#[0..4] RESET# C1 1 2 0 0603 H_RESET# 5 H23 D[15]# D[47]# AB25
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 5 5 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 5
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 5 5 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 5 5 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 5
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# 5 H_D#[0..63] H_D#[0..63]
H_REQ#4 L1
H_A#[17..35] REQ[4]# 5 H_D#[0..63] H_D#[0..63] 5
G6 H_D#16 N22 AE24 H_D#48
5 H_A#[17..35] HIT# H_HIT# 5 D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# 5 D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# H_D#19 D[18]# D[50]# H_D#51
R3 A[19]# BPM[0]# AD4 R23 D[19]# D[51]# AB22
H_A#20 W6 AD3 Layout Note: H_D#20 L23 AB21 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
ADDR GROUP 1
ADDR GROUP 1
H_A#21 U4 AD1 Place voltage H_D#21 M24 AC26 H_D#53
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# H_D#22 D[21]# D[53]# H_D#54
Y5 AC4 L22 AD20
A[22]# BPM[3]# divider within D[22]# D[54]#
DATA GRP 1
H_A#23 H_D#23 H_D#55
DATA GRP 3
U1 A[23]# PRDY# AC2 M23 D[23]# D[55]# AE22
H_A#24 R4 AC1 0.5" of GTLREF H_D#24 P25 AF23 H_D#56
H_A#25 A[24]# PREQ# ITP_TCK H_D#25 D[24]# D[56]# H_D#57
T5 A[25]# TCK AC5 pin P23 D[25]# D[57]# AC25
H_A#26 T3 AA6 ITP_TDI H_D#26 P22 AE21 H_D#58
H_A#27 A[26]# TDI ITP_TDO H_D#27 D[26]# D[58]# H_D#59
W2 A[27]# TDO AB3 T24 D[27]# D[59]# AD21
H_A#28 W5 AB5 ITP_TMS +1.05V_VCCP H_D#28 R24 AC22 H_D#60
H_A#29 A[28]# TMS ITP_TRST# H_D#29 D[28]# D[60]# H_D#61
Y4 A[29]# TRST# AB6 L25 D[29]# D[61]# AD23
H_A#30 U2 C20 ITP_DBRESET# H_D#30 T25 AF22 H_D#62
A[30]# DBR# ITP_DBRESET# 13 D[30]# D[62]#
2
H_A#31 V4 H_D#31 N25 AC23 H_D#63
H_A#32 A[31]# R67 R380 D[31]# D[63]#
W3 A[32]# 56 5 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 5
H_A#33 AA4 THERMAL 2 1 1K/F M26 AF24
A[33]# +1.05V_VCCP 5 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 5
H_A#34 AB2 N24 AC20
A[34]# 5 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 5
B H_A#35 AA3 D21 H_PROCHOT# B
PAD T3
1
A[35]# PROCHOT# H_THERMDA V_CPU_GTLREF COMP0
5 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 H_THERMDA 31 AD26 GTLREF COMP[0] R26 Note:
B25 H_THERMDC CPU_TEST1 C23 MISC COMP[1] U26 COMP1 H_DPRTSTP need to daisy chain
THERMDC H_THERMDC 31 TEST1
1
A6 CPU_TEST2 D25 AA1 COMP2
11 H_A20M# A20M# TEST2 COMP[2] from ICH8 to IMVP6 to CPU.
A5 C7 H_THERM R379 CPU_TEST3 C24 Y1 COMP3
11 H_FERR# FERR# THERMTRIP# TEST3 COMP[3]
ICH
ICH
C4 R44 2K/F CPU_TEST4 AF26
11 H_IGNNE# IGNNE# 56 TEST4
1 2 CPU_TEST5 AF1 E5
+1.05V_VCCP TEST5 DPRSTP# H_DPRSTP# 6,11,39
D5 H CLK CPU_TEST6 A26 B5
2
11 H_STPCLK# STPCLK# TEST6 DPSLP# H_DPSLP# 11
11 H_INTR C6 LINT0 DPWR# D24 H_DPWR# 5
11 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 17 6,17 CPU_MCH_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD 11
11 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 17 6,17 CPU_MCH_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 5
6,17 CPU_MCH_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# 39
M4 RSVD[01]
N5 RSVD[02]
T2 C487 *2200P_NC 47387-4784
RSVD[03] H_THERMDA H_THERMDC R75 *1K/F_NC
V3 RSVD[04] 1 2
RESERVED
B2 2 1 CPU_TEST1
RSVD[05] 50 R74 *1K/F_NC PAD T145 CPU_TEST3
C3 RSVD[06]
D2 Voltage Level shift 2 1 CPU_TEST2 PAD T146 CPU_TEST5
RSVD[07] C509 *0.1U_NC
D22 RSVD[08]
For EA test use D3 +1.05V_VCCP +3.3V_ALW 2 1 CPU_TEST4 For the purpose of testability, route these signals
RSVD[09]
F6 RSVD[10] through a ground referenced Z0 = 55ohm trace that
H_DSTBN#0 10
ET11 1 For EA test use CPU_TEST6 ends in a via that is near a GND via and is
2
H_DSTBN#2 R373 *0_NC
ET17 1
ET16 1 H_DSTBP#2
ET5 1 H_ADSTB#0 accessible through an oscilloscope connection.
1 H_D#41 47387-4784 1 H_A#14 R50 Place C close to the
ET15 H_DSTBN#3 ET12 H_A#16
1 1 *2.2K_NC CPU_TEST4 pin. Make sure
ET22 ET1
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