Service Manuals, User Guides, Schematic Diagrams or docs for : Dell DELL_Vostro_1400_QUANTA_fm5-corsica
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Cosica / Gilligan UMA VER : 2B
C&G UMA M/B PCB
A A
SYSTEM PG 38 POWER
POWER Merom CLOCK
RESET CIRCUIT gen.
(478 Micro-FCPGA) REGULATOR PG 43
BATT +1.5V_RUN/+1.05V_VCCP CPU VR PG 45 CK505
PG 40 PG 3,4
AC/BATT CHARGER
REGULATOR PG 42 PG 17
CONNECTOR +1.8V_SUS/+1.25V_SRC_M
RUN POWER SW (Symbol Rev.09) DC/DC PG 44
PG 41 PG 39
+3.3V_SUS/+5V_SUS/+3.3V_M +1.05V_M/+0.9V_DDR_VTT +3.3V_ALW/+5V_ALW/+15V_ALW
+5V/+3.3V/+1.8V/+1.25_RUN
PG 41
667/800 MHz FSB
LVDS
Panel Connector PG 18
Crestline
DDR2-SODIMM1 533/667 MHZ DDR II TVOUT S-Video CONN.
B
1299 uFCBGA B
PG 15,16 PG 19
PG 5,6,7,8,9,10
VGA CRT CONN.
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533/667 MHZ DDR II
DDR2-SODIMM2 PG 19
(Symbol Rev.09)
PG 15,16
USB2.0 (P0,P1) (EXT SIDE)
USB X 4
USB2.0 (P2,P3) (EXT BACK)
IDE PG 27
DMI interface
Fix ODD 1394 & Conn.
PG 23 PG 21
R5C833 Controller
33MHz PCI
PG 20-22
ICH8-M 8 in 1 Conn.
SATA - HDD SATA PG 22
33MHz PCI LOM BCM4401 B0
PG 23 676 BGA
PG 35,36
IHDA PG 11,12,13,14 PCIEx1 EXPRESS-CARD
C USB2.0 (P6) C
PG 26
MDC BTB PCIEX3
AUDIO/AMP connector. (Symbol Rev.09) USB2.0 (P7,P9)
PG 32,33 MINI-CARD x3
PG 26
WPAN & WWAN & WLAN
LPC PG 24,25
SPI
Audio jack
S/PDIF
BTB Conn.
PG 20
PG 33 PG 28 SIO SIO USB2.0 (P5) Dig Camera
MEC5025 ECE5011
BC PG 33
To connector for Media 128KB Flash BC Expander
PS/2 TMKBC GPIOs
board/Touch pad/KBC
module Media board
PG 31 Controller signal 128 Pins VTQFP 128 Pins VTQFP
PG 28 PG 29
D Digitally signed by fdsf D
SPI
DN: cn=fdsf, o=fsdfsd,
USER FAN & THERMAL QUANTA ou=ffsdf,
FLASH CIR INTERFACE EMC4001 COMPUTER
PG 30 PG 31 PG 37 PG 34
Title
Schematic Block Diagram1
email=fdfsd@fsdff, c=US
Size Document Number
C & G UMA
Date: 2010.03.29 Rev
2A
Date: Thursday, January 25, 2007 18:08:03 +07'00'
Sheet 1 of 60
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
INDEX Power & Ground
Pg# Description DNI LIST Label Pg# Description Control Signal
1 Schematic Block Diagram DC_IN+ AC ADAPTER (19V)
2 Front Page PBATT+ MAIN BATTERY + (10~17V)
3-4 Merom PBATT+ SECOND BATTERY + (10~17V)
A A
5-10 Crestline PWR_SRC MAIN POWER (10~19V)
11-14 ICH8M RTC_PWR3_3V RTC & +3.3V_RTC_LDO(3.3V)
15-16 DDRII SO-DIMM(200P) +VCC_CORE CPU CORE POWER (1.5V) RUNPWROK
17 Clock Generator +15V_ALW LARGE POWER (15V) SUS_ON
18-19 VGA/LVDS/CRT/S-Video +3.3V_RUN SLP_S3# CTRLD POWER RUN_ON
20 8 in 1 controller +3.3V_SUS SLP_S5# CTRLD POWER SUS_ENABLE
21 1394 function +3.3V_ALW 8051 POWER (3.3V) ALWON/THERM_STP#
22 8 in 1 connector +5V_RUN SLP_S3# CTRLD POWER RUN_ON
23 SATA & IDE Conn +5V_SUS SLP_S5# CTRLD POWER SUS_ON
24-25 Mini Card (WLAN/WPAN/WWAN) +5V_HDD HDD POWER (5V) +5V_RUN
B B
26 Express Card + MDC BTB Connector +5V_MOD MODULE POWER (5V) HDD_EN
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27 USB Conn. +5V_ALW LCD/CHARGE POWER (5V)
28 SIO (MEC5025) +VDDA AUDIO ANALOG POWER (5V) AUDIO_AVDD_ON
29 SIO (MEC5011) +1.5V_RUN CALISTOGA/ICH7 POWER RUN_ON
30 Flash / RTC +1.05V_VCCP CPU/CALISTOGA/ICH7 POWER RUN_ON
31 TP/KB/Media/CIR Conn. +1_8V_SUS SODIMM POWER SUSPWROK_5V
32-33 Audio CODEC(STAC9200)/Phone Jack +1.8V_RUN SDVO POWER RUN_ON
34 FAN & Thermal +0.9V_DDR_VTT SODIMM POWER RUN_ON
35-36 LOM (BCM4401) +3.3V_LAN LAN POWER AUX_EN
C 37 Dash/LED/BT Conn. C
38 System reset CKT.
39 RUN Power Switch GND ALL PAGES DIGITAL GROUND
40 Battery Charger AGND_ISL6260 CPU GND
41 DCIN/Batt Conn. AGND_TPS51120 DC/DC POWER GND
42 1.25V,1.8V,0.9V AGND1 VTT POWER GND
43 1.5VSUS,1.05V(VTT) AGND2 VTT POWER GND
44 D/D Power 8731AGND CHARGER GND
45 CPU_ISL6260(3phase)
46 EMI CAP & Screw Hole.
D D
QUANTA
Title
COMPUTER
Index, DNI, Power & Ground
Size Document Number Rev
C & G UMA 2A
Date: Friday, January 19, 2007 Sheet 2 of 60
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
H_D#[0..63] U14B H_D#[0..63]
5 H_D#[0..63] H_D#[0..63] 5
H_D#0 E22 Y22 H_D#32
H_A#[3..16] U14A H_D#1 D[0]# D[32]# H_D#33
5 H_A#[3..16] F24 D[1]# D[33]# AB24
H_A#3 J4 H1 H_D#2 E26 V24 H_D#34
A[3]# ADS# H_ADS# 5 D[2]# D[34]#
H_A#4 L5 E2 H_D#3 G22 V26 H_D#35
A[4]# BNR# H_BNR# 5 D[3]# D[35]#
H_A#5 L4 G5 H_D#4 F23 V23 H_D#36
A[5]# BPRI# H_BPRI# 5 D[4]# D[36]#
H_A#6 K5 H_D#5 G25 T22 H_D#37
H_A#7 A[6]# H_D#6 D[5]# D[37]# H_D#38
M3 A[7]# DEFER# H5 H_DEFER# 5 E25 D[6]# D[38]# U25
H_A#8 N2 F21 H_D#7 E23 U23 H_D#39
A[8]# DRDY# H_DRDY# 5 D[7]# D[39]#
DATA GRP 0
DATA GRP 2
H_A#9 J1 E1 H_D#8 K24 Y25 H_D#40
A[9]# DBSY# H_DBSY# 5 D[8]# D[40]#
H_A#10 N3 H_D#9 G24 W22 H_D#41
A A[10]# H_BR0# 5 D[9]# D[41]# A
ADDR GROUP 0
ADDR GROUP 0
H_A#11 P5 F1 H_D#10 J24 Y23 H_D#42
H_A#12 A[11]# BR0# H_D#11 D[10]# D[42]# H_D#43
P2 A[12]# 1 2 +1.05V_VCCP J23 D[11]# D[43]# W24
H_A#13 L2 D20 H_IERR# R384 56_0402 H_D#12 H22 W25 H_D#44
CONTROL
H_A#14 A[13]# IERR# H_D#13 D[12]# D[44]# H_D#45
P4 A[14]# INIT# B3 H_INIT# 11 F26 D[13]# D[45]# AA23
H_A#15 P1 H_D#14 K22 AA24 H_D#46
H_A#16 A[15]# H_D#15 D[14]# D[46]# H_D#47
R1 A[16]# LOCK# H4 H_LOCK# 5 H23 D[15]# D[47]# AB25
5 H_ADSTB#0 M1 ADSTB[0]# 5 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 5
H_REQ#[0..4] C1 H_RESET# H26 AA26
5 H_REQ#[0..4] RESET# H_RESET# 5 5 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
H_REQ#0 K3 F3 H25 U22
REQ[0]# RS[0]# H_RS#0 5 5 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 5
H_REQ#1 H2 F4
REQ[1]# RS[1]# H_RS#1 5 H_D#[0..63] H_D#[0..63]
H_REQ#2 K2 G3
REQ[2]# RS[2]# H_RS#2 5 5 H_D#[0..63] H_D#[0..63] 5
H_REQ#3 J3 G2 H_D#16 N22 AE24 H_D#48
REQ[3]# TRDY# H_TRDY# 5 D[16]# D[48]#
H_REQ#4 L1 H_D#17 K25 AD24 H_D#49
H_A#[17..35] REQ[4]# H_D#18 D[17]# D[49]# H_D#50
5 H_A#[17..35] HIT# G6 H_HIT# 5 P26 D[18]# D[50]# AA21
H_A#17 Y2 E4 H_D#19 R23 AB22 H_D#51
A[17]# HITM# H_HITM# 5 D[19]# D[51]#
H_A#18 U5 Layout Note: H_D#20 L23 AB21 H_D#52
H_A#19 A[18]# ITP_BPM#0 H_D#21 D[20]# D[52]# H_D#53
R3 A[19]# BPM[0]# AD4 Place voltage M24 D[21]# D[53]# AC26
H_A#20 W6 AD3 ITP_BPM#1 H_D#22 L22 AD20 H_D#54
A[20]# BPM[1]# divider within D[22]# D[54]#
ADDR GROUP 1
DATA GRP 1
DATA GRP 3
H_A#21 U4 AD1 ITP_BPM#2 H_D#23 M23 AE22 H_D#55
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# ITP_BPM#3 0.5" of GTLREF H_D#24 D[23]# D[55]# H_D#56
Y5 A[22]# BPM[3]# AC4 P25 D[24]# D[56]# AF23
H_A#23 U1 AC2 ITP_BPM#4 pin H_D#25 P23 AC25 H_D#57
H_A#24 A[23]# PRDY# ITP_BPM#5 H_D#26 D[25]# D[57]# H_D#58
R4 A[24]# PREQ# AC1 P22 D[26]# D[58]# AE21
H_A#25 T5 AC5 ITP_TCK H_D#27 T24 AD21 H_D#59
H_A#26 A[25]# TCK ITP_TDI +1.05V_VCCP H_D#28 D[27]# D[59]# H_D#60
T3 A[26]# TDI AA6 R24 D[28]# D[60]# AC22
H_A#27 W2 AB3 ITP_TDO H_D#29 L25 AD23 H_D#61
H_A#28 A[27]# TDO ITP_TMS H_D#30 D[29]# D[61]# H_D#62
W5 A[28]# TMS AB5 T25 D[30]# D[62]# AF22
2
H_A#29 Y4 AB6 ITP_TRST# H_D#31 N25 AC23 H_D#63
H_A#30 A[29]# TRST# ITP_DBRESET# R448 D[31]# D[63]#
U2 A[30]# DBR# C20 ITP_DBRESET# 13,29 5 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 5
H_A#31 V4 1K/F_0402 M26 AF24
A[31]# 5 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 5
B H_A#32 W3 2 1 +1.05V_VCCP N24 AC20 B
A[32]# 5 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 5
H_A#33 AA4 THERMAL R383 56_0402
1
H_A#34 A[33]# CPU_PROCHOT# 1 V_CPU_GTLREF AD26 COMP0
AB2 A[34]# 2 EC_CPU_PROCHOT# 28 GTLREF COMP[0] R26 Note:
H_A#35 AA3 D21 R367 0_NC CPU_TEST1 C23 MISC U26 COMP1 H_DPRTSTP need to daisy chain
A[35]# PROCHOT# TEST1 COMP[1]
2
V1 A24 H_THERMDA CPU_TEST2 D25 AA1 COMP2
5 H_ADSTB#1 ADSTB[1]# THERMDA H_THERMDA 34 TEST2 COMP[2] from ICH8 to IMVP6 to CPU.
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B25 H_THERMDC CPU_TEST3 C24 Y1 COMP3
THERMDC H_THERMDC 34 TEST3 COMP[3]
A6 R454 CPU_TEST4 AF26
11 H_A20M# A20M# TEST4
A5 C7 H_THERMTRIP# 2K/F_0402 CPU_TEST5 AF1 E5
11 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 34 TEST5 DPRSTP# H_DPRSTP# 6,11,45
ICH
ICH
C4 CPU_TEST6 A26 B5
11 H_IGNNE# H_DPSLP# 11
1
IGNNE# TEST6 DPSLP#
1 2 +1.05V_VCCP DPWR# D24 H_DPWR# 5
D5 H CLK R370 56_0402 B22 D6
11 H_STPCLK# STPCLK# 6,17 CPU_MCH_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 11
11 H_INTR C6 LINT0 6,17 CPU_MCH_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 5
11 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 17 6,17 CPU_MCH_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# 45
11 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 17
MLX_47387-4784
M4 RSVD[01]
N5 RSVD[02]
T2 RSVD[03]
V3 H_THERMDA 1 2 H_THERMDC PAD T19 CPU_TEST3
RSVD[04]
RESERVED
B2 C168 1 2 CPU_TEST1 PAD T95 CPU_TEST5
RSVD[05] 2200P/50V/0402_NC R368 1K/F_0402_NC
C3 RSVD[06]
D2 1 2 CPU_TEST2 For the purpose of testability, route these signals
RSVD[07] R374 1K/F_0402_NC
D22 RSVD[08] through a ground referenced Z0 = 55ohm trace that
D3 2 1 CPU_TEST4
RSVD[09] C538 .1U/10V/0402_NC ends in a via that is near a GND via and is
F6 RSVD[10]
1 2 CPU_TEST6 accessible through an oscilloscope connection.
R153 0_0402_NC
MLX_47387-4784 Place C close to the
C CPU_TEST4 pin. Make sure COMP0 C
CPU_TEST4 routing is FSB BCLK BSEL2 BSEL1 BSEL0
COMP1
reference to GND and away 533 133 0 0 1 COMP2
Populate ITP700Flex for bringup For Support XDP: from other noisy signal. COMP3
1. TIP_BPM#5 need PU 51ohms to +1.05V_VCCP. 667 166 0 1 1
+1.05V_VCCP 2. Populate R5,R1. Change R4 & R361 to 51 ohms.
2
2
2
2
800 200 0 1 0 R416
3. Changed R6 & R346 to 51 ohms. R429 27.4/F_0402
4. Depopulate R2 and changed R8 to 1K/F. R459 54.9/F_0402
R452 27.4/F_0402
1
1
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