Service Manuals, User Guides, Schematic Diagrams or docs for : Dell Dell Inspiron 17R N7110_QUANTA R03_V03 UMA
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
>> Download Dell Inspiron 17R N7110_QUANTA R03_V03 UMA documenatation <<
Text preview - extract from the document
1 2 3 4 5 6 7 8
DIS R03/V03 UMA BLOCK DIAGRAM
DDRIII-SODIMM1 DDRIII 1333 MT/s
A
A 00 PAGE 16 A
CPU
DDRIII-SODIMM2 DDRIII 1333 MT/s
Sandy Bridge 45W
A 01 PAGE 17
PGA 989
PAGE 4~8
PAGE 19 PAGE 19
FDI LINK DMI LINK
2.5GT /s 2.5GT /s
iGFX Interfaces
SATA4 300MB /S
PAGE 20
B 1600 x 900 (HD) PAGE 18 B
PAGE 20
SATA0 300MB /S
Mobile Intel
PAGE 21
PAGE 20 PAGE 18 PAGE 22 PAGE 28 PAGE 27
Series 6 Chipset
USB2.0 USB[0] USB[11] USB[8] USB[10] USB[12]
SATA1 300MB /S
USB[8]
PAGE 21 PCH
PAGE 03 IO Board PAGE 02
SMBUS HM67
PAGE 21
USB[4] USB[5] PCIE[3] EXP Board
Couger Point
PAGE 05 PAGE 04 PAGE 06 LED Board
PCIE[1] PCIE[2]
BGA 989
PCIE[5]
C
25 mm X 25 mm PAGE 05 PAGE 07
PB Board Charger
PAGE 35
C
USB[6]
32.768KHz 3/5V
PAGE 08
TP Board PAGE 36
IHDA PAGE 09 USB[2] 1.5V_SUS/0.75V_DDR
LPC PAGE 9~15 PAGE 37
PAGE 28
PAGE 10 HotKey Board
25MHz Batt/DC-IN
PAGE 34
SPI
PAGE 28 1.05V_PCH
25MHz PAGE 38
32.768KHz
VCCSA
PAGE 23 PAGE 39
PAGE 27
PAGE 29
PAGE 25
CPU_CORE
PAGE 40
D D
1.8V_RUN
PAGE 38
PAGE 31 PAGE 27 PAGE 25 PAGE 25 PAGE 25
PAGE 26
Quanta Computer Inc.
PROJECT : R03/V03
Size Document Number Rev
2A
BLOCK DIAGRAM
Date: W ednesday, October 06, 2010 Sheet 1 of 42
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+RTC_CELL +DC_IN +VCHGR +5V_SUS +VCC_CORE
+DC_IN_SS +PWR_SRC +3.3V_SUS +1.05V_PCH
power +PWR_SRC +5V_ALW_2 +1.5V_SUS +5V_RUN
+5V_ALW_2 +3.3V_ALW +1.5V_CPU +3.3V_RUN
+3.3V_ALW +5V_ALW +DDR_VTTREF +1.8V_RUN
+5V_ALW +15V_ALW
+3.3V_LAN (for R03) +1.5V_RUN
+15V_ALW +3.3V_LAN (for V03)
A +3.3V_LAN (for V03) +VCCSA A
+0.75V_DDR_VTT
+LCDVCC
+VCC_GFX_CORE
State
ON ON ON ON ON
S0
S1
S3 ON ON ON ON OFF
B B
ON ON
S4/S5 AC
S4/S5 ON ON OFF OFF
DC Only
AC/DC ON OFF OFF OFF OFF
No Exist
C C
SMBCLK
SMBDATA
SMB_CLK_ME1
SMB_DAT_ME1
AB1A_CLK
AB1A_DATA
D D
Quanta Computer Inc.
PROJECT : R03/V03
Size Document Number Rev
2A
Power Rails
Date: W ednesday, October 27, 2010 Sheet 2 of 42
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
C C
B B
A A
Quanta Computer Inc.
PROJECT : R03/V03
Size Document Number Rev
2A
BLANK
Date: W ednesday, October 06, 2010 Sheet 3 of 42
5 4 3 2 1
5 4 3 2 1
DP & PEG Compensation
+1.05V_PCH
Sandy Bridge Processor (DMI,PEG,FDI)
U17A
PEG_ICOMPO 12mil
D J22 PEG_COMP PEG_ICOMPI, PEG_RCOMPO 4mil, D
PEG_ICOMPI R309 24.9/F_4 EDP_COMP
PEG_ICOMPO J21
[9] DMI_TXN0 B27 DMI_RX#[0] PEG_RCOMPO H22
[9] DMI_TXN1 B25 DMI_RX#[1]
eDP_COMPIO and ICOMPO signals should
[9] DMI_TXN2 A25 DMI_RX#[2] be shorted near balls and
[9] DMI_TXN3 B24 K33
DMI_RX#[3] PEG_RX#[0]
M35
routed within 500 mils
PEG_RX#[1]
[9] DMI_TXP0 B28 DMI_RX[0] PEG_RX#[2] L34
[9] DMI_TXP1 B26 DMI_RX[1] PEG_RX#[3] J35
DMI
[9] DMI_TXP2 A24 DMI_RX[2] PEG_RX#[4] J32
B23 H34 +1.05V_PCH
[9] DMI_TXP3 DMI_RX[3] PEG_RX#[5]
PEG_RX#[6] H31
[9] DMI_RXN0 G21 DMI_TX#[0] PEG_RX#[7] G33
[9] DMI_RXN1 E22 DMI_TX#[1] PEG_RX#[8] G30
F21 F35 R55 24.9/F_4 PEG_COMP
[9] DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
[9] DMI_RXN3 D21 DMI_TX#[3] PEG_RX#[10] E34
PEG_RX#[11] E32
[9] DMI_RXP0 G22 DMI_TX[0] PEG_RX#[12] D33
[9] DMI_RXP1 D22 DMI_TX[1] PEG_RX#[13] D31
PCI EXPRESS* - GRAPHICS
[9] DMI_RXP2 F20 DMI_TX[2] PEG_RX#[14] B33
[9] DMI_RXP3 C21 DMI_TX[3] PEG_RX#[15] C32 PEG_ICOMPI and RCOMPO signals should
be routed within 500 mils
PEG_RX[0] J33
PEG_RX[1] L35
K34 PEG_ICOMPO signals should
PEG_RX[2]
[9] FDI_TXN0 A21 FDI0_TX#[0] PEG_RX[3] H35 be routed within 500 mils
[9] FDI_TXN1 H19 FDI0_TX#[1] PEG_RX[4] H32
[9] FDI_TXN2 E19 FDI0_TX#[2] PEG_RX[5] G34
F18 G31
Intel(R) FDI
C
[9] FDI_TXN3 FDI0_TX#[3] PEG_RX[6] C
[9] FDI_TXN4 B21 FDI1_TX#[0] PEG_RX[7] F33
[9] FDI_TXN5 C20 FDI1_TX#[1] PEG_RX[8] F30
[9] FDI_TXN6 D18 FDI1_TX#[2] PEG_RX[9] E35
[9] FDI_TXN7 E17 FDI1_TX#[3] PEG_RX[10] E33
PEG_RX[11] F32
PEG_RX[12] D34
[9] FDI_TXP0 A22 FDI0_TX[0] PEG_RX[13] E31
G19 C33
[9]
[9]
FDI_TXP1
FDI_TXP2 E20
FDI0_TX[1]
FDI0_TX[2]
PEG_RX[14]
PEG_RX[15] B32 eDP Hot-plug (Disable)
[9] FDI_TXP3 G18 FDI0_TX[3]
[9] FDI_TXP4 B20 FDI1_TX[0] PEG_TX#[0] M29
C19 M32 +1.05V_PCH
[9] FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
[9] FDI_TXP6 D19 FDI1_TX[2] PEG_TX#[2] M31
[9] FDI_TXP7 F17 FDI1_TX[3] PEG_TX#[3] L32
PEG_TX#[4] L29
[9] FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31
J17 K28 R304
[9] FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6]
PEG_TX#[7] J30 *10K_4_NC
[9] FDI_INT H20 FDI_INT PEG_TX#[8] J28
PEG_TX#[9] H29
J19 G27 INT_EDP_HPD
[9] FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
[9] FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29
PEG_TX#[12] F27
PEG_TX#[13] D28
PEG_TX#[14] F26
PEG_TX#[15] E25 CAD Note: Place PU resistor within 2 inches
eDP_ICOMPO 12mil EDP_COMP
A18 eDP_COMPIO of CPU
A17 eDP_ICOMPO PEG_TX[0] M28
eDP_COMPIO 4mil INT_EDP_HPD B16 M33
B eDP_HPD PEG_TX[1] B
PEG_TX[2] M30 This signal can be left as no connect if
PEG_TX[3] L31
C15 L28 entire eDP interface is disabled.
eDP_AUX PEG_TX[4]
D15 eDP_AUX# PEG_TX[5] K30
eDP
PEG_TX[6] K27
PEG_TX[7] J29
C17 eDP_TX[0] PEG_TX[8] J27
F16 eDP_TX[1] PEG_TX[9] H28
Programing Disable eDP interface(BIOS) C16 eDP_TX[2] PEG_TX[10] G28
G15 eDP_TX[3] PEG_TX[11] E28
PEG_TX[12] F28
C18 eDP_TX#[0] PEG_TX[13] D27
E16 eDP_TX#[1] PEG_TX[14] E26
D16 eDP_TX#[2] PEG_TX[15] D25
F15 eDP_TX#[3]
Sandy Bridge_rPGA_4SODIMM_Rev1p0
A A
Quanta Computer Inc.
PROJECT : R03/V03
Size Document Number Rev
2A
Sandy Bridge 1/5
Date: Friday, January 07, 2011 Sheet 4 of 42
5 4 3 2 1
5 4 3 2 1
Sandy Bridge Processor (CLK,MISC,JTAG)
U17B
follow SS8: SNB_IVB# N.A at SNB EDS #27637 0.7v1
BCLK A28 CLK_CPU_BCLKP [13]
MISC
CLOCKS
TP43 C26 PROC_SELECT# BCLK# A27 CLK_CPU_BCLKN [13]
+1.05V_PCH
R186 62/F_4 H_PROCHOT# AN34 R310 1K_4
D [23] H_CPUDET# SKTOCC#
A16 CLK_DP_P_R R305 *0_4_NC CLK_DP_P [13]
Schematic C/L_v1.0, P56 (PU,PD 1k/J) D
DPLL_REF_CLK CLK_DP_N_R R306 *0_4_NC
DPLL_REF_CLK# A15
R311 1K_4
CLK_DP_N [13] (Intel and PD3)
+1.05V_PCH
Reserve (Intel confirm now)
TP_CATERR# AL33
TP34 CATERR#
THERMAL
[23] PECI_EC R445 43/J_4 H_PECI_R AN33 R8 CPU_DRAMRST#
PECI SM_DRAMRST#
DDR3
MISC
[23,35,40] H_PROCHOT# R181 56/J_4 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R153 140/F_4
PROCHOT# SM_RCOMP[0] SM_RCOMP_1 R312 25.5/F_4
SM_RCOMP[1] A5
SM_RCOMP_2 R313 200/F_4
SM_RCOMP_0, SM_RCOMP_1 20mil
SM_RCOMP[2] A4
SM_RCOMP_2 15mil,
Over 130 degree C will [14] PM_THRMTRIP# AN32 THERMTRIP#
drive low
+1.05V_PCH
PRDY# AP29
PREQ# AP27
XDP_TMS R452 51/J_4
AR26 XDP_TCLK XDP_TDI R450 51/J_4
TCK
PWR MANAGEMENT
XDP_TMS XDP_TDO R201 51/J_4
JTAG & BPM
TMS AR27
[9] H_PM_SYNC AM34 AP30 XDP_TRST# R447 51/J_4
PM_SYNC TRST#
C AR28 XDP_TDI C
TDI XDP_TDO XDP_TCLK R202 51/J_4
TDO AP26
[14] H_PW RGOOD AP33 +3.3V_RUN
UNCOREPWRGOOD
R189 10K/J_4
AL35 XDP_DBRST# R443 1K_4
SM_DRAMPW ROK DBR#
V8 SM_DRAMPWROK
XDP_DBRST# use a 1k pull-up to 3.3V_S
BPM#[0] AT28 TRST# use a 51ohm pull down.
+1.05V_PCH R192 *75/J_4_NC AR29
BPM#[1]
BPM#[2] AR30
CPU_PLTRST# R193 *43/J_4_NC
CPU_PLTRST#_R AR33 AT30 When MP, JTAG PU/PD resistor
RESET# BPM#[3]
BPM#[4] AP32
AR31 can be removed?
+3.3V_SUS BPM#[5]
BPM#[6] AT31 Need to confirm with Intel
IN OUT BPM#[7] AR32
L L
H High-Z C333
U8 *0.1U/10V/X7R_4_NC Sandy Bridge_rPGA_4SODIMM_Rev1p0
1 NC VCC 5
[12,23,24] PLTRST# 2 IN Boot S3 S3 RSM
3 4 CPU_PLTRST#
GND OUT
R556 *74LVC1G07GW _NC
B
1.5K +1.5V_CPU B
1%
CPU_PLTRST#_R voltage level Ckt.
DRAM_PWRGD
CPU_PLTRST#_R
100 ns after +1.5V_CPU
1% SYS_PWROK reaches 80%
750
SM_DRAMPWROK
R557
Follow #DG1.0 436735 P107 +1.5V_SUS
DRAMRST# Routing Illustration
R72 R54 *0_4_NC
1K/F_4
Change OD part same with PDC R8239, R8241 change to 5% R63 Q5 BSS138-7-F
1K/F_4
Pin1 Pin2 Pin4 DDR3_DRAMRST#_R 3 1 CPU_DRAMRST#
Copy from PDC +3.3V_SUS [16,17] DDR3_DRAMRST#
L L L
2
+1.5V_CPU
L H L
[13] DDR_HVREF_RST_PCH
H L L R56
C301 C86 4.99K/F_4
R183 0.1U/10V/X7R_4 H H H 0.047U/10V_4
A
200_4 A
R170
5
U6 200/F_4
[9] PM_DRAM_PW RGD 2
4 SM_DRAMPW ROK_R R176 130/F_4 SM_DRAMPW ROK
[9] SYS_PW ROK 1
Quanta Computer Inc.
3
3 1
74AHC1G09GW R184 *39_NC
PROJECT : R03/V03
Follow #DG1.0 436735 P105 Q14 *2N7002K_NC Size Document Number Rev
2
2A
DDR Power Gating Topology PS_S3CNTRL [7,16] Sandy Bridge 2/5
Date: Monday, January 24, 2011 Sheet 5 of 42
5 4 3 2 1
5 4 3 2 1
Sandy Bridge Processor (DDR3)
U17D
U17C
[17] M_B_DQ[63:0] SB_CLK[0] AE2 M_B_CLKP0 [17]
D
SA_CLK[0] AB6 M_A_CLKP0 [16] SB_CLK#[0] AD2 M_B_CLKN0 [17] D
AA6 M_A_CLKN0 [16] M_B_DQ0 C9 R9 M_B_CKE0 [17]
[16] M_A_DQ[63:0] SA_CLK#[0] SB_DQ[0] SB_CKE[0]
M_A_DQ0 C5 V9 M_A_CKE0 [16] M_B_DQ1 A7
M_A_DQ1 SA_DQ[0] SA_CKE[0] M_B_DQ2 SB_DQ[1]
D5 SA_DQ[1] D10 SB_DQ[2]
M_A_DQ2 D3 M_B_DQ3 C8
M_A_DQ3 SA_DQ[2] M_B_DQ4 SB_DQ[3]
D2 SA_DQ[3] A9 SB_DQ[4] SB_CLK[1] AE1 M_B_CLKP1 [17]
M_A_DQ4 D6 AA5 M_A_CLKP1 [16] M_B_DQ5 A8 AD1 M_B_CLKN1 [17]
M_A_DQ5 SA_DQ[4] SA_CLK[◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo