Service Manuals, User Guides, Schematic Diagrams or docs for : Dell Dell Inspiron M102Z - Compal LA-7161P PLM00
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A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : PLM00
1 1
PCB NO : LA-7161P (DAZ0I800100)
BOM P/N : 4319AS31L01
4319AS31L02
4319AS31L03
4319AS31L04
4319AS31L05
4319AS31L06
4319AS31L07
Andros MLK
4319AS31L08
AMD APU (Ontario/Zacate) -FT1 + FCH Hudson-M1
2 2
2011-01-05
REV : 1.0(A00)
3
@ : Nopop Component 3
WWAN@: WWAN function
CONN@: Connector only
Z@ : Zacate
O@ : Ontario
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Cover Sheet
http://hobi-elektronika.net
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 1 of 43
A B C D E
A B C D E
LVDS
LVDS conn. Page 20
TMDS DDR3-SO-DIMM X2
HDMI conn. Page 18 AMD Brazos APU Page 10, 11
DDR3 BUS
VGA FT1
CRT conn. Page 19 1.5V DDRIII 1066 Single Channel
1
BGA 413-Ball 1
19mm x 19mm DDRIII 800~1066MHz
GPP
PCI Express Page 7,8,9
GPP PCIE2 GPP PCIE3 GPP PCIE1
LAN Mini Card UMI
Atheros AR8152 WLAN Mini Card
WWAN
Page 21 Page 25
Page 25
USB port2
RJ45 conn. USB conn.
Page 23
Page 21
USB port0,1
USB conn. x 2
Sub/B & Page 26
2 2
Hudson M1 USB port4 Mini Card
WLAN Page 25
BGA 605-Ball
Clock Generator 23mm x 23mm USB2.0 USB port5 Mini Card
WWAN Page 25 SIM conn.
Page 25
FCH
USB port6
Internal CKG Bluetooth conn.
Page 25
Page 13
Page 12,13,14,15,16
Page 22
USB port8 CardBus 7 in 1 conn.
Realtek RTS5138 Page 22
LPC BUS USB port9
Camera
Page 20
DC/DC Power Button
3
(Power Control) Page 28 Sub/B 3
EC ENE KB926QFE0 CODEC Audio Jack x 2
Sub/B
Page 17 AZ-Audio I/F Realtek ALC259
BATT IN &OTP
Page 32 Page 24
Digital MIC
Camera side
DC IN & DECTOR Int. KBD
Page 17
Page 33
T/P conn.
Page 29
CHARGER SPI ROM
Page 12
Page 34
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Block Diagram
http://hobi-elektronika.net
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 2 of 43
A B C D E
5 4 3 2 1
POWER SEQUENCE
VIN
D D
B+
+3VALW,+5VALW
+1.1VALW
ON/OFFBTN# NOTE1
T1>10ms, +3VALW to RSMRST#
T1
EC->FCH EC_RSMRST#
T2>100ms, RSMRST# to PBTN_OUT#
EC->FCH PBTN_OUT# T2
T3>100ns, PBTN_OUT# to SLP_S5#
T3
FCH->EC SIO_SLP_S5#
T4>10ms, SLP_S5# to SYSON
T4
EC->PWR SYSON
+1.5V
The same with SLP_S5#
FCH->EC SIO_SLP_S3#
T5>10ms, SYSON to SUSP#
T5
EC->PWR SUSP#
C
+3VS,+5VS,+0.75VS C
+1.8VS
+1.1VS
T6>100ms, SUSP# to VR_ON
T6
EC->PWR VR_ON
+APU_CORE
+APU_COREP_NB NOTE2
PWR->EC VGATE
T7>50ms, VGATE to EC_FCH_PWROK
T7
EC->FCH EC_FCH_PWROK
EC->FCH KB_RST#
98ms>T8>150ms, EC_FCH_PWROK to APU_PWRGD
T8
FCH->APU APU_PWRGD
101ms>T9>113ms, EC_FCH_PWROK to A_RST#
T9
FCH->DEVICE A_RST#
FCH->APU LDT_RST#
B B
NOTE1: RSMRST# rise time(10% to 90%)<50ms
fail time<1ms
NOTE2: EC_FCH_PWROK rise time(10% to 90%)<50ms
fail time<1ms
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER SEQUENCE
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 3 of 43
5 4 3 2 1
5 4 3 2 1
D D
Voltage Rails
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF
+APU_CORE_NB 1.0V switched power rail ON OFF OFF
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF
+0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF
+1.05VS 1.05V switched power rail for NB VDDC & VGA ON OFF OFF
+1.1VS 1.1VS switched power rail ON OFF OFF
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF
+3VS 3.3V switched power rail ON OFF OFF
C
+5VALW 5V always on power rail ON ON ON* C
+5VS 5V switched power rail ON OFF OFF
+RTCVCC RTC power ON ON ON
+1.1VALW 1.1V always on power rail ON ON ON*
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B B
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
Board ID Table for AD channel
Vcc 3.3V +/- 5% BOARD ID Table
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.2
A 2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.3 A
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.4
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 0.5
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6
Title
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7
Power Rails
http://hobi-elektronika.net Size Document Number
LA-7161P
Rev
Date: Wednesday, January 05, 2011 Sheet 4 of 43
5 4 3 2 1
5 4 3 2 1
+3VS
1K
D 1K D
Ontario
P3 APU_SIC
MMBT3904
SMBUS Address [TBD]
P4 APU_SID
MMBT3904
Zacate
+3VS
2.2K
2.2K
AD22 SMB_FCH_CK0 202 JDIMMA SMBUS Address [TBD]
AE22 SMB_FCH_DA0 200
C GND C
10K
10K 202 JDIMMB SMBUS Address [TBD]
200
F5 SMB_FCH_CK1
F4 SMB_FCH_DA1
UT7
Hudson GND 8
(NB_Thermal)
SMBUS Address [TBD]
10K 7
10K
D25 SCL2
F23 SDA2
+3VALW
10K
10K
B26 FCH_SIC
0R @
E26 FCH_SID
0R @
B B
+5VALW
4.7K
4.7K
0R @ WWAN_SMB_CK_R 30 JWLAN1 SMBUS Address [TBD]
100R PJBATT 0R @
77 EC_SMB_CK1 7 SMBUS Address [TBD] WWAN_SMB_DA_R 32
(BattERy conn)
78 EC_SMB_DA1
100R 6
0R @ WWAN_SMB_CK_R 30
+3VS JWWAN1 SMBUS Address [TBD]
2.2K 0R @
KB 926 WWAN_SMB_DA_R 32
2.2K
79 EC_SMB_CK2
0R @ LAN_SMB_CK_R 30 UL10 (LAN) SMBUS Address [TBD]
80 EC_SMB_DA2
0R @ LAN_SMB_DA_R 32
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
SMBus Topology
http://hobi-elektronika.net
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7161P
Date: Wednesday, January 05, 2011 Sheet 5 of 43
5 4 3 2 1
A
Board ID Table for AD channel
Vcc 3.3V +/- 5% BOARD ID Table USB PORT# DESTINATION
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision 0 USB Port 0 (Sub-board)
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.2 1 USB Port 1 (Sub-board)
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.3
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.4 2 USB Port 2
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 0.5
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 3 None
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 4 MiniCard- WLAN
SMBUS Control Table USB 5 MiniCard- WWAN
EXPRESS 6 None
SOURCE MIINI1 BATT MINI2 CARD SODIMM CLKOUT DESTINATION
PCI0 None 7 None
EC_SMB_CK1
EC_SMB_DA1
KB926 X V X X X
8 Card Reader
EC_SMB_CK2 KB926 X X X X X PCI1 PCICLK1
EC_SMB_DA2
9 Camera
PCH_SMBCLK PCI2 PCICLK2
PCH_SMBDATA PCH
V X V V X 10 None
PCI3 PCICLK3
MEM_SMBCLK
MEM_SMBDATA PCH
X X X X V PCI4 PCICLK4
11 None
12 None
13 None
1 1
APU
DIFFERENTIAL DESTINATION SATA DESTINATION PCI EXPRESS DESTINATION
CLKOUT_PCIE0 10/100 LAN SATA0 HDD1 Port0 None
CLKOUT_PCIE1 MINI CARD- WLAN SATA1 None Port1 WWAN
CLKOUT_PCIE2 MINI CARD- WWAN SATA2 None Port2 10/100
CLK CLKOUT_PCIE3 None SATA3 None Port3 WLAN
CLKOUT_PCIE4 None SATA4 None FCH
CLKOUT_PCIE5 None : etoN lobmyS SATA5 None PCI EXPRESS DESTINATION
CLKOUT_PCIE6 None dnuorG latigiD snaem : Port0 None
CLKOUT_PCIE7 None Port1 None
dnuorG golanA snaem :
CLKOUT_PCIE8 None Port2 None
Port3 None
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/31 Deciphered Date 2011/07/31 Title
Notes List
http://hobi-elektronika.net THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
Custom
LA-7161P
Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 6 of 43
A
5 4 3 2 1
UU1B
+1.8VS
CU1 1 2 0.1U_0402_16V7K HDMI_TXD2P_C A8 H3 RU3 1 2 150_0402_1%
DISPLAYPORT 1
<18> HDMI_TXD2P CU3 HDMI_TXD2N_C TDP1_TXP0 DP_ZVSS
1 2 0.1U_0402_16V7K B8
DP MISC
RU1 APU_LDT_STP# <18> HDMI_TXD2N TDP1_TXN0
1 2 1K_0402_5% G2 ENBKL <20>
CU4 HDMI_TXD1P_C DP_BLON
1 2 0.1U_0402_16V7K B9 H2 ENVDD <20>
<18> HDMI_TXD1P TDP1_TXP1 DP_DIGON
RU4 1 2 300_0402_5% DBREQ# <18> HDMI_TXD1N
CU5 1 2 0.1U_0402_16V7K HDMI_TXD1N_C A9 TDP1_TXN1 DP_VARY_BL H1 NB_LCD_PWM <20>
RU5 1 2 1K_0402_5% APU_SVC CU6 1 2 0.1U_0402_16V7K HDMI_TXD0P_C D10
<18> HDMI_TXD0P CU7 HDMI_TXD0N_C C10 TDP1_TXP2
<18> HDMI_TXD0N
1 2 0.1U_0402_16V7K TDP1_TXN2 TDP1_AUXP B2 HDMICLK_UMA <18>
RU2 1 2 1K_0402_5% APU_SVD C2 HDMIDAT_UMA <18>
CU2 HDMI_CLKP_C TDP1_AUXN
1 2 0.1U_0402_16V7K A10
<18> HDMI_CLKP TDP1_TXP3
RU6 1 2 300_0402_5% LDT_RST# CU8 1 2 0.1U_0402_16V7K HDMI_CLKN_C B10 C1 HDMI_HPD <18>
<18> HDMI_CLKN TDP1_TXN3 TDP1_HPD
RU7 1 2 300_0402_5% APU_PWRGD <20> LVDS_A2+
B5 LTDP0_TXP0 LTDP0_AUXP A3 LDDC_CLK_MCH <20>
A5 B3
DISPLAYPORT 0
<20> LVDS_A2- LTDP0_TXN0 LTDP0_AUXN LDDC_DATA_MCH <20>
RU8 1 2 510_0402_1% TEST_25_L
D D6 D3 LTDP0_HPD RU9 2 @ 1 100K_0402_5% D
RU10 1 TEST_36 <20> LVDS_A1+ LTDP0_TXP1 LTDP0_HPD
2 1K_0402_5% C6
<20> LVDS_A1- LTDP0_TXN1
DAC_RED C12 VGA_CRT_R <19>
RU35 2 1 1K_0402_5% TEST_35 A6 D13 RU11 1 2 150_0402_1%
<20> LVDS_A0+ LTDP0_TXP2 DAC_REDB
<20> LVDS_A0-
B6 LTDP0_TXN2 DAC_GREEN A12 VGA_CRT_G <19>
Enable HDMI output B12 RU12 1 2 150_0402_1%
DAC_GREENB
D8 A13
VGA DAC
<20> LVDS_ACLK+ LTDP0_TXP3 DAC_BLUE VGA_CRT_B <19>
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