Service Manuals, User Guides, Schematic Diagrams or docs for : Dell Dell Schemetic 1720 fm5
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Corsica\Gilligan - DISCRETE
M08 M/B PCB
A VER : X02 A
POWER
POWER CLOCK
SYSTEM Merom CK505M+LP
RESET CIRCUIT PG 38 (478 Micro-FCPGA) REGULATOR PG 43 CPU VR PG 45
+1.5V_RUN/+1.05V_VCCP
PG 3,4
BATT REGULATOR PG 17
PG 40 PG 42 DC/DC PG 44
AC/BATT CHARGER
(Symbol Rev.09) +1.25V/+1.8V_SUS/+0.9V_DDR_VTT +3.3V_ALW/+5V_ALW/+15V_ALW
CONNECTOR
RUN POWER SW PG 39
PG 41 +3.3V_SUS/+5V_SUS/+3.3V_M
+5V/+3.3V/+1.8V/+1.25_RUN 667/800 MHz FSB
LVDS
VGA CONN. Panel Connector
Crestline PCI EXPRESS GFX TVOUT S-Video
PCIEx16
B
DDR2-SODIMM1 533/667 MHZ DDR II PG 19 B
1299 uFCBGA
PG 15,16
VGA CRT CONN.
PG 5,6,7,8,9,10 PG 18
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PG 19
533/667 MHZ DDR II
DDR2-SODIMM2
(Symbol Rev.09)
PG 15,16
USB2.0 (P5) Camera
PG 33
IDE LAN
DMI interface
CD-ROM BCM4401 (B0)
PG 23 +3.3V_LAN RJ45/Magnetics
33MHz PCI
PG 35
PG 36
SATA - HDD SATA0 ICH8-M (Symbol Rev.09)
33MHz PCI
PG 23
PCIEx1
676 BGA
USB2.0 (P6) CARDBUS/1394
SATA - HDD SATA1
PG 11,12,13,14 PCIEx1 R5C833
C PG 23 C
IHDA USB2.0 (P9) PG 20,21,22
PCIEx2
(Symbol Rev.09) USB2.0 (P7) EXPRESS-CARD
AUDIO/AMP MDC CONN
R5538
PG 32 PG 26
SPI LPC
MINI-CARD x1
PG 26
WWAN
D-Micro Audio Tip PG 25
Jacks Ring SIO SIO MINI-CARD x2
PG 33 PG 33 MEC5025 ECE5011
WLAN
128KB Flash BC Expander
BC TMKBC USB 2.0 Hub(4) PG 24
Dash BD USB2.0 (P0,P2) (EXT SIDE)
TP/KB External USB
PS/2 128 Pins VTQFP 128 Pins VTQFP USB2.0 (P3,P8) (EXT BACK)
& PG 27
PG 28 PG 29
D
KB Media/Dash BD D
Conn
SPI
QUANTA Digitally signed by fdsf
Touchpad FAN & THERMAL DN: cn=fdsf, o=fsdfsd,
FLASH CIR COMPUTER
PG 31
PG 31
EMC4001 Title
Schematic Block Diagram1
ou=ffsdf,
PG 30 PG 34
Media BD Size Document Number email=fdfsd@fsdff, c=US
Rev
Date:1 2010.03.29 17:57:21
C G M-08 0.1
31FM5MB0011 31GM2MB0004
41FM5SS0017 41GM2SS0000 Date: Tuesday, March 06, 2007 Sheet of 51
1 2 3 4 5 6 7
+07'00'
8
1 2 3 4 5 6 7 8
INDEX Power & Ground
Pg# Description DNI LIST Label Pg# Description Control Signal
1 Schematic Block Diagram DC_IN+ AC ADAPTER (19V)
2 Front Page PBATT+ MAIN BATTERY + (10~17V)
3-4 Merom PBATT+ SECOND BATTERY + (10~17V)
A A
5-10 Crestline PWR_SRC MAIN POWER (10~19V)
11-14 ICH8M RTC_PWR3_3V RTC & +3.3V_RTC_LDO(3.3V)
15-16 DDRII SO-DIMM(200P) +VCC_CORE CPU CORE POWER (1.5V) RUNPWROK
17 Clock Generator +15V_ALW LARGE POWER (15V) SUS_ON
18-21 VGA +3.3V_RUN SLP_S3# CTRLD POWER RUN_ON
22 LCD Conn. & SSP +3.3V_SUS SLP_S5# CTRLD POWER SUS_ENABLE
23 CRT Conn +3.3V_ALW 8051 POWER (3.3V) ALWON/THERM_STP#
24 SATA & IDE Conn +5V_RUN SLP_S3# CTRLD POWER RUN_ON
25 PCCARD/Conn & 1394 +5V_SUS SLP_S5# CTRLD POWER SUS_ON
26 Express Card & Smart Card +5V_HDD HDD POWER (5V) +5V_RUN
B B
27 Mini Card +5V_MOD MODULE POWER (5V) HDDC_EN
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28 MDC Conn. +5V_ALW LCD/CHARGE POWER (5V)
29 SIO (MEC5004) +VDDA AUDIO ANALOG POWER (5V) AUDIO_AVDD_ON
30 SIO (MEC5018) +1.5V_RUN CALISTOGA/ICH7 POWER RUN_ON
31 SERIAL PORT & USB +1.05V_VCCP CPU/CALISTOGA/ICH7 POWER RUN_ON
32 Flash ROM +1_8V_SUS SODIMM POWER SUSPWROK_5V
33 TP,BT & FIR +1.8V_RUN SDVO POWER RUN_ON
34 Switch,Keyboard & LED +0.9V_DDR_VTT SODIMM POWER RUN_ON
35 FAN & Thermal +3.3V_LAN LAN POWER AUX_EN
C 36-37 Audio CODEC(STAC9200)/Phone Jack C
38-39 LOM (BCM5752)/Switch
40-41 Docking Conn/Q-Switch GND ALL PAGES DIGITAL GROUND
42 System Reset Circuit AGND_ISL6260 CPU GND
43-44 Battery Selector & Charger AGND_TPS51120 DC/DC POWER GND
45 DDR2_1.8VSUS, 0.9V AGND1 VTT POWER GND
46 1.5VSUS,1.05V(VTT) AGND2 VTT POWER GND
47 1.25V,1.05VM 8731AGND CHARGER GND
48 CPU_MAX8786(3phase)
49 D/D Power
D 50 RUN Power Switch D
51 VGA DC/DC QUANTA
52 DCIN/Batt Conn.
Title
COMPUTER
53 Index, DNI, Power & Ground
PAD& SCREW
Size Document Number Rev
54 M-08 0.1
EMI CAP
Date: Monday, March 05, 2007 Sheet 2 of 51
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
H_A#[3..16] U15A H_D#[0..63] U15B H_D#[0..63]
<5> H_A#[3..16] <5> H_D#[0..63] H_D#[0..63] <5>
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# <5> D[0]# D[32]#
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# <5> D[1]# D[33]#
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# <5> D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 A[7]# DEFER# H5 H_DEFER# <5> F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# <5> D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# <5> D[6]# D[38]#
H_A#10 N3 H_D#7 E23 U23 H_D#39
A A[10]# H_BR0# <5> D[7]# D[39]# A
ADDR GROUP 0
ADDR GROUP 0
DATA GRP 0
DATA GRP 2
H_A#11 P5 F1 H_D#8 K24 Y25 H_D#40
H_A#12 A[11]# BR0# R346 56 H_D#9 D[8]# D[40]# H_D#41
P2 A[12]# G24 D[9]# D[41]# W22
H_A#13 L2 D20 H_IERR# 1 2 H_D#10 J24 Y23 H_D#42
CONTROL
A[13]# IERR# +1.05V_VCCP D[10]# D[42]#
H_A#14 P4 B3 H_D#11 J23 W24 H_D#43
A[14]# INIT# H_INIT# <11> D[11]# D[43]#
H_A#15 P1 H_D#12 H22 W25 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# <5> F26 D[13]# D[45]# AA23
M1 H_D#14 K22 AA24 H_D#46
<5> H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# D[14]# D[46]#
C1 H_RESET# H_D#15 H23 AB25 H_D#47
<5> H_REQ#[0..4] RESET# H_RESET# <5> D[15]# D[47]#
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 <5> <5> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <5>
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 <5> <5> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <5>
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 <5> <5> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <5>
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# <5> H_D#[0..63] H_D#[0..63]
H_REQ#4 L1
H_A#[17..35] REQ[4]# <5> H_D#[0..63] H_D#[0..63] <5>
G6 H_D#16 N22 AE24 H_D#48
<5> H_A#[17..35] HIT# H_HIT# <5> D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# <5> D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# ITP_BPM#0 H_D#19 D[18]# D[50]# H_D#51
R3 A[19]# BPM[0]# AD4 R23 D[19]# D[51]# AB22
H_A#20 W6 AD3 ITP_BPM#1 Layout Note: H_D#20 L23 AB21 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
ADDR GROUP 1
H_A#21 U4 AD1 ITP_BPM#2 H_D#21 M24 AC26 H_D#53
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# ITP_BPM#3
Place voltage H_D#22 D[21]# D[53]# H_D#54
Y5 A[22]# BPM[3]# AC4 L22 D[22]# D[54]# AD20
divider within
DATA GRP 1
DATA GRP 3
H_A#23 U1 AC2 ITP_BPM#4 H_D#23 M23 AE22 H_D#55
H_A#24 A[23]# PRDY# ITP_BPM#5 0.5" of GTLREF H_D#24 D[23]# D[55]# H_D#56
R4 A[24]# PREQ# AC1 P25 D[24]# D[56]# AF23
H_A#25 T5 AC5 ITP_TCK pin H_D#25 P23 AC25 H_D#57
H_A#26 A[25]# TCK ITP_TDI H_D#26 D[25]# D[57]# H_D#58
T3 A[26]# TDI AA6 P22 D[26]# D[58]# AE21
H_A#27 W2 AB3 ITP_TDO H_D#27 T24 AD21 H_D#59
H_A#28 A[27]# TDO ITP_TMS +1.05V_VCCP H_D#28 D[27]# D[59]# H_D#60
W5 A[28]# TMS AB5 R24 D[28]# D[60]# AC22
H_A#29 Y4 AB6 ITP_TRST# H_D#29 L25 AD23 H_D#61
H_A#30 A[29]# TRST# ITP_DBRESET# H_D#30 D[29]# D[61]# H_D#62
U2 A[30]# DBR# C20 ITP_DBRESET# <13,29> T25 D[30]# D[62]# AF22
2
H_A#31 V4 H_D#31 N25 AC23 H_D#63
H_A#32 A[31]# R344 56 R402 D[31]# D[63]#
B W3 A[32]# <5> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <5> B
H_A#33 AA4 THERMAL 2 1 +1.05V_VCCP 1K/F M26 AF24
A[33]# <5> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <5>
H_A#34 AB2 R340 0_NC N24 AC20
A[34]# <5> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <5>
H_A#35 AA3 D21 CPU_PROCHOT# 1 2 EC_CPU_PROCHOT# <28>
1
A[35]# PROCHOT# H_THERMDA V_CPU_GTLREF AD26 COMP0
<5> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 H_THERMDA <34> GTLREF COMP[0] R26 Note:
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B25 H_THERMDC CPU_TEST1 C23 MISC COMP[1] U26 COMP1 H_DPRTSTP need to daisy chain
THERMDC H_THERMDC <34> TEST1
2
A6 CPU_TEST2 D25 AA1 COMP2
<11> H_A20M# A20M# TEST2 COMP[2] from ICH8 to IMVP6 to CPU.
A5 C7 H_THERMTRIP# CPU_TEST3 C24 Y1 COMP3
<11> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <34> TEST3 COMP[3]
ICH
ICH
C4 R330 56 R404 CPU_TEST4 AF26
<11> H_IGNNE# IGNNE# TEST4
1 2 +1.05V_VCCP 2K/F CPU_TEST5 AF1 E5
TEST5 DPRSTP# H_DPRSTP# <6,11,45>
D5 H CLK CPU_TEST6 A26 B5
<11> H_STPCLK# H_DPSLP# <11>
1
STPCLK# TEST6 DPSLP#
<11> H_INTR C6 LINT0 DPWR# D24 H_DPWR# <5>
<11> H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK <17> <6,17> CPU_MCH_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD <11>
<11> H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# <17> <6,17> CPU_MCH_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# <5>
<6,17> CPU_MCH_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# <45>
M4 RSVD[01]
N5 Merom Ball-out Rev 1a
RSVD[02] C163
T2 RSVD[03]
V3 H_THERMDA 1 2 H_THERMDC
RSVD[04]
RESERVED
B2 RSVD[05]
C3 2200P/50V_NC R331 1K/F_NC PAD T17 CPU_TEST3
RSVD[06] CPU_TEST1 CPU_TEST5
D2 RSVD[07] 1 2 PAD T97
D22 R106 1K/F_NC
RSVD[08] CPU_TEST2
D3 RSVD[09] 1 2 For the purpose of testability, route these signals
F6 C520 0.1U/10V_NC through a ground referenced Z0 = 55ohm trace that
RSVD[10] CPU_TEST4
2 1
R332 0_NC ends in a via that is near a GND via and is
1 2 CPU_TEST6 accessible through an oscilloscope connection.
Merom Ball-out Rev 1a
C C
For Support XDP: Place C close to the
1. ITP_BPM#5 need PU 51ohms to +1.05V_VCCP. CPU_TEST4 pin. Make sure
FSB BCLK BSEL2 BSEL1 BSEL0 COMP0
Populate ITP700Flex for bringup 2. Change R4 & R361 to 51 ohms. CPU_TEST4 routing is COMP1
3. Changed R6 & R346 to 51 ohms. reference to GND and away COMP2
533 133 0 0 1
+1.05V_VCCP 4. Depopulate R2 and changed R8 to 1K/F. from other noisy signal. COMP3
667 166 0 1 1
Layout Note:
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