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5 4 3 2 1
D D
DJ1 Montevina UMA Schematics Document
uFCPGA Mobile Penryn
C
Intel GM45+ICH9M C
2010-02-10
REV : A00
B B
DY : Nopop Component
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number
Cover Page Rev
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 1 of 88
5 4 3 2 1
5 4 3 2 1
DJ1 Montevina UMA Block Diagram INPUTS
CPU DC/DC
TPS51620
OUTPUTS
47
Project code : 91.4EK01.001 +PWR_SRC +VCC_CORE
Intel Mobile CPU PCB P/N : 48.4EK06.0SA SYSTEM DC/DC
TPS51218 49
D
Clock Generator Penryn Revision : 09275-SA INPUTS OUTPUTS D
SLG8SP513VTR +PWR_SRC +1.05V_VCCP
7
Socket P 8,9
SYSTEM DC/DC
TPS51125 46
INPUTS OUTPUTS
FSB +5V_ALW2
800/1066MHz +PWR_SRC +3.3V_RTC_LDO
+5V_ALW
+3.3V_ALW
+15V_ALW
RGB CRT
Intel DDRIII 800/1066 Channel A DDRIII Slot 0 SYSTEM DC/DC
CRT 55 18
800/1066 TPS51116
GM45 50
INPUTS OUTPUTS
AGTL + CPU I/F
DDRIII 800/1066 Channel B DDRIII Slot 1 +1.5V_SUS
DDR Memory I/F +PWR_SRC +0.75V_DDR_VTT
19
800/1066 +V_DDR_REF
LCD 54
LVDS(Dual Channel) External Graphics
10,11,12,13,14,15 MAXIM CHARGER
C BQ24745 C
INPUTS OUTPUTS
DMIx4 C-LINK +DC_IN +PWR_SRC
+PBATT
10/100 NIC
Atheros
RJ45 26
AR8132 CONN SYSTEM DC/DC
Switches 42
PCIE x 2 26
SATA INPUTS OUTPUTS
Intel
I/O Board
Connector
Mini-Card +1.5V_SUS +1.5V_RUN
802.11a/b/g +5V_ALW +5V_RUN
ICH9-M +3.3V_ALW +3.3V_RUN
PCIE USB 2.0 x 1
CardReader PCB LAYER
Left Side:
SD/MMC/MS/ USB 2.0/1.1 ports (12) USB x 1
Realtek USB2.0 75 L1: Top
MS Pro/xD PCI Express ports (8)
70 RTS5138
High Definition Audio L2: VCC
32
SATA ports (4)
USB 2.0 x 1
L3: Signal
LPC I/F USB 2.0 CAMERA 54
B B
ACPI 1.1 L4: Signal
MIC IN PCI/PCI BRIDGE
60
Azalia AZALIA
USB 2.0 x 1
L5: GND
Bluetooth 72
Internal Analog MIC CODEC L6: Bottom
60
IDT 20,21,22,23
LPC Bus
92HD79B1 USB 2.0 x 2
30
Right Side: 63
HP1 USB x 2
60
KBC
SPI
NUVOTON
SATA
SATA
NPCE781BA0DX 37
A DJ1 A
2CH SPEAKER
Flash ROM Touch Int. Thermal
HDD ODD
2MB 62 PAD KB EMC2102 Wistron Corporation
59 59 39 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
67 67 25 Taipei Hsien 221, Taiwan, R.O.C.
60
Title
Block Diagram
Size Document Number Rev
Fan 58 A3 A00
DJ1 Montevina UMA
Date: W ednesday, February 24, 2010 Sheet 2 of 88
5 4 3 2 1
5 4 3 2 1
DJ1 Montevina UMA Power Block Diagram
D D
+PWR_SRC
Adapter
TPS51125 TPS51620 TPS51218 TPS51116
Charger
BQ24745 +VCC_CORE +1.05V_VCCP
47 49 +V_DDR_REF +0.75V_DDR_VTT
Battery +VCHGR +1.5V_SUS 50
50 50
C C
FSD8880
+15V_ALW +3.3V_RTC_LDO +5V_ALW2 +5V_ALW 46 +3.3V_ALW 46 +1.5V_RUN 42
46 46 46
G547F2P81U SI4800 G547F2P81U FDS8880 PA102
+5V_USB1 +5V_RUN +5V_USB2 +3.3V_RUN +3.3V_LAN
42
63 42 63
B B
G9091
G5285T11U RTS5159 RT9198 RTL8103T
+3.3V_CRT_LDO
15 +LCDVDD +3.3V_RUN_CARD +1.8V_NB_S0 +1.2V_LOM
54
32 15
A DJ1 A
Power Shape
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Regulator LDO Switch Title
Size
Power Block Diagram
Document Number Rev
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 3 of 88
5 4 3 2 1
A B C D E
ICH SMBus Block Diagram KBC SMBus Block Diagram
+5V_RUN
+3.3V_ALW +3.3V_RUN
+3.3V_RUN
SRN4K7J-8-GP SRN4K7J-8-GP SRN10KJ-5-GP
ICH
SMBCLK SMB_CLK ICH_SMBCLK
DIMM 1 PSDAT1 TPDATA TPDATA TPDATA
TouchPad Conn.
1 SCL 1
SMBDATA SMB_DATA ICH_SMBDATA PSCLK1 TPCLK TPCLK TPCLK
SDA
+KBC_PWR
SMBus Address:A0
2N7002SPT
ICH_SMBCLK
DIMM 2
SCL
ICH_SMBDATA SRN4K7J-8-GP
SDA
SMBus Address:A4
SCL1 BAT_SCL
SRN100J-3-GP
PBAT_SMBCLK1
Battery Conn.
CLK_SMB
SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB SMBus address:16
Clock
ICH_SMBCLK
Generator
ICH_SMBDATA
SCLK
SDATA
BQ24745
KBC SCL
SDA SMBus address:12
SMBus address:D2
NPCE781BA0DX
Minicard +3.3V_RUN
2
ICH_SMBCLK
WLAN
SMB_CLK
2
+KBC_PWR
ICH_SMBDATA SMB_DATA +3.3V_RUN
SRN4K7J-8-GP
SRN4K7J-8-GP
Thermal
THERM_SCL SCL
SMBus address:7A
THERM_SDA SDA
GPIO61/SCL2 KBC_SCL1
2N7002DW-1-GP
GPIO62/SDA2 KBC_SDA1
+3.3V_RUN
SRN2K2J-1-GP
3 3
DDC1CLK LDDC_CLK
DDC1DATA LDDC_DATA LCD CONN
+3.3V_RUN +5V_CRT_RUN
+3.3V_RUN
SRN2K2J-1-GP SRN2K2J-1-GP
VGA
DDC2CLK GMCH_DDCCLK DDC_CLK_CON
DDC2DATA GMCH_DDCDATA DDC_DATA_CON CRT CONN
2N7002DW-1-GP
4 4
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
SMBUS Block Diagram
Size Document Number Rev
A2 DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 4 of 88
A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram
1 1
SPKR_PORT_D_L-/L+ 2CH SPEAKERS
SPKR_PORT_D_R-/R+
DP1 H_THERMDA CPU
THRMDA
HP1_PORT_B_L
HP
SC470P50V3JN-2GP
HP1_PORT_B_R
2
DN1 H_THERMDC OUT 2
THRMDC
Codec
Thermal
92HD79B1
EMC2102
DP2 EMC2102_DP2
HP0_PORT_A_L
MIC
PMBS3904-1-GP
SC470P50V3JN-2GP HP0_PORT_A_R
DN2 EMC2102_DN2 VREFOUT_A_OR_F
IN
Put between CPU and NB
3 3
DP3 EMC2102_DP3
PMBS3904-1-GP
SC470P50V3JN-2GP
DN3 EMC2102_DN3
HW T8 sensor PORTC_L
PORTC_R
Analog
VREFOUT_C MIC
4 4
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 5 of 88
A B C D E
A B C D E
ICH9M Functional Strap Definitions ICH9 Integrated pull-up Cantiga chipset and ICH9M I/O controller
ICH9 EDS 642879 Rev.2.3 and pull-down Resistors Hub strapping configuration
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.2.3 Montevina Platform Design guide 355648 Rev.2.3
HDA_SDOUT XOR Chain Entrance / Allows entrance to XOR Chain testing when TP3 SIGNAL Resistor Type/Value Pin Name Strap Description Configuration
PCI Express* pulled low at rising edge of PWROK. When TP3
Port Config 1 bit 1 not pulled low at rising edge of PWROK, sets CL_CLK[1:0] PULL-UP 20K CFG2:0 FSB Frequency 000 = FSB1066
1 (Port 1-4), bit 1 of RPC.PC (Chipset Config Registers: Offset 010 = FSB800 1
CL_DATA[1:0] PULL-UP 20K 011 = FSB667
Rising Edge of PWROK 224h).This signal has a weak internal pull-down.
CL_RST0# PULL-UP 10K Others = Reserved
HDA_SYNC PCI Express Port Config This signal has a weak internal pull-down.
1 bit 0 (Port 1-4), Sets bit 0 of RPC.PC (Chipset Config Registers: DPRSLPVR/GPIO16 PULL-DOWN 20K
Rising Edge of PWROK. Offset 224h) CFG5 DMI x2 Select 0 = DMI x2
HDA_BIT_CLK PULL-DOWN 20K 1 = DMI x4 (Default)
GNT2#/ PCI Express Port This signal has a weak internal pull-up.
GPIO53 Config 2 bit 2 Sets bit 2 of RPC.PC2 (Chipset Config HDA_DOCK_EN#/GPIO33 PULL-UP 20K
(Port 5-6), Rising Edge Registers:Offset 0224h) when sampled low. CFG6 ITPM Host Interface 0 = The iTPM Host Interface is enabled (Note 2)
HDA_RST# PULL-DOWN 20K 1 = The iTPM Host Interface is disabled (default)
of PWROK
GPIO20 Reserved, Rising Edge This signal has a weak internal pull-down. HDA_SDIN[3:0] PULL-DOWN 20K 0 = Intel Management Engine Crypto Transport
of PWROK NOTE: This signal should not be pulled high CFG7 Intel Management Layer Security (TLS) cipher suite with no
HDA_SDOUT PULL-DOWN 20K engine crypto strap confidentiality
GNT1#/ ESI Strap (Server Only), Tying this strap low configures DMI for ESIcompatible
GPIO51 Rising Edge of PWROK. operation. This signal has a weak internal HDA_SYNC PULL-DOWN 20K 1 = Intel Management Engine Crypto TLS cipher
pull-up. suite with confidentiality (default)
GNT0#, GNT[3:1]#/ PULL-UP 20K
NOTE: ESI compatible mode is for server platforms GPIO[55,53,51] 0 = Reverse Lanes, 15->0, 14->1 etc.
only. This signal should not be pulled low for CFG9 PCIE Graphics Lane 1 = Normal operation (default): Lane Numbered
desktop and mobile. GPIO20 PULL-DOWN 20K in Order
GNT3#/ Top-Block Swap Sampled low: this indicates that the GPIO49 PULL-UP 20K
GPIO55 override. Rising Edge system is strapped to the "top-block swap"
of PWROK. mode (IntelR ICH9 inverts A16 for all LAD[3:0]# / FHW[3:0]# PULL-UP 20K CFG10 PCIE Loopback enable 0 = Enable (Note 3)
1 = Disable (Default)
cycles targeting BIOS space). The status of LAN_RXD[2:0] PULL-UP 20K
this strap is readable via the Top Swap bit
2 (Chipset Config Registers:Offset 3414h: LDRQ0 PULL-UP 20K 2
bit 0). Note that software will not be able CFG12 ALLZ 0 =ALLZ mode enabled (Note 3)
to clear the Top-Swap bit until the system LDRQ1 / GPIO23 PULL-UP 20K
1 = Disable (Default)
is rebooted without GNT3# being pulled down. PME# PULL-UP 20K
0 = XOR mode enabled (Note 3)
Boot BIOS Destination Controllable via Boot BIOS Destination PWRBTN# PULL-UP 20K CFG13 XOR 1 = Disable (Default)
GNT0# Selection 1, bit (Chipset Config Registers:Offset 3410h:bit 11).
Rising Edge of PWROK. This strap is used in conjunction with Boot BIOS SATALED# PULL-UP 15K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
Destination Selection 0 strap. SPI_CS1# / 1 = Dynamic ODT Enabled (Default)
GPIO58 (Desktop Only) / PULL-UP 20K
Bit11 Bit 10 Boot BIOS CLGPIO6 (Digital Office Only)
(GNT0#) (SPI_CS1#) Destination CFG19 DMI Lane Reversal 0 = Normal operation (Default): Lane Numbered in
Order
0 1 SPI SPI_MOSI PULL-DOWN 20K 1 = Reverse Lanes
1 0 PCI DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)
1 1 LPC DMI x2 mode [MCH->ICH]: (3->0, 2->1)
0 0 Reserved SPI_MISO PULL-UP 20K
Digital Display Port 0 = Only digital DisplayPort (SDVO/DP/HDMI) or
CFG20 (SDVO/DP/HDMI) PCIe is operational (default)
SPI_CS1#/ Boot BIOS Destination Controllable via Boot BIOS Destination SPKR PULL-DOWN 20K Concurrent with PCIe 1 = Digital DisplayPort (SDVO/DP/HDMI) and
GPIO58 Selection 0, bit (Chipset Config Registers:Offset 3410h:bit 10).
Rising Edge of CLPWROK. This strap is used in conjunction with Boot BIOS PCIe are operating simultaneously via the PEG port
Destination Selection 1 strap. TACH[3:0] PULL-UP 20K
SDVO
_CTRLDATA SDVO Present 0 = No SDVO/HDMI/DP interface disabled (default)
Bit11 Bit 10 Boot BIOS TP3 PULL-UP 20K (Note4) 1 = SDVO/HDMI/DP interface enabled
(GNT0#) (SPI_CS1#) Destination
3 0 1 SPI USB[11:0][P,N] PULL-DOWN 15K 0 = LFP Disabled (Default) 3
1 0 PCI L_DDC_DATA Loca◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo