Service Manuals, User Guides, Schematic Diagrams or docs for : Dell Dell_Inspiron_Mini_10_1012-COMPAL_LA-5732P_NIM10_UMA-REV_0.2
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A B C D E
MODEL NAME : NIM10
PCB NO : LA-5732P (DA60000EI00)
1
BOM P/N : 43178431L01 1
Compal Confidential
2
SAMOS Schematics Document 2
Intel Pineview-M Processor with TigerPoint
2009-8-21
REV: 0.2
3 3
@ : Nopop Component
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/03/25 Deciphered Date 2009/06/22 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5732
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401784
Date: Wednesday, September 16, 2009 Sheet 1 of 33
A B C D E
A B C D E
Compal Confidential
Thermal Sensor
Model Name : NIM10 W83L771AWG
Project Code: page 5
Project Name : LA-5732P
1 1
Clock Generator
CK505 page 08
LCD Conn. LVDS
page 09 Pineview-M Memory BUS(DDRII)
Processor DDRII-DIMM X1
P 07
1.8V/667MHz
Daughter board CRT Conn RGB 22x22mm
LS-5731P page 21
page 4,5,6
USB Port X1 Port 1 DMI SIM card
X2 mode
page 21
USB Port X1 Port 2 USB
2
USB 2
page 21 Port 4 WWAN
Tiger Pointer page 14
Card Reader Chipset SATA
Port 7
RTS5159
SD/MMC/MS PCI-Express 17x17mm
page 21 HDA Port 0 USB Port X1
page 10,11,12,13
2.5" HDD (R) page 21
page 17
Through BT cable
Port 5
LPC BUS Audio Codec BlueTooth
AMP & Speaker page 14
ALC272-VB-GR
page 15
page 16
MINI Card MINI Card MINI Card 10/100 Ethernet Through LVDS cable
3 WLAN WWAN Broadcom MCP RTL8103EL HeadPhone & 3
page 14 page 14 page 14 page 18 MIC Jack Port 3
PCIE-Port 2 PCIE-Port 3 PCIE-Port 4 PCIE-Port 1 page 16 CMOS CAM
page 09
USB Port 6 USB Port 4 ENE KBC SPI
RJ45
page 18
KB926
page 19
Power ON/OFF DC/DC Interface
page 24 page 22
Through power buttom cable Through LED cable
DC IN 3VALW/5VALW Int.KBD Touch Pad SPI ROM
page 24 page 26
page 19 page 20 page 20
PWR buttom board LED/B
BATT CONN/OTP 1.5VS/0.9VS/ LS-5732P LS-5733P
page 30
0.89VS
page 28
4
CHARGER 4
page 25
1.8V/VCCP
page 27
Security Classification Compal Secret Data Compal Electronics, Inc.
CPU CORE Issued Date 2009/03/25 Deciphered Date 2009/06/22 Title
page 29 SCHEMATIC, MB A5732
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401784
Date: Wednesday, September 16, 2009 Sheet 2 of 33
A B C D E
A B C D E
ZZZ
PCB
DA60000EI00
1 1
Voltage Rails
External PCI Devices
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
DEVICE IDSEL # REQ/GNT # PIRQ
B+ AC or battery power rail for power circuit. N/A N/A N/A
No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+0.89VS CORE VOLTAGE FOR CPU VGA ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
2 2
+VS VS always on power rail ON ON ON*
+RTCBATT RTC power ON ON ON
EC SM Bus1 address EC SM Bus2 address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Device Address Device Address
Smart Battery 0001 011X b W83L771AWG 1001_100X b
EEPROM(24C16/02) 1010 000X b EMC1402 100_1100X b
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
3 BOARD ID Table(Page 19) Tiger Point SM Bus address
3
VCC 3.3V +/-5%
Device Address
ID BRD ID Ra Rb Vab (Min) Vab (Type) Vab (Max)
Clock Generator 1101 001Xb
0 R01 (SSI) NC 0 0V 0V 0.155V (SLG8SP556VTR)
1 R02 (ST) 100K +/- 5% 8.2K +/- 5% 0.168V 0.250V 0.362V DDR DIMMA 1010 000Xb
* 2 R10 (X build) 100K +/- 5% 18K +/- 5% 0.375V 0.503V 0.621V
3 Reserved 100K +/- 5% 33K +/- 5% 0.634V 0.819V 0.945V
4 Reserved 100K +/- 5% 56K +/- 5% 0.958V 1.185V 1.359V
5 Reserved 100K +/- 5% 100K +/- 5% 1.372V 1.650V 1.838V
6 Reserved 100K +/- 5% 200K +/- 5% 1.851V 2.200V 2.420V
7 MP 100K +/- 5% NC 2.433V 3.300V 3.300V
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/03/25 Deciphered Date 2009/06/22 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5732
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401784
Date: Wednesday, September 16, 2009 Sheet 3 of 33
A B C D E
5 4 3 2 1
<7> DDR_A_DQS#[0..7]
PINEVIEW_M
PINEVIEW_M <7> DDR_A_D[0..63]
U31A U31B
REV = 1.1
<7> DDR_A_DM[0..7]
REV = 1.1 DDR_A_MA0 DDR_A_DQS0
AH19 DDR_A_MA_0 DDR_A_DQS_0 AD3
DMI_RX0_R <7> DDR_A_DQS[0..7] DDR_A_MA1 DDR_A_DQS#0
F3 DMI_RXP_0 DMI_TXP_0 G2 DMI_TX0 <12> AJ18 DDR_A_MA_1 DDR_A_DQS#_0 AD2
DMI_RX#0_R F2 G1 DMI_TX#0 <12> DDR_A_MA2 AK18 AD4 DDR_A_DM0
DMI_RXN_0 DMI_TXN_0 <7> DDR_A_MA[0..14] DDR_A_MA_2 DDR_A_DM_0
DMI_RX1_R H4 H3 DMI_TX1 <12> DDR_A_MA3 AK16
DMI_RX#1_R DMI_RXP_1 DMI_TXP_1 DDR_A_MA4 DDR_A_MA_3 DDR_A_D0
G3 DMI_RXN_1 DMI_TXN_1 J2 DMI_TX#1 <12> AJ14 DDR_A_MA_4 DDR_A_DQ_0 AC4
DDR_A_MA5 AH14 AC1 DDR_A_D1
DMI
DDR_A_MA6 DDR_A_MA_5 DDR_A_DQ_1 DDR_A_D2
AK14 DDR_A_MA_6 DDR_A_DQ_2 AF4
DDR_A_MA7 AJ12 AG2 DDR_A_D3
DDR_A_MA8 DDR_A_MA_7 DDR_A_DQ_3 DDR_A_D4
AH13 DDR_A_MA_8 DDR_A_DQ_4 AB2
D DDR_A_MA9 DDR_A_D5 D
AK12 DDR_A_MA_9 DDR_A_DQ_5 AB3
<8> CLK_CPU_EXP# N7 L10 DDR_A_MA10 AK20 AE2 DDR_A_D6
EXP_CLKINN EXP_RCOMPO R1172 DDR_A_MA11 DDR_A_MA_10 DDR_A_DQ_6 DDR_A_D7
<8> CLK_CPU_EXP N6 EXP_CLKINP EXP_ICOMPI L9 AH12 DDR_A_MA_11 DDR_A_DQ_7 AE3
L8 R1171 49.9_0402_1% DDR_A_MA12 AJ11
EXP_RBIAS 750_0402_1% DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
R10 EXP_TCLKINN AJ24 DDR_A_MA_13 DDR_A_DQS_1 AB8
R9 N11 DDR_A_MA14 AJ10 AD7 DDR_A_DQS#1
EXP_TCLKINP RSVD_TP T1 DDR_A_MA_14 DDR_A_DQS#_1
N10 P11 AA9 DDR_A_DM1
RSVD RSVD_TP T2 DDR_A_DM_1
N9 RSVD DDR_A_WE# AK22 AB6 DDR_A_D8
<7> DDR_A_WE# DDR_A_WE# DDR_A_DQ_8
DDR_A_CAS# AJ22 AB7 DDR_A_D9
<7> DDR_A_CAS# DDR_A_CAS# DDR_A_DQ_9
DDR_A_RAS# AK21 AE5 DDR_A_D10
<7> DDR_A_RAS# DDR_A_RAS# DDR_A_DQ_10
K2 K3 AG5 DDR_A_D11
RSVD RSVD DDR_A_BS0 DDR_A_DQ_11 DDR_A_D12
J1 RSVD RSVD L2 <7> DDR_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
M4 M2 DDR_A_BS1 AH20 AB5 DDR_A_D13
RSVD RSVD <7> DDR_A_BS1 DDR_A_BS_1 DDR_A_DQ_13
L3 N2 DDR_A_BS2 AK11 AB9 DDR_A_D14
RSVD RSVD <7> DDR_A_BS2 DDR_A_BS_2 DDR_A_DQ_14
AD6 DDR_A_D15
DDR_A_DQ_15
1 OF 6 DDR_A_DQS2
PINEVIEW-M_FCBGA8559 DDR_A_DQS_2 AD8
DDR_CS#0 AH22 AD10 DDR_A_DQS#2
<7> DDR_CS#0 DDR_A_CS#_0 DDR_A_DQS#_2
DDR_CS#1 AK25 AE8 DDR_A_DM2
<7> DDR_CS#1 DDR_A_CS#_1 DDR_A_DM_2
AJ21 DDR_A_CS#_2
AJ25 AG8 DDR_A_D16
DDR_A_CS#_3 DDR_A_DQ_16 DDR_A_D17
DDR_A_DQ_17 AG7
DDR_CKE0 AH10 AF10 DDR_A_D18
<7> DDR_CKE0 DDR_A_CKE_0 DDR_A_DQ_18
DDR_CKE1 AH9 AG11 DDR_A_D19
<7> DDR_CKE1 DDR_A_CKE_1 DDR_A_DQ_19
JP80 AK10 AF7 DDR_A_D20
XDP_PREQ# DDR_A_CKE_2 DDR_A_DQ_20 DDR_A_D21
<5> XDP_PREQ# 1 1 AJ8 DDR_A_CKE_3 DDR_A_DQ_21 AF8
C906 DMI_RX0_R XDP_PRDY# DDR_A_D22
<12> DMI_RX0 1 2 <5> XDP_PRDY# 2 2 DDR_A_DQ_22 AD11
0.1U_0402_10V7K 3 M_ODT0 AK24 AE10 DDR_A_D23
3 <7> M_ODT0 DDR_A_ODT_0 DDR_A_DQ_23
<5> XDP_BPM#3 XDP_BPM#3 4 M_ODT1 AH26
C907 4 <7> M_ODT1 DDR_A_ODT_1
1 2 DMI_RX#0_R <5> XDP_BPM#2 XDP_BPM#2 5 AH24 AK5 DDR_A_DQS3
<12> DMI_RX#0 5 DDR_A_ODT_2 DDR_A_DQS_3
0.1U_0402_10V7K 6 AK27 AK3 DDR_A_DQS#3
C XDP_BPM#1 6 DDR_A_ODT_3 DDR_A_DQS#_3 DDR_A_DM3 C
<5> XDP_BPM#1 7 7 DDR_A_DM_3 AJ3
C908 DMI_RX1_R XDP_BPM#0
<12> DMI_RX1 1 2 <5> XDP_BPM#0 8 8
0.1U_0402_10V7K 9 AH1 DDR_A_D24
R1173 1 9 M_CLK_DDR0 DDR_A_DQ_24 DDR_A_D25
C909 <5,12> H_PWRGD 2 1K_0402_1% 10 10 <7> M_CLK_DDR0 AG15 DDR_A_CK_0 DDR_A_DQ_25 AJ2
<12> DMI_RX#1 1 2 DMI_RX#1_R @ R1174 1 2 1K_0402_1% 11 M_CLK_DDR#0 AF15 AK6 DDR_A_D26
<12> SLPIOVR# 11 <7> M_CLK_DDR#0 DDR_A_CK_0# DDR_A_DQ_26
0.1U_0402_10V7K <8> CPU_ITP CPU_ITP 12 M_CLK_DDR1 AD13 AJ7 DDR_A_D27
12 <7> M_CLK_DDR1 DDR_A_CK_1 DDR_A_DQ_27
<8> CPU_ITP# CPU_ITP# 13 M_CLK_DDR#1 AC13 AF3 DDR_A_D28
13 <7> M_CLK_DDR#1 DDR_A_CK_1# DDR_A_DQ_28
+VCCP 14 AH2 DDR_A_D29
14 DDR_A_DQ_29
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