Service Manuals, User Guides, Schematic Diagrams or docs for : Dell N4010 Wistron Arsenal DJ1 AMD Dis
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5 4 3 2 1
Arsenal Discrete Schematics Document
D D
AMD Danube CPU S1G4
VGA ATI PARKS3-LP
RS880M + SB820M
C C
2010-05-07
REV : X01
DY : Nopop Component
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
Custom
Arsenal DJ1 Discrete X01
Date: Friday, May 07, 2010 Sheet 1 of 89
5 4 3 2 1
5 4 3 2 1
CHARGER
28,
BQ24745RHDR
Project code : Arsenal DJ1 Discrete Block Diagram INPUTS OUTPUTS
PCB P/N : +DC_IN_SS
+PWR_SRC
+CHAGER_SRC
Revision : 09915-1 DDR III 800/1066 DDRIII DIMM1 SYSTEM DC/DC
AMD Champlain 800/1066/1333 18
3
TPS51125RGER-GP 46
D CPU S1G4 INPUTS OUTPUTS D
DDR III 800/1066 DDRIII DIMM2
8,9,10,11 +5V_ALW2
Clock Generator 800/1066/1333 19
+PWR_SRC +3.3V_RTC_LDO 2
VRAM +5V_ALW
ICS9LPRS480BKLFT
7 64Mx16bx4 (512MB)4 +3.3V_ALW
HyperTransport
OUT
84,85
IN
16X16 SYSTEM DC/DC
gDDR3 RT8209EGQW 48
700MHz INPUTS OUTPUTS
+PWR_SRC +1.1V_ALW 3
ATI PARK-S3 North Bridge CPU CORE
AMD RS880M ISL6265AHRTZ-T-GP 47
CRT RGB CRT PCIe x 16
55
CPU I/F LVDS, CRT I/F INPUTS OUTPUTS
INTEGRATED GRAHPICS 10/100 NIC RJ45
PCIE x 1 +VCC_CORE
ATHEROS AR8152 CONN +PWR_SRC +VDDNB
12,13,14,15 3
C C
LCD LVDS
DDR III SUS&VTT
I/O Board
Connector
54
80,81,82,83
Left Side:
USB 2.0 x 2 TPS51116RGER-GP-U 49
USB x 2
INPUTS OUTPUTS
A-LINK +PWR_SRC +1.5V_SUS
4X4 Mini-Card 3
PCIE x 1 802.11a/b/g SYSTEM DC/DC
76
USB 2.0 x 1 APL5930KAI 52
INPUTS OUTPUTS
CardReader South Bridge +3.3V_ALW
+1.8V_RUN
AMD SB820M +1.8V_DELAY
SD/SDIO/MMC
MS/MS Pro/xD
Realtek USB2.0
14 USB 2.0 ports SYSTEM DC/DC
44 53
RTS5138 Swithes
ETHERNET (10/100/1000Mb)
32 INPUTS OUTPUTS
High Definition Audio
CAMERA +3.3V_ALW +3.3V_RUN
4 PCIE GPP USB 2.0 USB 2.0 x 1
73
(Option) +5V_ALW +5V_RUN
B 6 SATA ports B
+1.5V_SUS +1.5V_RUN
ACPI 1.1
AZALIA +1.1V_ALW +1.1V_RUN
Internal Analog MIC Azalia LPC I/F USB 2.0 x 1 Bluetooth 73
2
VGA
CODEC PCI/PCI BRIDGE RT8208AGQW 86
LPC Bus
INPUTS OUTPUTS
MIC IN & 20,21,22,23,24
USB 2.0 x 1 Right Side:
+PWR_SRC +VCC_GFX_CORE
USB x 1 63
OP AMP PCB LAYER
HP OUT
92HD79B1 30 L1: Top
KBC L2: GND
SATA
SATA
SPI NUVOTON L3: Signal
37
2CH SPEAKER NPCE781BA0DX L4: Signal
L5: VCC
L6: Signal
L7: GND
A L8: Bottom A
Flash ROM Touch Int. Thermal
HDD ODD
59 59 2MB PAD KB EMC2102 Wistron Corporation
62 68 68 25 39 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Fan Block Diagram
Size Document Number Rev
58
A3 Arsenal DJ1 Discrete X01
Date: Friday, May 07, 2010 Sheet 2 of 89
5 4 3 2 1
A B C D E
Power Shape
Regulator LDO Switch
Power Block Diagram
4 4
+PWR_SRC
Adapter
ISL6265AHRTZ RT9025 RT8208AGQW RT8209EGQW TPS51116RGER
AO4407A
Charger
+1.5V_SUS
+VCC_CORE +VDDNB(CPU) VDDR(CPU) +VCC_GFX_CORE +1.1V_ALW
Battery +PBATT
SI4634DY AO4468 AO4468
TPS51125RGER
3 3
+1.1V_RUN
+1.1V_GFX_RUN +1.5V_RUN
+3.3V_RTC_LDO +5V_ALW +5V_ALW2 +3.3V_ALW
G547F2P81U AO4468 G547F2P81U SI2301BDS AO4468 PA102FMG APL5930 APL5930
+5V_USB1 +5V_RUN +5V_USB2 +3.3V_DELAY +3.3V_RUN +3.3V_LAN +1.8V_RUN +1.8V_DELAY
2 2
RESISTER RESISTER G5285T11U RTS5138 RT9013-25PB AR8152
+PVDD +AVDD +LCDVDD +3.3V_RUN_CARD +2.5V_RUN +1.2V_LOM
1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Power Block Diagram
Size Document Number Rev
Custom
Arsenal DJ1 Discrete X01
Date: Friday, May 07, 2010 Sheet 3 of 89
A B C D E
5 4 3 2 1
SB820M SMBus Block Diagram KBC SMBus Block Diagram
+5V_RUN
D D
SRN10KJ-5-GP
PSDAT1 TPDATA TPDATA TPDATA
TouchPad Conn.
PSCLK1 TPCLK TPCLK TPCLK
+KBC_PWR
+3.3V_RUN SRN4K7J-8-GP
Battery Conn.
SRN100J-3-GP
SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB
SDA1 BAT_SDA PBAT_SMBDAT1 SMBus address:16
SRN2K2J
DAT_SMB (In I/O Board)
SB820M SCL0 SB_SMBCLK
SB_SMBCLK
DIMM 1 BQ24745RHDR
SCL
SDA0 SB_SMBDATA
C SB_SMBDATA C
SCL1 SMB_CLK
+3.3V_ALW
SDA
SMBus Address:A0
KBC SCL
SDA SMBus address:12
SDA1 SMB_DATA
(In I/O Board)
SCL3_LV/IMC_GPIO13 CPU_SIC
NPCE781
SDA3_LV/IMC_GPIO14 CPU_SID SRN10K2J
SB_SMBCLK
DIMM 2 +3.3V_RUN
SCL
SB_SMBDATA
SDA
+KBC_PWR
+3.3V_RUN
SMBus Address:A4
SRN4K7J-8-GP
CLOCK GEN Thermal
THERM_SCL SCL SMBus address:7A
SRN4K7J-8-GP
THERM_SDA SDA
SB_SMBCLK
SCLK
SB_SMBDATA
SDATA
GPIO61/SCL2 KBC_SCL1
2N7002SPT
GPIO62/SDA2 KBC_SDA1
SMBus address:D2
MINI CARD
SB_SMBCLK
SMB_CLK
B SB_SMBDATA B
SMB_DATA
+3.3V_DELAY
+1.5V_SUS
SRN1K2J CPU S1G4 2K2R2J-2-GP
SIC
CPU_SIC DDC1CLK LDDC_CLK
CPU_SID
SID
DDC1DATA LDDC_DATA LCD Conn.
SMBus address:98
+5V_CRT_RUN
ATI +3.3V_DELAY
+3.3V_DELAY
PARKLP-S3 SRN2K2J-8-GP
DDC_CLK_CON
A
SRN2K2J-8-GP
DDC_DATA_CON CRT CONN A
DDC2CLK M92CRT_DDCCLK
2N7002SPT
DDC2DATA M92CRT_DDCDATA
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
SMBUS BLOCK DIAGRAM
Size Document Number Rev
A2
Arsenal DJ1 Discrete X01
Date: Friday, May 07, 2010 Sheet 4 of 89
5 4 3 2 1
5 4 3 2 1
D
Thermal Block Diagram Audio Block Diagram D
SPKR_PORT_D_L+
SPKR_PORT_D_L-
AUD_SPK_L+
AUD_SPK_L-
SPEAKER
SPKR_PORT_D_R- AUD_SPK_R-
SPKR_PORT_D_R+ AUD_SPK_R+
60
60D4R2F
CPU
HP1_PORT_B_L
HP1_PORT_B_R
AUD_HP1_JACK_L
AUD_HP1_JACK_R
Bead
Bead
AUD_HP1_JACK_L1
AUD_HP1_JACK_R1
HP
DP1 H_THERMDA THERMDA 60D4R2F
SC470P50V3JN-2GP
OUT
C
DN1 H_THERMDC THERMDC
Codec 60
C
Thermal 92HD81
EMC2102 VREFOUT_A_OR_F AUD_VREFOUT_B
GPU MIC
4K7R2J-2-GP
4K7R2J-2-GP
DP2 VGA_THERMDA DPLUS
SC470P50V3JN-2GP HP0_PORT_A_L AUD_EXT_MIC_L IN
DN2 VGA_THERMDC DMINUS HP0_PORT_A_R AUD_EXT_MIC_R
60
B
DMIC_CLK/GPIO1
AUD_DMIC_CLK
33R2J-2-GP
AUD_DMIC_CLK_G
Digital B
DMIC0/GPIO2
AUD_DMIC_IN0
33R2J-2-GP
AUD_DMIC_IN0_R MIC
Array 54
DP3 EMC2102_DP3
PMBS3904
SC470P50V3JN-2GP
SC1U10V3KX-3GP
DN3 EMC2102_DN3
AUD_INT_MIC_R_L INT_MIC_L_R
System sensor, put PORT_C_L Internal
between CPU and NB.
PORT_C_R AUD_INT_MIC_R_L MIC
VREFOUT_C
AUD_VREFOUT_C
30 4K7R2J-2-GP 60
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
THERMAL/AUDIO BLOCK DIAGRAM
Size Document Number Rev
Custom
Arsenal DJ1 Discrete X01
Date: Friday, May 07, 2010 Sheet 5 of 89
5 4 3 2 1
5 4 3 2 1
SB820M Strapping NB880M Strapping
Capture from 45484 Rev. 1.02 AMD SB8xx-Series Southbridge Design Guide Capture from 46113_rs880m_ds_nda_1.03
Name Strap Name Schematic Note Name Strap Function Schematic Note
Embedded Controller (EC) Enables debug bus access
LPCCLK0 ECEnableStrap DAC_VSYNC STRAP_DEBUG_BUS_GPIO through memory I/O pads and GPIOs.
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