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A B C D E
1 1
2 2
Mosaic Schematics Document
uFCBGA/uFCPGA Northwood
2001-09-19
3 3
REV: 0.1
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
0.1
Date: Wednesday, September 19, 2001 Sheet 1 of 37
A B C D E
A B C D E
Compal confidential Block Diagram
Model Name :ADY13(Mosaic)
File Name : LA-1271
.%$$
!
-/$
8"
1
page 6
1
page 4,5
,;/ page 5 page 14
page 7 $$
page 7
.$/$
/
.
(-
'""(*
page 15
page 11,12
63;
8
page 8,9
page 15
2 2
:
%
page 27
0
IDSEL:AD20
page 30
IDSEL:AD17
(PIRQA#,GNT#3,REQ#3)
(PIRQA/B#,GNT#2,REQ#2)
<37
AC-LINK
"
page 25
0)0+39
)56+73 page 16,17
page 20 page 21
3
(<;
page 20
9
page 22
"&
'""(()*
+,
-+,99
3
page 19 page 23
!))## 4
($(-
page 30
14M_5V page 26 page 24
""# page 28 ) )
$% page 27 page 27
-
page 31 page 27
&)## 12" ""
page 29 page 19
!
4 4
page 29
""
page ) 3
32,33,34,35,36,37 page 28 page 27
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
0.1
Date: Wednesday, September 19, 2001 Sheet 2 of 37
A B C D E
5 4 3 2 1
Power Managment table
Model
+3VS
Function Mosaic Midas
Signal +5VS CHIPS Rev CHIPS Rev
+3VALW +3V +1.8VS RG82845 FW82801CAM
D FDD YES YES +5VALW +5V +1.5VS SST-Build A3(QC45) B1(QC42) D
State +1.8VALW +2.5V +1.2VP
PS/2 YES YES +12VALW +CPU_CORE
+1.25V
Serial port NO NO
ON ON ON
S0
Parallel port YES YES
S1 ON ON ON
RJ45 YES YES
S3 ON ON OFF
OZ6912/TPS2211 YES YES
S5 S4/AC ON OFF OFF
3Com Lan YES YES
chipset(3C920)
S/W S5 S4/AC don't exist
disable OFF OFF OFF
C C
Note1:
"@" means all model depop
Note2:
Removed serial port,because add 2nd Fan
B
B
A A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL Note & Revision
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
ADY13 LA-1271 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Wednesday, September 19, 2001 Sheet 3 of 37
5 4 3 2 1
A B C D E
1 1
+CPU_CORE
AC10
AC12
AC14
AC16
AC18
AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18
AB11
AB13
AB15
AB17
AB19
AE10
AE12
AE14
AE16
AE18
AE20
AF11
AF13
AF15
AF17
AF19
AF21
AC8
AD7
AD9
AA8
AB7
AB9
AE6
AE8
AF2
AF5
AF7
AF9
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
A10
A12
A14
A16
A18
A20
B11
B13
B15
B17
B19
E10
C8
D7
D9
A8
B7
B9
HA#[3..31] U4A HD#[0..63]
<8> HA#[3..31] HD#[0..63] <8>
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
HA#3 K2 B21 HD#0
HA#4 A#3 D#0 HD#1
K4 B22
HA#5 A#4 D#1 HD#2
L6 A23
A#5 D#2
HA#6 K1 A25 HD#3
HA#7 A#6 D#3 HD#4
L3 C21
HA#8 A#7 D#4 HD#5
M6 D22
HA#9 A#8 D#5 HD#6
L2 B24
HA#10 A#9 D#6 HD#7
M3 C23
HA#11 A#10 D#7 HD#8
M4 C24
A#11 D#8
HA#12 N1 B25 HD#9
HA#13 A#12 D#9 HD#10
M1 G22
HA#14 A#13 D#10 HD#11
N2 H21
HA#15 A#14 D#11 HD#12
N4 C26
HA#16 A#15 D#12 HD#13
N5 D23
HA#17 A#16 D#13 HD#14
T1 J21
HA#18 A#17 D#14 HD#15
R2 D25
HA#19 A#18 D#15 HD#16
P3 H22
HA#20 A#19 D#16 HD#17
P4 E24
HA#21 A#20 D#17 HD#18
R3 G23
2 HA#22 A#21 D#18 HD#19 2
T2 F23
HA#23 A#22 D#19 HD#20
U1 F24
HA#24 A#23 D#20 HD#21
P6 E25
HA#25 A#24 D#21 HD#22
U3 F26
HA#26 A#25 D#22 HD#23
T4 D26
HA#27 A#26 D#23 HD#24
V2 L21
HA#28 A#27 D#24 HD#25
R6 G26
HA#29 A#28 D#25 HD#26
W1 H24
HA#30
HA#31
T5
U4
V3
A#29
A#30
A#31
Mobile D#26
D#27
D#28
M21
L22
J24
HD#27
HD#28
HD#29
A#32 D#29 HD#30
W2 K23
A#33 D#30 HD#31
Y1 H25
A#34 D#31 HD#32
AB1 M23
<8> HREQ#[0..4]
HREQ#[0..4]
HREQ#0 J1
A#35
NorthWood D#32
D#33
D#34
N22
P21
M24
HD#33
HD#34
HD#35
HREQ#1 REQ#0 D#35 HD#36
K5 N23
HREQ#2 REQ#1 D#36 HD#37
J4 M26
HREQ#3 REQ#2 D#37 HD#38
J3 N26
HREQ#4 REQ#3 D#38 HD#39
H3 N25
REQ#4 D#39 HD#40
<8> HADS# G1 R21
ADS# D#40 HD#41
P24
D#41 HD#42
R25
D#42 HD#43
AC1 R24
+CPU_CORE AP#0 D#43 HD#44
V5 T26
R98 10K_0402 AP#1 D#44 HD#45
AA3 T25
BINIT# D#45 HD#46
1 2 AC3 T22
3
<8> HBR0#
<8> HBPRI#
<8> HBNR#
<8> HLOCK#
1 2 R31 51.1_1%
H6
D2
G2
G4
IERR#
BR0#
BPRI#
BNR#
LOCK#
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
T23
U26
U24
U23
V25
U21
V22
V24
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
3
CLK_HCLK AF22 W26 HD#55
<14> CLK_HCLK BCLK0 D#55
CLK_HCLK# AF23 Y26 HD#56
<14> CLK_HCLK# BCLK1 D#56
W25 HD#57
D#57 HD#58
Y23
D#58 HD#59
Y24
D#59 HD#60
<8> HIT# F3 Y21
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