Service Manuals, User Guides, Schematic Diagrams or docs for : Dell dell_studio_1535_quanta_fm7b_hepburn_intel_uma_rev_d3b_sch
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FM7B Hepburn Intel UMA VER : D3B
A *FM7B M/B PCB A
FAN & THERMAL POWER
Penryn SMSC1423
PG 39
REGULATOR CPU VR
POWER (478 Micro-FCPGA) +1.5V_RUN/+1.05V_VCCP
SYSTEM PG 48 PG 51
RESET CIRCUIT PG 44 CLOCK
SLG8SP513V REGULATOR DC/DC
BATT (QFN-64) +1.8V_SUS/+1.25V_RUN +3.3V_ALW/+5V_ALW/+15V_ALW
PG 3,4 PG 17 /+0.9V_DDR_VTT
AC/BATT CHARGER PG 46 PG 49 PG 52
CONNECTOR 1066 MHz FSB
RUN POWER SW
PG 54 +3.3V_SUS/+5V_SUS LVDS
+5V/+3.3V/+1.8V
Panel Connector
PG 53 PG 26
Cantiga SDVO
HDMI
DDR2-SODIMM1 667/800 MHZ DDR II PI3VDP411LSZDE HDMI CONN.
B
1329 uFCBGA PG 26 B
PG 18
PG 15,16
VGA
667/800 MHZ DDR II CRT CONN.
DDR2-SODIMM2 PG 27
PG 5,6,7,8,9,10
PG 15,16 LAN
USB2.0 x 4
USB conn x 4 BCM5784M RJ45/Magnetics
SATA-ODD SATA PG 35
DMI interface PCIEx1 PG 43
PG 36 PG 42
PCIEx1
SATA-HDD SATA EXPRESS-CARD
USB2.0
PG 36 R5538
PG 30
PI2EQX3211BHE ICH9-M PCIEx2
E-SATA Combo SATA
USB2.0 MINI-CARD
with USB CONN PG 35 PG 35
PCIEx1 WLAN
676 BGA PG 34
C USB2.0 C
IHDA
Cantiga USB2.0
USB2.0 MINI-CARD
PG 11,12,13,14 WWAN
AUDIO/AMP PG 33
Biometric
92HD73C Camera + D-MIC PG 38
LPC MINI-CARD
PG 41
PG 40 WPAN
CIR PG 33
TSOP36136TR
Audio Audio KBC PG 37
ITE8512 1394
SPK conn Jacks x3 18X8 1394 CONN.
33MHz PCI 8-in-1 Card Reader PG 29
PG 40 PG 41 PG 31 Keyboard
R5C833
SPI PS/2 PG 37 Card Reader CONN.
PG 28 PG 30
USER
INTERFACE FLASH Touchpad
D D
PG 38 2Mbyts
PG 32 PG 37 QUANTA
Title
COMPUTER
Schematic Block Diagram1
Size Document Number Rev
FM7B 1A
Date: Monday, July 21, 2008 Sheet 1 of 60
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Table of Contents Power States
CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE PAGE DESCRIPTION ACTIVE IN
SIGNAL
1 Schematic Block Diagram
2 Front Page +PWR_SRC 10V~+19V 4,26,32,34,46,48,49,51,52,56 MAIN POWER S0~S5
3-4 Merom
+RTC_CELL +3.0V~+3.3V 11,14,31,32 RTC S0~S5
5-10 Crestline
A 11-14 ICH8M +3.3V_ALW +3.3V 3,31,32,34,36,37,38,44,46,49,52,53,54 8051 POWER ALWON S0~S5 A
15-16 DDRII SO-DIMM(200P)
+5V_ALW +5V 35,36,46,48,49,52,53,54,56 LCD/CHARGE POWER ALWON S0~S5
17 Clock Generator
18 HDMI +15V_ALW +15V 26,36,37,52,53 LARGE POWER +5V_ALW S0~S5
23 LCD Conn. & SSP
+3.3V_LAN +3.3V 42,43 LAN POWER AUX_ON
24 CRT Conn
25 SATA Conn +5V_SUS +5V 14,38,51,53 SLP_S5# CTRLD POWER SUS_ON
26-27 CARD READER/Conn & 1394
+3.3V_SUS +3.3V 3,11,12,13,14,26,30,37,38,43,48,49,51,53 SLP_S5# CTRLD POWER 3.3V_SUS_ON
28 Express Card & Smart Card
29-30 Mini Card +1.8V_SUS +1.8V 6,8,9,15,48,49,53 SODIMM POWER DDR_ON
31 SIO (ITE8512)
+0.9V_DDR_VTT +0.9V 16,49,53 SODIMM POWER 0.9V_DDR_VTT_ON
32 FLASH/RTC
33 USB +5V_RUN +5V 14,18,27,36,37,38,39,40,41,53 SLP_S3# CTRLD POWER RUN_ON
35 TP / KEYBOARD 14,18,27,36,37,38,39,40,41,53
+3.3V_RUN +3.3V SLP_S3# CTRLD POWER 3.3V_RUN_ON
36 SWITCH /LED
B 37 FAN & Thermal +1.8V_RUN +1.8V 18,38,53 SDVO POWER RUN_ON B
38-39 Audio CODEC(ALC888)/Phone Jack
+1.5V_RUN +1.5V 4,9,14,30,33,34,48,53,56 CALISTOGA/ICH8 POWER 1.5V_RUN_ON
40-41 LOM / Switch
44 System Reset Circuit +1.25V_RUN +1.25V 6,9,14,49,53 CALISTOGA/ICH8 POWER 1.25V_RUN_ON
46 Battery Selector & Charger
+1.05V_VCCP +1.05V 3,4,5,6,8,9,11,14,48,56 CPU/CALISTOGA/ICH8 POWER 1.05V_RUN_ON
48 1.05VCCP / 1.5VRUJN
49 DDR2_1.8VSUS, 0.9V +VCC_CORE +0.7V~+1.77V 4,51,56 CPU CORE POWER IMVP_VR_ON
51 CPU_ISL6266(2phase) LCDVCC_TST_EN
+LCDVCC +3.3V 26 LCD Power & ENVDD
52 MAX8744 (+5.5V,+3,3V)
53 RUN Power Switch +5V_MOD +5V 36 Module Power MODC_EN#
54 DCIN,Batt
+5V_HDD +5V 36 HDD Power HDDC_EN#
55 PAD& SCREW
56 EMI CAP +PBATT +10V~+17V MAIN BATTERY CHG_PBATT
57 SMBUS BLOCK
+SBATT +10V~+17V SECOND BATTERY CHG_SBATT
58 Power Block Dianram
C C
GND PLANE PAGE DESCRIPTION
8731AGND
46
AGND_0.9V
49
AGND_DC/DC
52
AGND_DC2
48
AGND_DDR
49
AGND_ISL6260
51
GND ALL
D D
QUANTA
Title
COMPUTER
Index & Power Status
Size Document Number Rev
FM6B 1A
Date: Monday, June 30, 2008 Sheet 2 of 60
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
H_A#[3..16] U23A H_D#[0..63] U23B H_D#[0..63]
5 H_A#[3..16] 5 H_D#[0..63] H_D#[0..63] 5
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# 5 D[0]# D[32]#
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# 5 D[1]# D[33]#
ADDR GROUP 0
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
H_A#6
H_A#7
K5
A[5]#
A[6]#
BPRI# H_BPRI# 5
6/27-50 H_D#3
H_D#4
G22
D[2]#
D[3]#
D[34]#
D[35]# V26 H_D#35
H_D#36
M3 A[7]# DEFER# H5 H_DEFER# 5 F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# 5 D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# 5 D[6]# D[38]#
DATA GRP 0
DATA GRP 2
H_A#10 N3 +1.05V_VCCP H_D#7 E23 U23 H_D#39
A[10]# H_BR0# 5 D[7]# D[39]#
H_A#11 P5 F1 Layout Note: H_D#8 K24 Y25 H_D#40
H_A#12 A[11]# BR0# R78 56 H_D#9 D[8]# D[40]# H_D#41
P2 A[12]# Place R44 G24 D[9]# D[41]# W22
1
CONTROL
H_A#13 L2 D20 H_IERR# 1 2 +1.05V_VCCP H_D#10 J24 Y23 H_D#42
A
H_A#14 A[13]# IERR# R44 close
to H_D#11 D[10]# D[42]# H_D#43 A
P4 A[14]# INIT# B3 H_INIT# 11 J23 D[11]# D[43]# W24
H_A#15 P1 *51/F_NC CPU. H_D#12 H22 W25 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# 5 F26 D[13]# D[45]# AA23
M1 H_D#14 K22 AA24 H_D#46
5 H_ADSTB#0
2
H_REQ#[0..4] ADSTB[0]# R45 D[14]# D[46]#
5 H_REQ#[0..4] RESET# C1 1 2 0 0603 H_RESET# H_RESET# 5
H_D#15 H23 D[15]# D[47]# AB25 H_D#47
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 5 5 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 5
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 5 5 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 5 5 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 5
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# 5 H_D#[0..63] H_D#[0..63]
H_REQ#4 L1
H_A#[17..35] REQ[4]# 5 H_D#[0..63] H_D#[0..63] 5
G6 H_D#16 N22 AE24 H_D#48
5 H_A#[17..35] HIT# H_HIT# 5 D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# 5 D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
A[18]# D[18]# D[50]#
ADDR GROUP 1
H_A#19 R3 AD4 ITP_BPM#0 H_D#19 R23 AB22 H_D#51
H_A#20 A[19]# BPM[0]# ITP_BPM#1 H_D#20 D[19]# D[51]# H_D#52
W6 A[20]# BPM[1]# AD3 Layout Note: L23 D[20]# D[52]# AB21
XDP/ITP SIGNALS
H_A#21 U4 AD1 ITP_BPM#2 Place voltage H_D#21 M24 AC26 H_D#53
A[21]# BPM[2]# D[21]# D[53]#
DATA GRP 1
DATA GRP 3
H_A#22 Y5 AC4 ITP_BPM#3 H_D#22 L22 AD20 H_D#54
H_A#23 A[22]# BPM[3]# ITP_BPM#4 divider within H_D#23 D[22]# D[54]# H_D#55
U1 A[23]# PRDY# AC2 M23 D[23]# D[55]# AE22
H_A#24 R4 A[24]# PREQ# AC1 ITP_BPM#5 0.5" of GTLREF H_D#24 P25 D[24]# D[56]# AF23 H_D#56
H_A#25 T5 AC5 ITP_TCK pin H_D#25 P23 AC25 H_D#57
H_A#26 A[25]# TCK ITP_TDI H_D#26 D[25]# D[57]# H_D#58
T3 A[26]# TDI AA6 P22 D[26]# D[58]# AE21
H_A#27 W2 AB3 ITP_TDO H_D#27 T24 AD21 H_D#59
H_A#28 A[27]# TDO ITP_TMS +1.05V_VCCP H_D#28 D[27]# D[59]# H_D#60
W5 A[28]# TMS AB5 R24 D[28]# D[60]# AC22
H_A#29 Y4 AB6 ITP_TRST# H_D#29 L25 AD23 H_D#61
H_A#30 A[29]# TRST# ITP_DBRESET# H_D#30 D[29]# D[61]# H_D#62
U2 A[30]# DBR# C20 ITP_DBRESET# 13 T25 D[30]# D[62]# AF22
2
H_A#31 V4 H_D#31 N25 AC23 H_D#63
H_A#32 A[31]# R43 56 R386 D[31]# D[63]#
W3 L26 AE25
H_A#33
H_A#34
AA4
A[32]#
A[33]# THERMAL 1 2 +1.05V_VCCP 4/23-38 1K/F
5
5
H_DSTBN#1
H_DSTBP#1 M26
DSTBN[1]#
DSTBP[1]#
DSTBN[3]#
DSTBP[3]# AF24
H_DSTBN#3 5
H_DSTBP#3 5
AB2 A[34]# 5 H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 5
B H_A#35 AA3 D21 H_PROCHOT# B
PAD T5
1
A[35]# PROCHOT# H_THERMDA V_CPU_GTLREF AD26 COMP0
5 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 H_THERMDA 39 GTLREF COMP[0] R26 Note:
B25 H_THERMDC R53 2 1 *1K/F_NC CPU_TEST1 C23 MISC COMP[1] U26 COMP1 H_DPRTSTP need to daisy chain
THERMDC H_THERMDC 39 TEST1
1
A6 R52 2 1 *1K/F_NC CPU_TEST2 D25 AA1 COMP2
11 H_A20M# A20M# TEST2 COMP[2] from ICH9 to IMVP6 to CPU.
ICH
A5 C7 H_THERM R387 PAD T87 CPU_TEST3 C24 Y1 COMP3
11 H_FERR# FERR# THERMTRIP# TEST3 COMP[3]
C4 R80 56 2K/F PAD T85 CPU_TEST4 AF26
11 H_IGNNE# IGNNE# TEST4
1 2 +1.05V_VCCP PAD T84 CPU_TEST5 AF1 E5
TEST5 DPRSTP# H_DPRSTP# 6,11,51
D5 H CLK PAD T86 CPU_TEST6 A26 B5
11 H_STPCLK# H_DPSLP# 11
2
STPCLK# PAD T4 CPU_TEST7 TEST6 DPSLP#
11 H_INTR C6 LINT0 C3 TEST7 DPWR# D24 H_DPWR# 5
11 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 17 6,17 CPU_MCH_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD 11
11 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 17 6,17 CPU_MCH_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 5
6,17 CPU_MCH_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# 51
Quard Core Only
F6 D2 Penryn Ball-out Rev 1a
TDI_1/RSV RSVD[06] PAD T3
D3 TDO_2/RSV
N5 BMP_1#[0]/RSV
M4 BMP_1#[1]/RSV
B2 C450 *2200P_NC
BMP_1#[2]/RSV H_THERMDA H_THERMDC
AE8 BMP_1#[3]/VSS 1 2
D8 DCLKPH_1/VSS
F8 50
ACLKPH_1/VSS
D22 GTLREF_2/RSV
T2 THRMDA_1/RSV
V3 +1.05V_VCCP +3.3V_ALW
THRMDC_1/RSV
AA8 HFPLL_1/VSS
AC8 SPARE_1[4]/VSS Voltage Level shift
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