Service Manuals, User Guides, Schematic Diagrams or docs for : ECS ECS laptop schematic diagram
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3 2 1
o m
.c
D
INTEL
s
YONAH
HyperTransport
t ic
a
CN. 9/ 22
DDR II DDR II
m
LCD /
INVERTER CN.18 / 4
LVDS
RC410M C
e
TV-OUT
To TV BD CN.1 PCI-E x 1
h
CRT
PCI-E x 1
To CRT BD CN.3 USB x 1
c
New Card Mini Card
USB
CN.2/ 5/ 10
PCI-E x 2 CN.16 CN.27
s
USB x 1 TO 3G/SIM 2nd
-
USB x 3 USB x 1 Mini CARD BD
USB x 1
CN.6
p
USB x 1
RTL8100CL
PCI
to
RJ45 CN.7
AMP CN.17
1394
SB460 B
CN.11 Azalia AUDIO SPEAKER
Card OZ128 CODEC
p
Reader CN.14
PATA CN.13
To RF CN.21 ODD
la
Switch CN.15 TO MDC
SATA
LPC BD
To TP CN.23 HDD
IT8512
.
BD CN.12
KB CN.8
w w A
w 3 2 1
A B C D E
R58 2 1 200R +V1.05S
TDI pullup must be placed within 300ps of CPU TDI pin(within 2")
m
H_BR0#_R R59 2 1 0R Place testpoint on H_IERR# with a GND 0.1" away.
H_A#[3..31] H_BR0# 5
COMP0 R39 1 2 27.4R/F
5 H_A#[3..31] +V1.05S
U25A COMP1 R38 1 2 54.9R/F
YONAH CPU
H_A#3 J4 A6 H_A20M# COMP2 R57 1 2 27.4R/F
A3# A20M# H_FERR# H_A20M# 12
o
H_A#4 L4 A5 COMP3 R56 1 2 54.9R/F IERR# R47 2 1 56R
A4# FERR# H_IGNNE# H_FERR# 12
H_A#5 M3 C4
A5# IGNNE# H_IGNNE# 12
INTEL 1/3
Legacy
H_A#6 K5 Layout note: H_CPURST# R60 2 1 220R
H_A#7 A6# H_STPCLK# H_PWRGD R291 332R/F
M1 A7# STPCLK# D5 H_STPCLK# 12 2 1
H_A#8 N2 C6 H_INTR (1).COMP0 & COMP2 need to be H_FERR# R296 2 1 56R
.c
A8# LINT0 H_NMI H_INTR 12
H_A#9 J1 B4 H_DPSLP# R399 2 1 200R
A9# LINT1 H_SMI# H_NMI 12 Zo=27.4ohm traces.Best estimate is H_CPUSLP#
H_A#10 N3 A3 R410 2 1 200R
A10# SMI# H_SMI# 12
4 H_A#11 P5 18mil wide trace for outer layers 4
H_A#12 A11#
P2 A12# ADS# H1 H_ADS# 5
H_A#13 L1 E2 and 14mil if no internal layer. H_A20M# R293 2 1 @390R
A13# BNR# H_BNR# 5 H_INIT#
H_A#14 P4 G5 R298 2 1 @390R
CONTROL
A14# BPRI# H_BPRI# 5 H_INTR
H_A#15 (2).See RDDP of Banias .traces R297 @390R
s
P1 A15# 2 1
H_A#16 R1 H5 H_NMI R299 2 1 @390R
A16# DEFER# H_DEFER# 5 should be shorter than 0.5".Refer to H_SMI#
H_A#17 Y2 F21 R292 2 1 @390R
A17# DRDY# H_DRDY# 5 H_STPCLK#
H_A#18 U5 E1 latest CS layout COMP1,COMP3 should R294 2 1 @390R
A18# DBSY# H_DBSY# 5 H_IGNNE#
H_A#19 R3 R295 2 1 @390R
ic
H_A#20 A19# H_BR0#_R be routed as Zo=55ohm traces shorter
W6 A20# BR0# F1
ADDR GROUP
H_A#21 U4 than 0.5" RN6 56R/F-8P4R
H_A#22 A21# IERR# H_BPM3_ITP#
Y5 A22# IERR# D20 4 5
H_A#23 U2 B3 H_INIT# H_BPM2_ITP# 3 6
A23# INIT# H_INIT# 12
t
H_A#24 R4 (Layout) GTLREF : 0.5" max length H_BPM1_ITP# 2 7
H_A#25 A24# H_BPM0_ITP#
T5 A25# LOCK# H4 H_LOCK# 5 1 8
H_A#26 T3
H_A#27 A26# H_CPURST# RN5 56R/F-8P4R
W3 A27# RESET# B1 H_CPURST# 5
H_A#28 W5 F3 GTL_REF0 R40 2 1 1K/F 4 5
A28# RS0# H_RS#0 5 +V1.05S
a
H_A#29 Y4 F4 H_TDO 3 6
A29# RS1# H_RS#1 5 H_BPM5_PREQ#
H_A#30 W2 G3 R42 1 2 2K/F 2 7
A30# RS2# H_RS#2 5 H_BPM4_PRDY#
H_A#31 Y1 G2 1 8
A31# TRDY# H_TRDY# 5
H_ADSTB#0 L2 G6 +V3.3S BSEL0 R49 2 1 1K
5 H_ADSTB#0 H_ADSTB#1 ADSTB0# HIT# H_HIT# 5 BSEL1
V4 E4 R35 2 1 1K
5 H_ADSTB#1 H_REQ#[0..4] ADSTB1# HITM# H_HITM# 5 BSEL2 R43 2 1 1K
5 H_REQ#[0..4] +V1.05S
m
1
H_REQ#0 K3 AD4 H_BPM0_ITP# H_TDI R55 2 1 150R/F
REQ0# BPM0#
1
H_REQ#1 H_BPM1_ITP# R305 H_TMS R54 1 39.2R/F
H_REQ#2
H2
K2
REQ1# BPM1# AD3
AD1 H_BPM2_ITP#
C modify R339
2
REQ2# BPM2#
1
3 H_REQ#3 J3 AC4 H_BPM3_ITP# 330R 3
SIGNALS
REQ3# BPM3#
e
H_REQ#4 L5 R338 @1K
H_D#[0..63] REQ4# H_BPM4_PRDY# H_PROCHOT#
2
5 H_D#[0..63] PRDY# AC2 H_PROCHOT# 12
H_BPM5_PREQ# 56R
2
AC1
C
H_D#0 PREQ#
E22 D0#
H_D#1 H_TCK Q52
2
F24 AC5 B
ITP
D1# TCK
h
H_D#2 E26 AA6 H_TDI @2N3904 +V3.3S
C
H_D#3 D2# TDI H_TDO @330R
H22 D3# TDO AB3
H_PROCHOT_S# ITP_DBRESET# R270 1
E
H_D#4 F23 AB5 H_TMS R312 1 2 B Q50 2 150R/F
H_D#5 D4# TMS H_TRST# @2N3904
G25 D5# TRST# AB6
H_D#6 ITP_DBRESET#
c
E25 D6# DBR# C20
E
H_D#7 E23 D7# H_TEST1 R41
H_D#8 K24 D8# 1 2 51R
H_D#9 +V1.05S H_TEST2 R45 2 51R
H CLK THERM
G24 D9# 1
H_D#10 J24 D21 H_PROCHOT_S#
s
H_D#11 D10# PROCHOT# H_THERMDA H_TCK R52
J23 D11# THERMDA A24 1 2 27.4R/F
1
H_D#12 H26 A25 H_THERMDC H_TRST# R53 1 2 680R
H_D#13 D12# THERMDC R387
F26
-
H_D#14 D13# PM_THRMTRIP#
K22 D14# THERMTRIP# C7 PM_THRMTRIP# 4
H_D#15 H25 470R
H_D#16 D15#
N22 D16#
H_D#17 H_DPRSTP#
2
K25 D17# H_DPRSTP# 25
H_D#18 P26 A21 CLK_CPU_BCLK-
p
C
D18# BCLK1 CLK_CPU_BCLK- 10
H_D#19 R23 A22 CLK_CPU_BCLK+ (Layout) Close to CPU side
D19# BCLK0 CLK_CPU_BCLK+ 10
H_D#20 L25 R382 1 2 470R B Q24
D20# 12,25 DPRSLPVR
DATA GROUP
H_D#21 L22 2N3904 H_A20M# C493 1 2 @180P
D21#
1
H_D#22 L23 R26 COMP0 H_INIT# C495 1 2 @180P
D22# COMP0 H_NMI
E
H_D#23 COMP1 R380 C496 @180P
to
M23 D23# COMP1 U26 1 2
H_D#24 P25 U1 COMP2 H_IGNNE# C498 1 2 @180P
2 H_D#25 D24# COMP2 COMP3 100K 2
P22 D25# COMP3 V1
H_D#26 P23
H_D#27 D26# H_DPSLP#
2
T24 D27# DPSLP# B5 H_DPSLP# 4,12
H_D#28 R24 D24
D28# DPWR# H_DPWR# 5 +V3.3S
MISC
H_D#29 L26 D6 H_PWRGD
D29# PWRGOOD H_CPUSLP# H_PWRGD 12
H_D#30 T25 D7
p
D30# SLP# H_CPUSLP# 12
H_D#31 N24 R491 2 1 10K
H_D#32 D31# H_TEST1
AA23 D32# TEST1 C26
H_D#33 AB24 D25 H_TEST2
H_D#34 D33# TEST2 D11
V24 D34#
H_D#35 V26 AE6 PSI# H_PROCHOT_S# A C
la
D35# PSI# PSI# 25 +V3.3S H_PROCHOT#_EC 22
H_D#36 W25 E5 H_DPRSTP#
H_D#37 D36# DPRSTP#
H_D#38
U23
U25
D37#
B22 BSEL0 BAT54
C modify
D38# BSEL0 BSEL0 5
1
H_D#39 U22 B23 BSEL1
D39# BSEL1 BSEL1 5,10,22
.
H_D#40 AB25 C21 BSEL2 R37
D40# BSEL2 BSEL2 10
H_D#41 W22
H_D#42 D41# GTL_REF0 220R/0603
Y23 D42# GTLREF AD26
H_D#43 AA26 U3
H_D#44 D43#
2
Y26 D44#
H_D#45 Y22 Z0301 1 8 SMB_CLK_CPU
D45# VDD SCLK SMB_CLK_CPU 22
w
H_D#46 AC26 7 SMB_DATA_CPU
D46# SDATA SMB_DATA_CPU 22
H_D#47 AA24 H_THERMDA 2
H_D#48 D47# D+ PM_THRM_CPU#
AC22 D48# 3 D- THERM 4 PM_THRM_CPU# 4
H_D#49 AC23 H23 C28
D49# DSTBN0# H_DSTBN#0 5
H_D#50 AB22 G22 2 1 5 6 THRM_ALERT#
D50# DSTBP0# H_DSTBP#0 5 GND ALERT
H_D#51 AA21 M24
D51# DSTBN1# H_DSTBN#1 5
1
1
H_D#52 AB21 N25 2200P C24 C23
w
D52# DSTBP1# H_DSTBP#1 5
H_D#53 AC25 W24 H_THERMDC ADM1032
1 D53# DSTBN2# H_DSTBN#2 5 1
H_D#54 AD20 Y25 68P 68P
D54# DSTBP2# H_DSTBP#2 5
H_D#55
2
2
AE22 D55# DSTBN3# AD23 H_DSTBN#3 5
H_D#56 AF23 AE24
D56# DSTBP3# H_DSTBP#3 5
H_D#57 AD24 D57#
1
H_D#58 AE21 Route H_THERMDA/C on same layer. C27
w
H_D#59 D58#
AD21 D59# DINV0# J26 H_DINV#0 5
H_D#60 AE25 M26 H_DINV#1 5
10 mil trace 0.1U
H_D#61 D60# DINV1#
2
AF25 D61# DINV2# V23 H_DINV#2 5 10 mil spaceing
H_D#62 AF22 AC20
D62# DINV3# H_DINV#3 5
H_D#63 AF26 D63#
F_PZ47823-2743-01
SCOKET_M479_u-FCPGA
A B C D
A B C D E
m
+VCC_CORE +VCC_CORE +VCC_CORE
+VCC_CORE
o
C59 1 2 0.1U C37 1 2 10U/6.3V/X5R C43 1 2 10U/6.3V/X5R C46 1 2 10U/6.3V/X5R
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