Service Manuals, User Guides, Schematic Diagrams or docs for : FUJITSU-SIEMENS Fujitsu-Siemens Amilo Pa2515 - 37GL53010-C1
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5 4 3 2 1
Model : L53II0 PCB P/N:37GL53010-C1
PCBA P/N:82GL53010-C1
D D
Intel Merom CPU + 965GM + ICH8-M Chipset
L53II0 M/B and Daughter P/N LIST: L53II0 M/B Affiliated FFC/Cable P/N LIST:
82GL53010-C1 MAIN BOARD ASSY L53II0 REV.C1 80G2L7020-C0 AUDIO BD ASSY FOR L50II REV:C
PG01 INDEX 37GL53010-C1 PCB MAIN BD FOR L53II0 REV:C1
PG02 SYSTEM BLOCK DIAGRAM 80G2L7020-C0 AUDIO BD ASSY FOR L50II REV:C
1st
2nd
29GL50041-00
29GL50041-10
FFC AUDIO L50 HB
FFC AUDIO L50 JH
To
Mother
35G2L5020-C0 PCB AUDIO BD FOR L50II0 REV:C
PG03 POWER DIAGRAM & SEQUENCE 3rd 29GL50041-20 FFC AUDIO L50 HF board
80G8L5000-C0 TOUCHPAD BD FOR L50RI0 REV:C
PG04 GPIO & POWER CONSUMPTION 35G8L5000-C0 PCB TOUCHPAD BD FOR L50RI0 REV:C
1st
2nd
29GL50080-00
29GL50085-00
CABLE SPK 4 OHM 28N04E2 L50 FG To
CABLE SPK HB28C 4O1.5W M.S. board
Audio
PG05 CPU Merom-1/2 80G9L5000-C0 MODEM BD FOR L50RI0 REV:C
35G9L5000-C0 PCB MODEM BD FOR L50RI0 REV:C
PG06 CPU Merom-2/2 80G5L5000-C0 SWITCH BD FOR L50RI0 REV:C
80G8L5000-C0 TOUCHPAD BD FOR L50RI0 R:C
PG07 CLOCK GEN ICS 9LPRS365 35G5L5000-C0 PCB SWITCH BD FOR L50RI0 REV:C 1st 29GL50040-00 FFC BT MB L50 HB To
Mother
2nd 29GL50040-10 FFC BT MB L50 JH
80GPL5000-C0 ODD BD FOR L50RI0 REV:C
PG08 NB HOST -1/5 35GPL5000-C0 PCB ODD BD FOR L50RIO REV:C
3rd 29GL50040-20 FFC BT MB L50 HF board
C PG09 NB VGA_PCIEXPR-2/5 80GJL5100-B0 3G BD FOR L50AI0 REV:B0
1st
2nd
29GL50043-00
29GL50043-10
FFC TP BT L50 HB
FFC TP BT L50 JH
To
Mouse
C
35GJL5100-B0 PCB 3G BD FOR L50AIO REV:B0
PG10 NB DDR_MEM SYSTEM-3/5 3rd 29GL50043-20 FFC TP BT L50 HF board
80GYL5310-A0 IR BD FOR L50IIX REV:A
PG11 NB POWER-4/5 35GYL5310-A0 PCB IR BD FOR L53IIX VER:A
80G9L5000-C0 MODEM BD FOR L50RI0 R:C
PG12 NB VSS_NCTF-5/5
1st 29GL50082-00 CABLE MDC L50 HL To
PG13 DDR2 SODIMM PCB STACK UP 2nd 29GL50082-10 CABLE MDC L50 CMI Mother
3rd 29GL50082-20 CABLE MDC L50 FVC board
PG14 Terminatation / SMP-II
PG15 LCD&S-VDIO&CRT&WEBCAM&BLUET LAYER1:TOP
LAYER2:GND
80GPL5000-C0 SWITCH BD ASSY L50RI0 VER.C
PG16 ICH8-CPU/STAT/IDE -1/3 LAYER3:IN1
1st 29GL50042-00 FFC SWITCH L50 HB To
LAYER4:IN2 Mother
2nd 29GL50042-10 FFC SWITCH L50 JH
PG17 ICH8-IO/GPIO/USB/SYS -2/3 LAYER5:GND1
3rd 29GL50042-20 FFC SWITCH L50 HF board
LAYER6:IN3
PG18 ICH8-POWER -3/3 LAYER7:VCC
LAYER8:BOT 80GJL5100-B0 3G BD FOR L50AI0 REV:B0
PG19 Mini card/ODD/SATA Con/FAN
1st 29GL51083-10 CABLE FOR 3G BD HL L51AI/RI To
B PG20 GL827 Card Reader 2nd Mother
B
board
PG21 3G/DEBUG/NEW Card /USB Con 3rd
PG22 AUDIO/LED/SW BD/TP CON/BIOS 80GYL5310-A0 IR BD ASSY L53II0 VER.A
PG23 10_100M LAN RTL8101E 1st 29GL51083-10 To
PG24 EC-IT8512E Mother
board
PG25 SYSTEM POWER (MAX8734A)
PG26 1.5VS/1.05V/0.9V_DDR2 WEBCAM
PG27 GFX CORE ( OZ827) 1st To
Mother
PG28 CPU CORE(ISL6261) board
PG29 +1.8V(OZ811)
BLUETOOTH
PG30 BATT IN / Charger
1st To
A
PG31 VCC SW / VIN SW Mother A
board
PG32 Appendix A. Ver. History
ECS COMPUTER CORP.
Title
INDEX
Size Document Number Rev
C1
3774
Custom L53IIX
Date: Tuesday, February 27, 2007 Sheet 1 of 34
5 4 3 2 1
5 4 3 2 1
L53IIX
SYSTEM BLOCK DIAGRAM
D
CPU D
CRYSTAL Merom
14.318MHz Socket 478 THERMAL 5
EC
5,6 ADM1032
FSB BUS
Clock Gen DDR2 RAM BUS 667/800 MHZ
533/667MHZ
PCIE x16
ICS None use
North Bridge TVout S-Video 15
9LPR365
INTEL LVDS
SODIMM1 SODIMM0 Crestline LCD 15
7 +1.8V 13 +1.8V 13
8,9,10,11,12 TMDS&CRT
SMALL BOARD DMI CRT 15
AUDIO/LED BOARD IDE
Extended AZALIA CD-ROM 19
South Bridge
C PCIE x 1 RJ45 23 C
AUDIO CODEC USB INTEL RTL8101E CRYSTAL
MDC USB CONN x 2 ICH8-M 23 25M HZ Mini Card
ALC883
PCIE x 2
16,17,18 Mini Card19 USB x 2
RJ11
AMPLIFIER PCIE x 1
AMP6011 NEW CARD 21
HP JACK(SPDIF)*1
USB x 10 USBX1
3G module
21
INTERAL SPK
1.5W x 2
CRYSTAL
22
USB CONN x 1 Buletooth WEB CAM USB x 1
21 15 15
32.768K
CRYSTAL GL827 USB x 1 USB x 1 USB x 1
12 MHz
RTC
20
LPC BUS
B
Debug B
CONN 21
SMBus Diagram
CARD READER 20
SB_SMB_DATA
MMC/SD/MS/MS-PRO SATA x 1 SB_SMB_CLK
2.5" SATA HDD South DDR DIMM
CRYSTAL Bridge 13
19
32.768K 16,17,18
EC Mini Card
19
SPI
K/B CONTROLLER
ITE8512 24
BATTERY 30
FLASH ROM 24
CIR 15 Thermal Sensor for CPU
EC_SDATA_THM 5
EC_SCLK_THM
EC
Clock Gen
A
SW/BD INT K/B T/P FAN CHARGER BATTERY
22 24 22 19 30 30
24 SMB_DATA_EC_GEN
SMB_CLK_EC_GEN
7
A
ECS COMPUTER CORP.
Title
SYSTEM BLOCK DIAGRAM
Size Document Number Rev
C1
3774
Custom L53IIX
Date: Tuesday, February 27, 2007 Sheet 2 of 34
5 4 3 2 1
5 4 3 2 1
POWER BLOCK DIAGRAM
VID0
VID1 VIN
D
VID2 +1.8V APL5912 +1.25VS/3A
D
ISL6262A
VID3 RQW200N03 &
VID4
RQW103N03 +CPU_CORE/35A
+1.8V EU7171 +0.9V/2A
VID5
VID6
Signal +*VA +*V +*VS CLOCKs
State
VID0 VIN GFX_CORE/8A
S0(FULL ON)/M0 ON ON ON ON
VID1 S3(Suspend to RAM)/M1 ON ON OFF ON
S4(Suspend to DISK)/M1 ON ON OFF ON
VID2 AO4468 S5(Soft OFF)/M1 ON ON OFF ON
OZ827
VID3
VID4
C C
VIN +5VA/8A/PK 10A
AO4468 PL1 AO4468 +5V/1A
AO4468 +5VS/7.5A
MAX8744 VIN
+CPU_CORE PWM
VIN +3.3VA/6A/PK 8A +3.3V/2A ISL6261 27
+3.3VA
+CPU_CORE /35A +3.3VS/7A
MOSFET SW 31
PGD_IN
AO4468 AO4468 +3.3VS_ON
+3.3VA +3.3V +1.5V/0.25A
Power PWM IC +3.3V/5A LDO
GFX_CORE PWM MOSFET SW 31 31
AO4468 +3.3VS/7A Power SW Mosfet ISL6263 27
+1.5V /0.25A
Power Regulator GFX_CORE/8A +3.3V_ON
follow +3.3V up
Power Input GFX_VR_EN +5VA
B +5VS/7.5A B
MOSFET SW 31
VADAP
DC-JACK All_AUX PWM +5VS_ON
VIN +1.5VS/4A 30 MAX8734A 25
+5VA
+3.3VA/6A +5V
+5VA /8A/PK10A MOSFET SW 31
+12VA/0.1A
VADAP
CHARGER follow VIN up +5V_ON
AO4468 TL594C 30
+12VA
+12VS
ISL6227 MOSFET SW 31
VBAT +1.5VS/+1.05VS PWM +3.3VS_ON
VIN +1.05VS/9A BATTERY ISL6227CA
30 26
+1.5VS /4A,+1.05VS/9A
+1.5VS_ON/+1.05VS_ON
AO4468 +1.8V
+1.8V_DDR PWM +1.25VS LDO
OZ811 28 APL5912 26
+1.8V/8A/PK10A +1.25VS /3A
VIN 1.8V/8A/PK 10A DDR_V_SW# +1.25VS_ON
+0.9V LDO
EUP7171 26
AO4468
A +0.9V/2A A
follow +1.8V up
OZ8811
ECS COMPUTER CORP.
Title
POWER DIAGRAM
Size Document Number Rev
C1
3774
Custom L53IIX
Date: Tuesday, February 27, 2007 Sheet 3 of 34
5 4 3 2 1
5 4 3 2 1
1. CFG_0 ~ CFG_2 Host clock frequency initial
ICH8-M ITE8512E GPIO ITE8512E GPIO ITE8512E Merom CPU
GPIO Pin Definition list Pin Definition list GND CFG0 CFG1 CFG2 Host Clock
GPIO0 PM_BM_BUSY# GPA0 BTL_BEEP DAC0/GPJ0 BRIGHTNESS AVSS EC-AVSS-75 Frequency CPU CORE(V) ICC(A) W TEMP()
GPIO1 EC_EXTSMI# GPA1 RF_OFF# DAC0/GPJ1 CHG_I VSS0 GND IMVP-6+ 1.25 44.0 46.2
0 1 0 800
GPIO2 INT_PIRQE# GPA2 EC_VID2 DAC0/GPJ2 FAN_CTRL0 VSS1 GND
GPIO3 INT_PIRQF# GPA3 EC_VID3 DAC0/GPJ3 CHG_ON VSS2 GND 1 1 0 667
GPIO4 INT_PIRQG# GPA4 EC_VID4 DAC0/GPJ4 SENBAT_V VSS3 GND 2. CFG5 DMIx2 selection
GPIO5 INT_PIRQH# GPA5 EC_VID5 DAC0/GPJ5 CHG_V VSS4 GND
GPIO6 BIOS_REC GPA6 SMP_100MV_EN# VSS5 GND DMIx2 selction
D D
GPIO7 NC GPA7 SMP_50MV_EN# VSS6 GND Low = DMI*2
ITE8512E CFG5 High = DMI*4
GPIO8 BT_ON GPB0 LED_PWR KB Matrlk interface (default)
GPIO9 WOL_EN Pull low 100k GPB1 +3.3V_ON KSI0/STB# KB_SIN0
KSI1/AFD#
965-GM
GPIO10 Pull high 8.2k GPB2 LED_RF KB_SIN1 GPIO 3. CFG_9 PCIe Lane
GPIO11 SMB_ALERT# GPB3 SMB_CLK_BAT KSI0/STB# KB_SIN2 GPIO0 MCH_BSEL0 PCIe Lane
GPIO12 LAN_PHYPC GPB4 SMB_DATA_BAT KSI3SLIN# KB_SIN3 GPIO1 MCH_BSEL1 Low = Reverse Lane
GPIO13 GPB5 H_A20GATE KSI4 KB_SIN4 GPIO2 MCH_BSEL2
NC CFG9
(default)
Crestline
GPIO14 GPB6 H_RCIN# KSI5 KB_SIN5 GPIO3 High = Normal
Pull high 8.2k N.C
KSI6
VCC ICC(mA) W TEMP()
GPIO15 PM_STPPCI# GPB7 MUTE_AMP# KB_SIN6 GPIO4 N.C CFG[17:3] have internal pullup ressistors.
KSI7
+3.3VS 340 1.122
GPIO16 PM_DPRSLPVR GPC0 IR_RX KB_SIN7 GPIO5 CFG5(DMIx2 selction)
KSO0/PD0 4. CFG_12 ~ CFG_13
+1.8V 3800 6.84
GPIO17 NC GPC1 SMB_CLK_EC_GEN KB_SOUT0 GPIO6 N.C
KSO1/PD1 XOR / ALLZ / Clock Un-gating
+1.5VS 130 0.195
GPIO18 GPIO18 GPC2 SMB_DATA_EC_GEN KB_SOUT1 GPIO7 N.C 105
KSO2/PD2 CFG12 CFG13 Configuration
+1.25VS 2440 3.05
GPIO19 SATA1GP GPC3 SMP2_EN# KB_SOUT2 GPIO8 N.C
KSO2/PD3
+1.05VS 4140 4.347
GPIO20 GPIO20 GPC4 PWR_KEEP KB_SOUT3 GPIO9 CFG9(PCIe Lane) 0 0 Clock Gating Disabled
KSO2/PD4 0 1 XOR Mode Enabled
+0.9V 30 0.27
GPIO21 SATA0GP GPC5 EC_SKIP KB_SOUT4 GPIO10 N.C
KSO2/PD5 1 0 All-Z Mode Enabled
GFX_CORE 7700 8.085
GPIO22 NC GPC6 SB-PWRBTN# KB_SOUT5 GPIO11 N.C
GPIO23 GPC7 DDR_V_SW# KSO2/PD6 KB_SOUT6 GPIO12 CFG12(XOR / ALLZ / Clock 1 1 Normal Operation (Default)
N.C Un-gating)
GPIO24 CRB_SV_DET GPD0 AC_IN KSO2/PD7 KB_SOUT7 GPIO13 CFG13(XOR / ALLZ / Clock
Un-gating) 5. CFG_16 FSB Dynamic ODT
GPIO25 PM_STPCPU# GPD1 H_PROCHOT_EC# KSO8/ACK# KB_SOUT8 GPIO14 N.C ICH8-M
C
GPIO26 PM_SLP_S4_STATE# GPD2 PLT_RST# KSO9/BUSY KB_SOUT9 GPIO15 N.C FSB Dynamic ODT VCC ICC(mA) mW TEMP() C
GPIO27 KSO10/PE CFG16(FSB Dynamic ODT)
N.C(QRT_STATE0) GPD3 ECSCI# KB_SOUT10 GPIO16 Low = Dynamic ODT Disabled
+5V 2 10
GPIO28 KSO11/ERR# CFG16
N.C(QRT_STATE1) GPD4 3G_ON KB_SOUT11 GPIO17 N.C High = Dynamic ODT
+5VS 1 5
GPIO29 USB_OC#5 GPD5 EC_GPCF3 KSO12/SLCT KB_SOUT12 GPIO18 CFG18(NAPA design) Enabled(default) +3.3VA 230 756
KSO13
70
GPIO30 USB_OC#6 GPD6 FAN_SPEED# KB_SOUT13 GPIO19 CFG19(DMI lane Reversal) 6. CFG_18 NAPA design
+3.3VS 330 1089
GPIO31 USB_OC#7 GPD7 RF_SW_ON# KSO14 KB_SOUT14 GPIO20 CFG20(SDVO/PCIE Concurrent +1.5VS 2400 3600
Operation)
GPIO32 PM_CLKRUN# GPE0 PM_RSMRST# KSO15 KB_SOUT15 +1.25V 5 6.25
CFG18 Low = 1.05V
GPIO33 HDA_DOCK_EN# GPE1 PM_PWROK_SB (VCC Select) High = 1.5V
+1.05V 1131 1187.55
GPIO34 N.C GPE2 PGD_IN ITE8512E SPI
GPIO35 CLK_SATA_OE# GPE3 INTERNET# Flash ROM interface
FLFRAME#/GPG2 FLFRAME# NAPA design
GPIO36 SATA2GP GPE4 PWR_SW FLAD0/SCE# ITE8512E
SPI_CE#
GPIO37 SATA3GP GPE5 CHR_R FLAD1/S1 SPI_DIN 7. CFG_19 DMI lane Reversal VCC ICC(mA) W TEMP()
GPIO38 ODD_DET GPE6 CHR_G FLAD2/S2 SPI_DOUT DMI lane Reversal
+3.3VA 300 1 70
GPIO39 ICH_GPIO39 GPE7 NEWCARD_PWRON FLAD3/GPG6
GPIO40
N.C 0 = normal
USB_OC#1 GPF0 SILENT_ON# FLCLK/SCK SPI_CLK CFG19
(default)
GPIO41 USB_OC#2 GPF1 LED_CAP FLRST#/WU17 1 = Reversed
GPIO42 /GPG0/TM N.C
USB_OC#3 GPF2 LED_NUM CLOCK GENERATOR
GPIO43 USB_OC#4 GPF3 SILENT_LED ITE8512E 8. CFG_20 SDVO/PCIE Concurrent operation
VCC ICC(mA) mW TEMP()
GPIO48 MFG_MODE GPF4 PS2_CLK_TP System & LPC Bus +3.3VS 270 891 70
GPIO49 H_PWRGD GPF5 PS2_DATA_TP LAD0 LPC_AD0 CFG20
B GPIO50 PCI_REQ#1 GPF6 NEWCARD_PERST# LAD1 LPC_AD1 (SDVO/PCIE Concurrent Operation)
B
GPIO51 PCI_GNT#1 GPF7 NEWCARD_CPPE# LAD2 LPC_AD2
GPIO52 PCI_REQ#2 GPH0 +CPU_CORE_ON LAD3 LPC_AD3 0 = Only SDVO or PCIE x1 is operational (default) ADM1032
GPIO53 PCI_GNT#2 GPH1 +1.05VS_ON SERIRQ INT_SERIRQ 1 = SDVO and PCIE x1 are operating simultaneously VCC ICC mW TEMP()
via the PEG port
GPIO54 PCI_REQ#3 GPH2 +1.5VS_ON LFRAME# LPC_FRAME# +3.3VS 170uA 0.56 150
GPIO55 PCI_GNT#3 GPH3 +3.3VS_ON LPCCLK CLK_PCI_LPC
GPIO(44 GPH4 +5VS_ON WRST# LRST#
NA INT-PIRQA# :NC
~ 47 ) GPH5 +1.8V_ON INT-PIRQB# :NC
ITE8512E INT-PIRQC# :NC
GL827
GPH6 +1.25VS_ON
Clock INT-PIRQD# :NC VCC ICC(mA) mW TEMP()
GPG1 +5V_ON
ADC0/GPI0 CK32K EC32KI +5VS 170 561
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