Service Manuals, User Guides, Schematic Diagrams or docs for : FUJITSU-SIEMENS Fujitsu-Siemens Amilo Pro V2035 - FIC LM7W - REV 0.2
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5 4 3 2 1
First International Computer,Inc
D D
Protable Computer Group HW Department
Board name : Mother Board Schematic 1. Schematic Page Description :
Project : LM7W 2. PCI & IRQ & DMA Description :
C
Version : 0.2 3. Block Diagram : C
4. Nat name Description :
Initial Date : August 31 , 2005
5. Board Stack up Description :
6. Schematic modify Item and History :
7. power on & off & S3 Sequence :
8. Layout Guideline :
9. switch setting
B B
Manager Sign by:
Drawing by : Tom_Lin
Total confirm by: CC_TSAO
A
LAN Circuit check by: A
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
Audio Circuit check by: Title
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-875 1
LM7W < VIA VN800 + VT8237R >
Size Document Number Rev
C <> 0.2
Date: Monday, November 14, 2005 Sheet 1 of 55
5 4 3 2 1
8 7 6 5 4 3 2 1
1. Schematic Page Description :
LM7 Schematic Ver : 0.1
D
1. Title 23. VT8237 (1/3) 45. 1.5VDDA/S , 1.8/2.5VDDM/A D
2. Schematic Page Description 24. VT8237 (2/3) 46. 3VDDM / 5VDDM
3. Block Diagram 25. VT8237 (3/3) 47. VCCP/1.5VDDM
4. ANNOTATIONS 26. Power Good & Fan Controller 48. 3VDDA / 5VDDA / PMU3/5V
5. Schematic Modify 27. CB1410 CardBus Controller 49. POW-ON Controller
6. Timing Diagram 28. CB1410 CardBus Power SW./CNN 50. ADIN / Battery CNN
7. DDR Layout Guideline 29. MINI PCI 51. Charge Circuit / DCIN
8. Banias Celeron(1/2) 30. VT6103L PHY 52. Inverter Controller
9. Banias Celeron(2/2) 31. USB CNN 53. Audio board
10. POWER (CPU CORE) 32. S-ATA HD / CD-ROM CNN 54. Switch transfer board
11. Thermal / VR_PWRGD / RTC 33. LPC PMU08 55. Update list
12. Clock Generator 34. LPC KBC M3885X
13. Clock Buffer 35. INT KBC / GP Connector
C C
14. VN800 (1/4) 36. MDC Connector
15. VN800 (2/4) 37. DIP Switch & LED
16. VN800 (3/4) 38. Firm Ware Hub / LID Switch
17. VN800 (4/4) 39. Reset Circuit
18. DDR SO-DIMM1 40. OVP / SCREW
19. DDR SO-DIMM0 41. ALC655 Audio Codec
20. VT1631 LVDS Transmitter 42. G1432+1410 Audio Amplifier
21. LCD Connector 43. H.P. Out / Audio CNN
22. CRT Connector 44. DDR PWR
B
2. PCI & IRQ & DMA Description : B
IDSEL CHIP IRQ Channel Desciption DMA Channel Device
IRQ0 System timer DMA0 FIR (disable by default) (MODEM / LAN)
AD17 Mini PCI(Wireless LAN)
IRQ1 Keyboard DMA1 ECP
AD23 CardBus
IRQ2 (Casacde) DMA2 FLOPPY DISK
IRQ3 LAN / MODEM DMA3 AUDIO
IRQ4 Serial Port DMA4 (Cascade)
IRQ5 AUDIO / VGA / USB DMA5 Unused
IRQ6 FLOPPY DISK DMA6 Unused
IRQ7 LPT DMA7 Unused
PCIINT CHIP
IRQ8 RTC
IRQA MiniPCI/NB IRQ9 ACPI
IRQB MiniPCI/CardBus IRQ10 FIR (Disable by default) (MODEM/LAN)
IRQC MiniPCI IRQ11 Cardbus
IRQD IRQ12 PS/2 mouse
IRQ13 FPU
IRQ14 HDD
BUSMASTER
IRQ15 CDROM
REQ CHIP
A
REQ0 / GNT0 MiniPCI A
REQ1 / GNT1 CardBus
REQ2 / GNT2 Mini PCI(Wireless LAN)
REQ3 / GNT3 First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
REQ4 / GNT4 114 TAIPEI, TAIWAN ,ROC
(886-2)8751-875 1
Title
LM7W < VIA VN800 + VT8237R >
Size Document Number Rev
C <> 0.2
Date: Monday, November 14, 2005 Sheet 2 of 55
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3. Block Diagram : CLK ICS952906BF
P12
CLK Buffer
P13
D Thermal Intel CPU
CORE
D
Sensor DDR Pull up
P10
GMT G795 P11 Celeron-M P18,P19
CPU
Processor LID/DIP SW
VCCP
P8,9 P38,37
P49
Host Bus MAIN SW CNN
P35
DDR2 400/533
INTERFACE
VIA P18,P19
VN800
CRT P22 567 HSBGA Mem Bus
C
VT1631 P14~P17 C
LCD P21 LVDS Tx
P20
Hub Interface
Audio
AMP
LAN Phy IDE BUS CDROM AC'97 P42
MII BUS P32
RJ-45 P30 VT6103L VT8237 CODEC
P30 S-ATA HDD ALC655 HEADPHONE
P41
ACIN 539 BGA P32
USB 2.0
P46 Mic IN
P23~P25 MDC CNN
P36
3VDDA/5VDDA PMU3V/5V USB2,3 USB0,1 P31 AC-Link Audio EXT
P48 board
B
Audio EXT B
3VDDS/5VDDS board 32Bit PCI BUS
P46
LPC BUS
3VDDM/5VDDM
P46
1.8VDDS/DDM Mini PCI
P44 FLASH ROM LPC
K/B CTRL
DDR 0.9VDDM
P29 ( F/W Hub) PMU08
P44 LPC M3885X
VCCP/1.5VDDM P34
4M P38
P33
P47
Over Voltage
P48 Protect
P40 PCMCIA INT K/B P35 GP P35
Battery ENE FAN CNN
charger P51 PCMCIA SLOT0
CB1410 P11
Battery Select Ver:B0 P28
A A
P50 P27
BAT CON
RTC P11
P50 First International Computer, Inc.
CP2211 2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Battery Voltage (886-2)8751-875 1
sense
P33
P28
RESET Title
P39 LM7W < VIA VN800 + VT8237R >
Size Document Number Rev
C <> 0.2
Date: Monday, November 14, 2005 Sheet 3 of 55
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
4. Nat name Description : 5.Board Stack up Description
Voltage Rails PCB Layers
DCIN Primary DC system power supply Layer 1 Component Side, Microstrip signal Layer
D
PMU5V 5.0V always on power rail by LATCH or ACIN Layer 2 Ground Plane D
PMU3V 3.3V always on power rail by LATCH or ACIN
5VDDA 5.0V always on power rail by DCON or PSUSC0 Layer 3 Stripline Layer(AGTL,CLOCK,DDR)
3VDDA 3.3V always on power rail by DCON or PSUSC0 Layer 4 Power Plane
3VDDS 3.3V power rail
5VDDS 5.0V power rail Layer 5 Ground Plane
3VDDM 3.3V switched power rail Layer 6 Stripline Layer(Analog,LVDS,other)
5VDDM 5.0V switched power rail
Vcore_CPU Core Voltage for CPU Layer 7 Ground Plane
Layer 8 Solder Side,Microstrip signal Layer
VCCP 1.05V for AGTL+ Termination Voltage
1.8VDDM 1.8V for CPU PLL Voltage
DDR_0.9VDDM 0.9V DDR Termination Voltage
1.5VDDM 1.5V switched power rail
1.5VDDS 1.5V power rail
1.5VDDA 1.5V always on power rail
2.5VDDS 2.5V power rail for DDR
C C
Part Naming Conventions
C = Capacitor
CN = Connector
D = Diode
F = Fuse
L = Inductor
Q = Transistor
R = Resistor
B
RP = Resistor Pack B
U = Arbitrary Logic Device
Y = Crystal and Osc
Net Name Suffix
0 = Active Low signal
Signal Conditioning
_D_ = Damped (by a resistor)
_Q_ = Isolated (by a Q-switch)
_L_ = Filtered (by an inductor or bead)
A A
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-875 1
Title
LM7W < VIA VN800 + VT8237R >
Size Document Number Rev
C <> 0.2
Date: Monday, November 14, 2005 Sheet 4 of 55
8 7 6 5 4 3 2 1
5 4 3 2 1
6.Schematic modify Item and History :
D D
C C
B B
A A
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8 751
Title
LM7W < VIA VN800 + VT8237R >
Size Document Number Rev
C <> 0.2
Date: Monday, November 14, 2005 Sheet 5 of 55
5 4 3 2 1
5 4 3 2 1
7. power on & off & S3 Sequence :
D Power On Sequencing Timing Diagram D
VID
VR_ON Tsft_star_vcc
Vboot Vid
Vcc-core Tboot
Tboot-vid-tr
CPU_UP Tcpu_up
Vccp
Vccp_UP Tvccp_up
Vccgmch
GMCHPWRGD Tgmch_pwrgd
CLK_ENABLE#
IMVP4_PWRGD Tcpu_pwrgd
C C
BATTERY ONLY POWER ON TIMING S3 SUSPEND AND RESUME TIMING
POWSW0
POWSW0
PMU5V/PMU3V
PMU5V/PMU3V H
DCON DCON H
VDDA H
VDDA
PM_RSMRST0 H To ICH4_M
MAINSW0_ICH To ICH4
PM_SLP_S30 From ICH4_M
To ICH4
PM_RSTRST0 PM_SLP_S40/S50 H From ICH4_M
From ICH4
PSUSC0 H From ASIC_B0
PM_SLP_S30/S40/S50
SUSTAT_B0 From ASIC_B0
From ASIC_B0
PSUSC0
From ASIC_B0
VDDS H
SUSTAT_B0
B
VDDM B
VDDM,VDDS
PM_PWROK 1.5VDDS AND
DDR_PWRGD
PM_PWROK SYS_PWROK
VRON_VCCP
SYS_PWROK
VCCP,1.2VDDM
VRON_VCCP
VCORE_ON
VCCP/1.2VDDM
VR_ON
VCORE_ON
VR_ON VCORE_CPU
VCORE_CPU
CK408_PWRGD0
CK408_PWRGD0 To clock Generator
To clock generator PM_VGATE ToICH4 and ODEM
To ODEM and ICH4
PM_VGATE CPU_PWRGOOD From ICH4 to CPU
From ICH4 to CPU
CPU_PWRGD PCI_RST0 To ODEM/other
PCI_RST0 PCI device
To ODEM/other PCI device AGTL+_CPURST0 From ODEM to CPU
AGTL+_CPURST0
A From ODEM to CPU A
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-875 1
Title
LM7W < VIA VN800 + VT8237R >
Size Document Number Rev
C <> 0.2
Date: Monday, November 14, 2005 Sheet 6 of 55
5 4 3 2 1
5 4 3 2 1
8. Layout Guideline :
Montara-GM DDR Layout Guidelines
Note that all length matching formulas are based on GMCH die-pad to SO-DIMM pin total length CLOCKS LENGTH TRACE / SPACE NOTES
1. Differentials pairs with
D
DDR Signal Groups Length Matching Formulas HCLKCPU[1..0]
5 / 20 mils
the same length
(within 10 mil) D
HCLKNB[1..0] 2" ~ 8 " (5 mil space 2.CPU & NB trace
Group Signal Name Signal Group Minimum Length Maximum Length between + & - ) mismatch within
HCLKITP[1..0] 450 mil
Clocks SCK[5:0] Control to Clock Clock - 1.0" Clock + 0.5"
SCK#[5:0] * 66MCLK_ICH &
Command to Clock Clock - 1.0" Clock + 2.0" 66MCLK_ICH AGPCLK_GMCH
Data SDQ[71:0] 4.5" ~ 9.0 " AGPCLK_ATI
SDQS[8:0] CPC to Clock Clock - 1.0" Clock + 0.5" 66MCLK_GMCH 5 / 20 mils Length mismatch
SDM[8:0] within 100 mils
Strobe to Clock Clock - 1.0" Clock + 0.5" AGPCLK_ATI MAX : 8.5"
Control SCKE[3:0]
SCS#[3:0] Data to Strobe Strobe - 25 mils Strobe + 25 mils
PCLKICH 1.Making PCI length with
Command SMA[12:6,3:0] minimum various
SBA[1:0] PCLKCB
SRAS# 2.Max skew = 1ns
SCAS# PCLK1394
SWE#
PCLKUSB20 4.5"~9.0" 5 / 20 mils
CPC SMA[5,4,2,1]
SMAB[5,4,2,1] PCLKOP
Feedback RCVENOUT# PCLKFWH
RCVENIN#
PCLKSIO
PCLKLAN
Clock Signals Topologies and Routing Guidelines 14MCLK_SIO
14MCLK_ICH 4.5"~9.0" 5 / 10 mils
SO-DIMM PADS 7 mil trace, 4 mil pair space 14MCLK_AC97
Clock length tolerenve within the pair : +/- 10 mil
Clock to Clock Length Matching : +/- 25 mils
Minimum Pair to Pair Spacing : 20 mils 48MCLK_ICH
C GMCH Minimum Spacing to other Signals : 20 mils 3.5" ~ 12.5" 5 / 20 mils C
Pin 48MCLK_CB
P1 L1
Min:0.5"
Package Length Max:5.0"
Range
Data Signals Topologies and Routing Guidelines SDQ/SDM to SDQS Mapping
Signal Mask Relative To Mismatching
SDQ[7..0] SDM[0] SDQS[0] +/- 25 mil
Minimun Spacing to Trace Width Ratio, SDQ/SDM : 2 to 1
SDQS : 3 to1 SDQ[15..8] SDM[1] SDQS[1] +/- 25 mil
L1 L2 L3 L4 Minimum Spacing to other Signals : 20 mils
GMCH SDQ[23..16] SDM[2] SDQS[2] +/- 25 mil
Pin Trace Length L1 : Min 0.5" , Max 3.75"
56 ohm 5% L2 : Max 0.75" SDQ[31..24] SDM[3] SDQS[3] +/- 25 mil
P1 L3 : Min 0.25" , Max 1.0"
L4 : Max 1.0 " SDQ[39..32] SDM[4] SDQS[4] +/- 25 mil
Package Length
Range Length Matching : SDQS to SCK/SCK# SDQ[56..40] SDM[5] SDQS[5] +/- 25 mil
SDQS , SODIMM0 P1+L1+L2
SDQS , SODIMM1 P1+L1+L2+L3 SDQ[55..48] SDM[6] SDQS[6] +/- 25 mil
Min : Clock - 1.0" , Max : Clock + 0.5"
SO-DIMM0 SO-DIMM1 SDQ/SDM to SDQS : +/- 25 mils SDQ[63..56] SDM[7] SDQS[7] +/- 25 mil
PADS PADS SDQ[71..64] SDM[8] SDQS[8] +/- 25 mil
B B
Control Signals Topologies and Routing Guidelines
Trace spacing to trace width ratio : 2 to 1
L1 L2 Minimum Spacing to other Signals : 20 mils
GMCH Trace Length L1 : Min 0.5" , Max 5.5"
Pin L2 : Max 2.0"
56 ohm 5%
P1 Length Matching : CTRL(P1+L1) to SCK/SCK#
Min : Clock - 1.0" , Max : Clock + 0.5"
Package Length
Range
CPC Signals Topologies and Routing Guidelines
SO-DIMM0,1 PADS Trace spacing to trace width ratio : 2 to 1
Minimum Spacing to other Signals : 20 mils
Trace Length L1 : Min 0.5" , Max 5.5"
L2 : Max 2.0"
L1 L2
GMCH Length Matching : CPC(P1+L1) to SCK/SCK#
Command Signals Topologies and Routing Guidelines Pin 56 ohm 5%
Min : Clock - 1.0" , Max : Clock + 0.5"
P1
Package Length
Trace spacing to trace width ratio : 2 to 1 Range
L1 L3 L4 Minimum Spacing to other Signals : 20 mils
GMCH Trace Length L1 : Min 0.5" , Max 4.0"
Pin L2 : Max 1.0" SO-DIMM0,1 PADS
56 ohm 5% L3 : Max 2.0"
P1 L2+L3 : Max 3.0"
10 ohm 5% L4 : Max 1.0"
A Package Length Length Matching : CMD to SCK/SCK# A
Range CMD , SODIMM0 P1+L1+L2
CMD , SODIMM1 P1+L1+L3
Min : Clock - 1.0" , Max : Clock + 2.0"
L2
SO-DIMM1
PADS First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-875 1
Title
SO-DIMM0
LM7W < VIA VN800 + VT8237R >
Size Document Number Rev
PADS C <> 0.2
Date: Monday, November 14, 2005 Sheet 7 of 55
5 4 3 2 1
A B C D E
System Bus Common Clock Signal Layout Guide :
AGTL+_HA0[31..3] AGTL+_HD0[63..0] 9,14,26,38,47 VCCP
14 AGTL+_HA0[31..3] AGTL+_HD0[63..0] 14 ADS# , BNR# , BPRI# , BR0# , DBSY# , DEFER# , DPWR# , DRDY# , HIT# , HITM# , LOCK# ,
U12-1 RS[2..0]# , TRDY# , RESET#.
AGTL+_HA03 H_A20M0 R551 150 5% 1/16W SMT0402 LR
Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)
P4 A3#
AGTL+_HA04 U4 A19 AGTL+_HD00 H_IGNNE0 R561 150 5% 1/16W SMT0402 LR Strip-line(Int. Layer) 1.0 ~ 6.5 inch 55+/-10% 4 & 8(Int. Layer)
AGTL+_HA05 A4# D0# AGTL+_HD01 H_INTR R552 150 5% 1/16W SMT0402 LR
V3 A5# D1# A25 Micro-strip(Ext. Layer) 5 & 10(Ext. Layer)
AGTL+_HA06 R3 A22 AGTL+_HD02 H_NMI R553 150 5% 1/16W SMT0402 LR
AGTL+_HA07 A6# D2# AGTL+_HD03 H_SMI0 R560 150 5% 1/16W SMT0402 LR
V2 A7# D3# B21
AGTL+_HA08 W1 A24 AGTL+_HD04 H_STPCLK0 R572 150 5% 1/16W SMT0402 LR
AGTL+_HA09 A8# D4# AGTL+_HD05 H_CPUSLP0 R569 150 5% 1/16W SMT0402 LR
T4 A9# D5# B26
Source Synchronous DATA :
Address Group0
AGTL+_HA010 W2 A21 AGTL+_HD06 CPU_DPSLP0 R574 150 5% 1/16W SMT0402 LR
AGTL+_HA011 A10# D6# AGTL+_HD07 H_INIT0 R563 150 5% 1/16W SMT0402 LR
Y4 B20 DATA#[63..0] , DINV#[3..0] , DSTBN#[3..0] , DSTBP#[3..0]
Data Group0
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