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5 4 3 2 1
CPU-LGA775
Note:
D Do not include the schematic D
when create netlist.
Host Bus
SiS661GX
AGP SLOT
AGP BUS /661FX DDR SDRAM
/648FX/ DIMM1
VGA AGP BUS
648C DIMM2
PCI Slot 1
C C
MuTIOL 1G
PCI Slot 2
LAN PHY
PCI Slot 3
AC'97
Audio Codec
SiS964/
IDE 1 964L
IDE 2
Back Panel Front Panel
KEYBOARD PS/2
B
SATAX2 USB 0 B
/MOUSE LPC Bus USB 4
USB 1 USB 5
FAN 1 USB 2 USB 6
FAN CONTROL USB 3 USB 7
FAN 2 VOLTAGE MONITOR
SPI Bus LPC Super I/O
SPI ROM
TEMPERATURE MONITOR
LPC Bus
LPC ROM
A A
IR PARALLEL COM FLOPPY
TECHNOLOGY COPR.
Title
Topology
Document Number Rev
661M08 A
Date: Monday, August 01, 2005 Sheet 1 of 44
5 4 3 2 1
5 4 3 2 1
Foxconn Precision Co. Inc.
661M08 Schematic
D
Fab.A D
Data: 2005/06/28
Page Index
00. Index Page 22. DECOUPLE & EMI
01. Topology 23. Termination
02. Rest Map 24. PCI 1&2
03. Clock Distribution 25. PCI3
04. Power Delivery Map 26. IDE CONN
C
05. LGA775-1 27. USB & LAN PORT C
06. LGA775-2 28. SI/O_ITE8712F/JX
07. Voltage regulator Down 10.1 29. K/B & MS CONN
08. Output CAP 30. COM/PRT/GAME PORT
09. 661FX-1 HOST & AGP 31. LPC/SPI BIOS_FLOPPY
10. 661FX-2 DDR 32. FAN
11. 661FX Mutiol & VGA 33. 653/655 AC97 CODEC
12. 661FX Power 34. AC97 I/O
B
13. 964/L-1 PCI/IDE/Link 35. LAN PHY AC131KML B
14. 964/L-2 PC/MIL/CPU/GPIO 36. Power BTN/RTC Batt
15. 964-3 USB/SATA 37. DDR 2.5V DDRVTT
16. 964-4 Power 38. Power CONN
17. 952017/18AF Clock GEN 39. SB3V, SB1.8V, VCC1.8V, VDDQ
18. DDR Clock Buffer 40. TI1394(NA)
19. AGP 41. USB
20. VGA CON 42. Modification
A 21. DIMM1 & DIMM2 43. Jumper Setting/Option Table A
FOXCONN PCEG
Title
Index Page
Size Document Number Rev
B 661M08 A
Date: Monday, August 01, 2005 Sheet 1 of 44
5 4 3 2 1
5 4 3 2 1
VCCP VCCP
Prescott
VRD10.1/VRM9.X
CPUPWRGD
D D
CPURST_
VRMPWRGD
&
PWOK
CPUPWRGD
NBPWRGD CPURST_
ATX
Power SiS648FX
NBRST_
C
PSON_ SiS661FX C
AGP 8X SLOT
SiS964/SiS964L
SBPWRGD PCI Slot 1
PCI Slot 2
NBRST_ PCI Slot 3
PCIRST_
Front Panel
PSON_
B IDE CONN 1 B
RSTSW_ SIORST_
IDE CONN 2
PWRBTN_
PWRBTN_
SIORST_ SIORST_
Super IO Media
8712F/JX Interface
A A
TECHNOLOGY COPR.
Title
Reset Map
Document Number Rev
661M08 A
Date: Monday, August 01, 2005 Sheet 2 of 44
5 4 3 2 1
14.318MHz
CPU
D D
CPUCLK0 100/133/200 MHz
100/133/200 MHz
CPUCLK1
66 MHz AGP 8x
DDR CLOCK BUFFER
AGPCLK1
133 MHz
DIMM 1-2
ZCLK0 SiS648FX
66 MHz FWDSDCLK0 DDRCLK
AGPCLK0
/661FX
CLOCK GENERATOR
C C
33 MHz
96XPCLK
133 MHz
ZCLK1
48 MHz
UCLK48M
TXCLK
SiS964/
REFCLK LAN PHY
964L RXCLK
33 MHz
PCICLK1-3 PCI Slot 1-3
B B
AUDIO_CLK
32.768KHz
AC'97
24.576MHz/NC
48 MHz
SIO48M Super I/O
A A
TECHNOLOGY COPR.
Title
Clock Distribution
Document Number Rev
661M08 A
Date: Monday, August 01, 2005 Sheet 3 of 44
5 4 3 2 1
5 4 3 2 1
DDR 2 DIMMS:
ATX VCC3
ATX SPS
12V > 2.5V
REGULATOR
VCC2.5_MEM
> 2.5V +/-100mv
P/S S3AUXSW- 6.00A
SB5V
5
V 5
3
.
+
1
-
1 +
1
> REGULATOR
S V 3 2 2
D
V V V 2 D
B VCC2.5_MEM
V
LGA775 DDR_VTT_STR DDR VTT
1.25V
+12V CORE_CPU_SYS
VCCP
> REGULATOR > 1.25V
> VRD 10.1 > 1.1V~1.85V 119A
VCC_VID
2A
1.2V 30mA
> MIC5258 VCCVID
> VCC3 SIS964
SIS648FX/ 661FX
VCC3_DUAL
> VCC3:
5V_DUAL VCC3: VCC1.8V > 3.3V
PWRG_ATX
> 3.3V
108mA
1.8V
1389.5mA
VCC1.8V
>
VCC3 VCCP VCC1.8V
> VCC3_DUAL VDDQ: SB3V
> VCC3_DUAL 1.8V
VCC3_DUAL AGP > OR VCC_RTC VCC_RTC
C SB5V
AIC1086
SB3V PWRG_ATX
> 33.4mA 1.5V 35.1/21.7mA 3 VOLTS
BATTERY > > RTCVDD VCCP
C
VCC2.5_MEM SB1.8V
VCC3 VCC1.8V
AIC1084
> 2.5V
501.3mA
1.8V
10mA
VCC3
CLK_GEN
> 3.3V
300mA
VCCP
VCC5_DUAL
5V_SYS > SUPER I/O
VCC5_DUAL
VCC3_DUAL > 5V
VCC3
VCC5 >
PCI PER SLOT:
3.3V 7.6A
> VCC3_DUAL
+12V > 5V 5.0A
-12V > 12V
-12V
0.5A
0.1A VCC5 FWH
VCC3_DUAL > 3.3Vaux
0.375A >
B
> B
VCC5 VCC5_DUAL USB POWER
PWRG_ATX
> 5V
SB5V VCC5_DUAL
VCC3_DUAL > PS2 KB/MS POWER
> LAN PHY 5V
+12V VCC5A
VCC3 VDDQ 1.5V
AUDIO
VREG > AC' 97 AUDIO CODEC
VCC3
AIC1084
> AGP
VCC3
>
A5V 70mA
3.3V 10mA
+12V
>
A VCC5
> A
VCC3_DUAL
>
> TECHNOLOGY COPR.
Title
Power Delivery Map
Document Number Rev
661M08 A
Date: Monday, August 01, 2005 Sheet 4 of 44
5 4 3 2 1
5 4 3 2 1
HAJ[31..3]
9 HAJ[31..3]
HDJ[63..0]
HDJ[63..0] 9
U33A
HAJ3 L5 D2
2 OF 7 HAJ4 A03# ADS# HADSJ 9
U33B P6 A04# BNR# C2 HBNRJ 9
HAJ5 M5 D4
HAJ6 A05# HIT# TP_RSPJ HITJ
TP1 9
L4 A06# RSP# H4
HDJ0 B4 G16 HDJ32 HAJ7 M4 G8
HDJ1 D00# D32# HDJ33 HAJ8 A07# BPRI# HBPRIJ 9
C5 D01# D33# E15 R4 A08# DBSY# B2 HDBSYJ 9
D HDJ2 A4 E16 HDJ34 HAJ9 T5 C1 D
HDJ3 D02# D34# HDJ35 HAJ10 A09# DRDY# HDRDYJ 9
C6 D03# D35# G18 U6 A10# HITM# E4 HITMJ 9
HDJ4 A5 G17 HDJ36 HAJ11 T4 AB2 HIERRJ
HDJ5 D04# D36# HDJ37 HAJ12 A11# IERR#
B6 D05# D37# F17 U5 A12# INIT# P3 INITJ 14
HDJ6 B7 F18 HDJ38 HAJ13 U4 C3
HDJ7 D06# D38# HDJ39 HAJ14 A13# LOCK# HLOCKJ 9
A7 D07# D39# E18 V5 A14# TRDY# E3 HTRDYJ 9
HDJ8 A10 E19 HDJ40 HAJ15 V4 AD3 TP_BINITJ TP2
HDJ9 D08# D40# HDJ41 HAJ16 A15# BINIT#
A11 D09# D41# F20 W5 A16# DEFER# G7 HDEFERJ 9
HDJ10 B10 E21 HDJ42 N4 F2 TP_EDRDYJ TP3
HDJ11 D10# D42# HDJ43 RSVD1 EDRDY# TP_MCERRJ TP4
C11 D11# D43# F21 9 HREQJ[4..0] P5 RSVD2 MCERR# AB3
HDJ12 D8 G21 HDJ44 HREQJ0 K4 GTLREF voltage should be 0.67*FSB_VTT
HDJ13 D12# D44# HDJ45 HREQJ1 REQ0# TP_APJ0 TP5 12 mils width, 15 mils spacing
B12 D13# D45# E22 J5 REQ1# AP0# U2
HDJ14 C12 D22 HDJ46 HREQJ2 M6 U3 TP_APJ1 TP6 divider should be within 1.5" of the GTLREF pin
HDJ15 D14# D46# HDJ47 HREQJ3 REQ2# AP1# caps should be placed near CPU pin
D11 D15# D47# G22 K6 REQ3#
HDBIJ0 A8 D19 HDBIJ2 HREQJ4 J6 F3 HBR0J
9 HDBIJ0 DBI0# DBI2# HDBIJ2 9 HAJ[31..3] REQ4# BR0# HBR0J 9
C8 G20 R6 G3 TESTHI_8
9 HDSTBNJ0 DSTBN0# DSTBN2# HDSTBNJ2 9 9 HAJ[31..3] 9 HADSTBJ0 ADSTB0# TESTHI08 VTT_OUT_RIGHT
B9 G19 G5 G4 TESTHI_9
9 HDSTBPJ0 DSTBP0# DSTBP2# HDSTBPJ2 9 PCREQ# TESTHI09
H5 TESTHI_10
HDJ16 HDJ48 HAJ17 TESTHI10
G9 D16# D48# D20 AB6 A17#
HDJ17 F8 D17 HDJ49 HAJ18 W6 J16 TP_DPJ0 R813
HDJ18 D17# D49# HDJ50 HAJ19 A18# DP0# TP_DPJ1 100
F9 D18# D50# A14 Y6 A19# DP1# H15
HDJ19 E9 C15 HDJ51 HAJ20 Y4 H16 TP_DPJ2 +/-1%
HDJ20 D19# D51# HDJ52 HAJ21 A20# DP2# TP_DPJ3 R0603
D7 D20# D52# C14 AA4 A21# DP3# J17
HDJ21 E10 B15 HDJ53 HAJ22 AD6
HDJ22 D21# D53# HDJ54 HAJ23 A22# HGTLREF
D10 D22# D54# C18 AA5 A23# GTLREF H1
HDJ23 F11 B16 HDJ55 HAJ24 AB5
D23# D55# A24#
HDJ24
HDJ25
F12 D24# D56# A17 HDJ56
HDJ57
HAJ25
HAJ26
AC5 A25# RESET# G23 HCPURSTJ 9 BC938 BC939
R814
210
*
C
HDJ26
D13
E13
D25#
D26#
D57#
D58#
B18
C21 HDJ58 HAJ27
AB4
AF5
A26#
A27# RS0# B3 HRSJ0 9
* 1uF * 220pF +/-1%
C
HDJ27 G13 B21 HDJ59 HAJ28 AF4 F5 50V,
10V, Y5V, +80%/-20% X7R, +/-10%R0603
HDJ28 D27# D59# HDJ60 HAJ29 A28# RS1# HRSJ1 9 C0603 C0603
F14 D28# D60# B19 AG6 A29# RS2# A3 HRSJ2 9
HDJ29 G14 A19 HDJ61 HAJ30 AG4
HDJ30 D29# D61# HDJ62 HAJ31 A30#
F15 D30# D62# A22 AG5 A31#
HDJ31 G15 B22 HDJ63 TP_LAG775_PIN_AH4 AH4
D31# D63# TP11 A32# Place at CPU end of route
HDBIJ1 G11 C20 HDBIJ3 TP_LAG775_PIN_AH5 AH5
9 HDBIJ1 DBI1# DBI3# HDBIJ3 9 TP12 A33#
G12 A16 TP_LAG775_PIN_AJ5 AJ5
9 HDSTBNJ1 DSTBN1# DSTBN3# HDSTBNJ3 9 TP13 A34# HBR0J
E12 C17 TP_LAG775_PIN_AJ6 AJ6
9 HDSTBPJ1 DSTBP1# DSTBP3# HDSTBPJ3 9 TP14
AC4
A35# TBD CRB 0.7: 220 ohm, 5%
RSVD3 DG 0.51: 62 ohm, 5%
TBD AE4 RSVD4
Pin D23
CPU_Socket TBD 9 HADSTBJ1 AD5 ADSTB1#
CRB 0.7: test point TP_VCCPLL Pin AL2 PROCHOT#
Pin AM5 CRB 0.7: pull up to VTT_OUT_RIGHT 1 OF 7
CRB 0.7: test point TP_VID6 DG/611A: example VR thermal monitor circuit CPU_Socket
3 OF 7 HCPURSTJ BC940
U33C 22pF
14 SMIJ P2 SMI# TESTHI00 F26 TESTHI_0 TESTHI_0 6
*
K3 W3 TESTHI_1 VTT_OUT_LEFT C0603
14 A20MJ A20M# TESTHI01 FSB_VTT 10 mils width
R3 P1 TESTHI_11
14 FERRJ FERR#/PBE# TESTHI11 7 mils spacing
K1 W2 TESTHI_12
14 INTR
L1
LINT0 TESTHI12
F25
TBD R815 100 HCOMP2 VTT_OUT_RIGHT
14 NMI LINT1 TESTHI02 Pin AK6, G6
N2 G25 R816 100 HCOMP3
14 IGNNEJ IGNNE# TESTHI03 refer to CRB 0.7
M3 G27 R817 62 Dummy TESTHI_0
14 STPCLKJ STPCLK# TESTHI04
G26 R818 62 TESTHI_2_7 R819 60.4 HCOMP0 BC4 BC5
TESTHI05 R820 60.4 HCOMP1 0.1uF 0.1uF
B 6
6
HVCCA
HVSSA
A23
B23
VCCA
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