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foxconn ck804a07_rev_a_sch


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    5                       4                           3                      2                                       1




                                  CK804A07
D
                            nVIDIA CK804 Chipset forAM2 CPU                                                                                              D




                                          10/25/2006)

        PAGE                    CONTENT      PAGE           CONTENT
         1     Index                           22       PCI CONNECTOR 1-2
         2     Topology                        23       PCI CONNECTOR 3-4
         3     RESET MAP                       24       PCI TERMINATION
         4     CLOCK DISTRIBUTION              25       VT6307/6308
         5     Power Delivery                  26       LAN RTL8211BL
C


         6     M2-1 Hyper Transport            27       FWH & SPI                                                                                        C




         7     M2-2 DDR-1                      28       USB CONNECTORS
         8     M2-2 DDR-2                      29       IDE CONNECTORS
         9     M2-4 MISC                       30       AUDIO 653/850
        10     M2-5 Power                      31       AUDIO CONNECTORS 653/850
        11     DDRII SDRAM DIMM1-2             32       SIO ITE8716
        12     DDRII SDRAM DIMM3-4             33       FDD / PS2
        13     DDRTerminator                   34       FAN / HARDWARE MONITOR
        14     CK804 HT                        35       PRT COM PORT
B
        15     CK804 PCI EXPRESS               36       PWM ST L6711 AM2                                                                                 B




        16     CK804 PCI                       37       DDR POWER
        17     CK804 SATA / IDE                38       CK804 CORE
        18     CK804 G/MII / AC97 / USB        39       Power sequence
        19     CK804 DECOUPLING                40       PWR CON / FNT PNL / VBAT
        20     PCI EXPRESS X16 CONNECTOR       41       VID CONTROLLER
        21     PCI EXPRESS X1 CONNECTORS       42
                                                42
                                                        CHANGELIST
                                                                      42




A                                                                                                                                                        A




                                                                                                                                   TECHNOLOGY COPR.
                                                                                   Title
                                                                                                      Index
                                                                                   Document Number                                                 Rev

                                                                                                                 CK804A07                           A
                                                                                   Date:   Tuesday, October 31, 2006       Sheet    1    of   42
    5                       4                           3                      2                                       1
    5                                                4                                                        3                                                           2                                       1




D
                                                                                  BLOCK DIAGRAM                                                                                                                                                     D




                      POWER
                     SUPPLY                          VREG
                    CONNECTOR                                                         SOCKET 940
                                                                                                                                                          DDR SDRAM CONN A1
                                                                                         AM2

                                                                                                                                                          DDR SDRAM CONN B1



                                                                                                                                                          DDR SDRAM CONN A2



                                                                                                                                                          DDR SDRAM CONNB2
                                                         PCI EXPRESS/NEW CARD               HT 16X16 1GHZ
                        PEX X1



                                                         PCI EXPRESS
                                                                                                             PCI 33MHZ
                        PEX X16                                                                                                                            PCI SLOT 1

                                                                                       NFORCE
                                                         PCI EXPRESS
                        PEX X1 (2)                                                                                                                         PCI SLOT 2
                                                                                      CRUSH K804
                                                                                                             AC97
                                                                                                                                AC97
C                                                                                                                                                          PCI SLOT 3                                                                               C
                                                            ATA 133

                       PRIMARY IDE                                                                           X10 USB2
                                                                                                                                                           PCI SLOT 4


                        SECONDARY IDE
                                                                                                                                       BACK PANEL CONN
                                                                                                     RGMII
                                                                INTEGRATED SATA
                                                                                                                                       USB2 PORTS 4-5
                        X4 - SATA CONN
                                                                                                                                        QUAD STACK

                                                                                                                                       USB2 PORTS 8-9
                                                                                                                                         X2/GBIT LAN


                                                                                                                                       FRONT PANEL HDR


                                                                                                                                        USB2 PORTS 1-0
    FLOPPY CONN


    PS2/KBRD CONN                                                                                                                        USB2 PORTS 7-6
                          SIO             LPC BUS 33MHZ
    PARALLEL CONN
                      ITE IT8712F




    SERIAL CONN

B                                                                                                                                                                                                                                                   B


                                         4MB FLASH
                                                                                                                    MII/RGMII




A                                                                                                                                                                                                                                                   A




                                                                                                                                                                                                                              TECHNOLOGY COPR.
                                                                                                                                                                              Title
                                                                                                                                                                                                 Index
                                                                                                                                                                              Document Number                                                 Rev
                                                                                                                                                                                                             CK804A07                          A
                                                                                                                                                                              Date:   Tuesday, October 31, 2006       Sheet    2    of   42
    5                                                4                                                        3                                                           2                                       1
                 5                                       4                                                  3                             2                                                1




                                                                     RESET MAP

D                                                                                                                                                                                                                           D




                                                                      AM2



                                                                                                     CPU_RST*
                                                                               CPU RST*


                                                                                                     CPU_PWRGD
                                                                               CPU PWRGD




C                                                                                                                                                                                                                           C




                                           PWR SWTCH

                                                                     CK804
                                                                                                    CPU_PWRGD
                                                                             CPU PWRGD
    PWR CONN                                 PWRBTN*                                                CPU_RST*
                                                        PWR BUTTON           CPU RST*

                     SLP_S3*                                                                        PCIRST_SLOT1*
         PS ON                                          SLP S3*              PCI RST0*
                                                                                                    PCIRST_SLOT2*
                                                                             PCI RST1*
     PWR GOOD        POWER_GOOD                         PWRGD
                                                                                                    PCIRST_SLOT3-4*
                                                                             PCI RST2*

                                                                             PCI RST3*              PCIRST_IDE*

                                                                               LPC_RST*             LPCRST_FLASH*
     PWRGD SB                                PWRGD_SB   PWRGD_SB
                                                                                                    LPCRST_SIO*
B     CIRCUIT                                                                                                                                                                                                               B

                                                        PE_RESET*
                                                                             GPIO_AUX*

                                                                                                                  SIO   FLASH   PRI IDE       PCI SLOT 3                 PCI SLOT 2              PCI SLOT 1394




                               PEX X16                                                                                          SEC IDE       PCI SLOT 4                                         1394




                               PEX X1(2)                                                    LAN_PHY
                                                                                           RESET*



                               PEX X1NC




A                                                                                                                                                                                                                           A




                                                                                                                                                                                                    TECHNOLOGY COPR.
                                                                                                                                                     Title
                                                                                                                                                                        Reset Map
                                                                                                                                                     Document Number                                                  Rev

                                                                                                                                                                                   CK804A07                            A
                                                                                                                                                     Date:   Tuesday, October 31, 2006   Sheet          3   of   42
                 5                                       4                                                  3                             2                                                1
     5                                     4                                               3                               2                                                    1




                                K8 AM2 CPU
                                                                                         CHANNEL A1 0-63
               L0_CLKIN_H(1)         MEMORY_A0_CLK[2:0]                                                                        DIMM A1
                                     MEMORY_A0_CLK[2:0]*
               L0_CLKIN_L(1)
               L0_CLKIN_H(0)         MEMORY_B0_CLK[2:0]
D              L0_CLKIN_L(0)         MEMORY_B0_CLK[2:0]*                                                                       DIMM B1                                                                             D

                                                                                         CHANNEL B1 0-63
               L0_CLKOUT_H(1)
               L0_CLKOUT_L(1)
               L0_CLKOUT_H(0)                                                            CHANNEL A2 0-63
               L0_CLKOUT_L(0)        MEMORY_A1_CLK[2:0]                                                                        DIMM A2
                                     MEMORY_A1_CLK[2:0]*
                CPU_CLK_IN*
                                     MEMORY_B1_CLK[2:0]
                CPU_CLK_IN
                                     MEMORY_B1_CLK[2:0]*                                                                       DIMM B2
                                                                                         CHANNEL B2 0-63




                                   CK804

                  CPU_CLK_IN                   PE0_REFCLK
                  CPU_CLK_IN*                  PE0_REFCLK*                                                               PEX X16
                  HT_RXCLK0*
                  HT_RXCLK0
                                               PE1_REFCLK
                  HT_RXCLK1*
                                               PE1_REFCLK*                                                               PEX X1
                  HT_RXCLK1
                  HT_TXCLK1*
C                                                                                                                                                                                                                  C
                  HT_TXCLK1                    PE2_REFCLK
                  HT_TXCLK0*
                                               PE2_REFCLK*                                                               PEX X1
                  HT_TXCLK0
                                               PE3_REFCLK
                   XTAL_IN                     PE3_REFCLK*
    32.0 KHZ

                   XTAL_OUT

                    XTAL_IN

                                                                        14MHZ OR 24MHZ
    25 MHZ
                                                       BUF_SIO
                    XTAL_OUT                                                                               SIO
                                                         SUSCLK

                                                      LPC_CLK0


                                                      PCI_CLK0                                                                                                                             PCI SLOT 2
                                                      PCI_CLK1
                                                      PCI_CLK2
                                                      PCI_CLK3
                                                      PCI_CLK4
                                                      PCI_CLK5
                                                   PCI_CLK_FB                                                                                                                              PCI SLOT 1
B                                                                                                                                                                                                                  B




                                                                                                                                                                                           PCI SLOT 3
                                                             LPC_CLK1


                                                      AC_97CLK
                                                                        AC '97 LINK
                                                    AC_BITCLK                                                                                                                              PCI SLOT 4
                                                                                                                                  PCI_CLKLPC
                                                                                                                 AC97
                                                                                                                 CODEC

                                                    BUF_25MHZ                                                                                                                              1394




A                                                                                                                                                                                                                  A




                                                                                                                                                                                      TECHNOLOGY COPR.
                                                                                                                                          Title


                                                                                                                                          Document Number
                                                                                                                                                             Clock Distribution                              Rev

                                                                                                                                                                        CK804A07                              A
                                                                                                                                          Date:   Tuesday, October 31, 2006   Sheet    4       of       42

     5                                     4                                               3                               2                                                    1
                      5                               4                                   3                              2                                                   1




D
                                                                                                               POWER CONN                                                                                D

             +5V                                 AOD4600                       +5V_DUAL

           +5V_STBY
                                                                                                     12V_SYS   5V_SYS        3.3V_SYS        5V_STBY                   -12V_SYS



            3D3V__DUAL                    AZ1084D-ADJTRE1
                                                                                               5V_DUAL                                                                 MEM-POWER
                                                                                                                  RT9214PS                            1D8V_STR

                            AP15N03H
C                                                                                                                                                                                                        C




    3D3V_SYS/5V_SYS
                              AME8800                        +2.5V                              VTT_DDR               RT9173




        3D3V_SYS                                                                               1D2V_HT            AP15N03H
                          RT9166A-15PXL                    +1.5V_SP_PLLPWR



B                                                                                                                                                                                                        B




          12V_SYS
                             LM78L05                                5V_AUDIO
                                                                                              3.3V_DUAL        RT9166A-15PXL                   +1.5V_DUAL




        12V_VRM                                                       CPU-POWER
                             L6711TR                       +V_CPU
                                                                                               5V_SYS                                            1D5V_CORE
                                                                                                                  RT9214PS




A                                                                                                                                                                                                        A




                                                                                                                                                                                   TECHNOLOGY COPR.
                                                                                                                                   Title
                                                                                                                                                      Reset Map
                                                                                                                                   Document Number                                                 Rev

                                                                                                                                                                 CK804A07                           A
                                                                                                                                   Date:   Tuesday, October 31, 2006       Sheet    5    of   41
                      5                               4                                   3                              2                                                   1
                 5                                                           4                                                                3                                                           2                                                 1




                                                                                                                           U1A
                                                                                                                    HYPERTRANSPORT
                                                                                   HT_UPCLK1         N6                                            AD5                  HT_DWNCLK1
                                                         14   HT_UPCLK1            HT_UPCLK1*             L0_CLKIN_H(1)           L0_CLKOUT_H(1)                        HT_DWNCLK1*         HT_DWNCLK1        14
                                                         14   HT_UPCLK1*                             P6   L0_CLKIN_L(1)           L0_CLKOUT_L(1)   AD4                                      HT_DWNCLK1*        14
                                                                                   HT_UPCLK0         N3                                            AD1                  HT_DWNCLK0
D                                                        14   HT_UPCLK0            HT_UPCLK0*             L0_CLKIN_H(0)           L0_CLKOUT_H(0)                        HT_DWNCLK0*         HT_DWNCLK0        14                                                                        D
                                       1D2V_HT                                                       N2                                            AC1                                      HT_DWNCLK0*        14
                                                         14   HT_UPCLK0*                                  L0_CLKIN_L(0)           L0_CLKOUT_L(0)
                                                 R100         49.9 r0603h6 +/-1%   HT_CPU_CTLIN_H1   V4                                            Y6    HT_CPU_CTLOUT_H1   1       TP1
                                                 R101         49.9 r0603h6 +/-1%   HT_CPU_CTLIN_L1
                                                                                                          L0_CTLIN_H(1)           L0_CTLOUT_H(1)         HT_CPU_CTLOUT_L1           TP2
                                                                                                     V5   L0_CTLIN_L(1)           L0_CTLOUT_L(1)   W6                       1
                                                                                   HT_UPCNTL         U1                                            W2                   HT_DWNCNTL
                                         GND             14 HT_UPCNTL              HT_UPCNTL*             L0_CTLIN_H(0)           L0_CTLOUT_H(0)                        HT_DWNCNTL*         HT_DWNCNTL 14
                                                         14 HT_UPCNTL*                               V1   L0_CTLIN_L(0)           L0_CTLOUT_L(0)   W3                                       HT_DWNCNTL* 14
                                                                                   HT_UP15           U6                                            Y5        HT_DWN15
                                                                  HT_UP*15
                                                                                                          L0_CADIN_H(15)         L0_CADOUT_H(15)                                HT_DWN*15
                                                                                                     V6   L0_CADIN_L(15)         L0_CADOUT_L(15)   Y4
                                                                                   HT_UP14           T4                                            AB6       HT_DWN14
                                                                  HT_UP*14
                                                                                                          L0_CADIN_H(14)         L0_CADOUT_H(14)                                HT_DWN*14
                                                                                                     T5   L0_CADIN_L(14)         L0_CADOUT_L(14)   AA6
                                                                                   HT_UP13           R6                                            AB5       HT_DWN13
                                                                  HT_UP*13
                                                                                                          L0_CADIN_H(13)         L0_CADOUT_H(13)                                HT_DWN*13
                                                                                                     T6   L0_CADIN_L(13)         L0_CADOUT_L(13)   AB4
                                                                                   HT_UP12           P4                                            AD6       HT_DWN12
                                                                  HT_UP*12
                                                                                                          L0_CADIN_H(12)         L0_CADOUT_H(12)                                HT_DWN*12            HT_DWN[15..0]
                                                                                                     P5   L0_CADIN_L(12)         L0_CADOUT_L(12)   AC6                                                                             HT_DWN[15..0]    14
                       HT_UP[15..0]                                                HT_UP11           M4                                            AF6       HT_DWN11
    14 HT_UP[15..0]                                               HT_UP*11
                                                                                                          L0_CADIN_H(11)         L0_CADOUT_H(11)                                HT_DWN*11
                                                                                                     M5   L0_CADIN_L(11)         L0_CADOUT_L(11)   AE6
                                                                                   HT_UP10           L6                                            AF5       HT_DWN10
                                                                  HT_UP*10
                                                                                                          L0_CADIN_H(10)         L0_CADOUT_H(10)                                HT_DWN*10          HT_DWN*[15..0]
                                                                                                     M6   L0_CADIN_L(10)         L0_CADOUT_L(10)   AF4                                                                             HT_DWN*[15..0]    14
                       HT_UP*[15..0]                                               HT_UP9            K4                                            AH6       HT_DWN9
    14 HT_UP*[15..0]                                              HT_UP*9
                                                                                                          L0_CADIN_H(9)           L0_CADOUT_H(9)                                HT_DWN*9
                                                                                                     K5   L0_CADIN_L(9)           L0_CADOUT_L(9)   AG6
                                                                                   HT_UP8            J6                                            AH5       HT_DWN8
                                                                  HT_UP*8
                                                                                                          L0_CADIN_H(8)           L0_CADOUT_H(8)                                HT_DWN*8
                                                                                                     K6   L0_CADIN_L(8)           L0_CADOUT_L(8)   AH4

                                                                                   HT_UP7            U3                                            Y1        HT_DWN7
                                                                  HT_UP*7
                                                                                                          L0_CADIN_H(7)          L0_CADOUT_H(7)                                 HT_DWN*7
                                                                                                     U2   L0_CADIN_L(7)          L0_CADOUT_L(7)    W1
C                                                                                  HT_UP6            R1                                            AA2       HT_DWN6                                                                                                                    C
                                                                  HT_UP*6
                                                                                                          L0_CADIN_H(6)          L0_CADOUT_H(6)                                 HT_DWN*6
                                                                                                     T1   L0_CADIN_L(6)          L0_CADOUT_L(6)    AA3
                                                                                   HT_UP5            R3                                            AB1       HT_DWN5
                                                                  HT_UP*5
                                                                                                          L0_CADIN_H(5)          L0_CADOUT_H(5)                                 HT_DWN*5
                                                                                                     R2   L0_CADIN_L(5)          L0_CADOUT_L(5)    AA1
                                                                                   HT_UP4            N1                                            AC2       HT_DWN4
                                                                  HT_UP*4
                                                                                                          L0_CADIN_H(4)          L0_CADOUT_H(4)                                 HT_DWN*4
                                                                                                     P1   L0_CADIN_L(4)          L0_CADOUT_L(4)    AC3
                                                                                   HT_UP3            L1                                            AE2       HT_DWN3
                                                                  HT_UP*3
                                                                                                          L0_CADIN_H(3)          L0_CADOUT_H(3)                                 HT_DWN*3
                                                                                                     M1   L0_CADIN_L(3)          L0_CADOUT_L(3)    AE3
                                                                                   HT_UP2            L3                                            AF1       HT_DWN2
                                                                  HT_UP*2
                                                                                                          L0_CADIN_H(2)          L0_CADOUT_H(2)                                 HT_DWN*2
                                                                                                     L2   L0_CADIN_L(2)          L0_CADOUT_L(2)    AE1
                                                                                   HT_UP1            J1                                            AG2       HT_DWN1
                                                                  HT_UP*1
                                                                                                          L0_CADIN_H(1)          L0_CADOUT_H(1)                                 HT_DWN*1
                                                                                                     K1   L0_CADIN_L(1)          L0_CADOUT_L(1)    AG3
                                                                                   HT_UP0            J3                                            AH1       HT_DWN0
                                                                  HT_UP*0
                                                                                                          L0_CADIN_H(0)          L0_CADOUT_H(0)                                 HT_DWN*0
                                                                                                     J2   L0_CADIN_L(0)          L0_CADOUT_L(0)    AG1




             A1                                    A31
                                                                                    Layout: Add stitching caps if crossing plane split



B                                                                                               HyperTransport Net Naming Convention                                                                                                                                                    B


                              M2                                                 HT_"link driver"_"link receiver"_"function"_"polarity"_"number"
                            Top View


           AL1




A                                                                                                                                                                                                                                                                                       A




                                                                                                                                                                                                                                                                  TECHNOLOGY COPR.
                                                                                                                                                                                                                     Title
                                                                                                                                                                                                                                        M2-1 Hyper Transport
                                                                                                                                                                                                                     Document Number                                              Rev

                                                                                                                                                                                                                                                    CK804A07                       A
                                                                                                                                                                                                                     Date:   Tuesday, October 31, 2006    Sheet    6    of   41
                 5                                                           4                                                                3                                                           2                                                 1
    5                                                     4                                                              3                                                   2                                         1




                                                                                     U1B
                                                                              MEMORY INTERFACE A
                         11,13   MEM_MA0_CLK_H2               AG21    MA0_CLK_H(2)           MA_DATA(63)      AE14 MEM_MA_DATA63                  MEM_MA_DATA[63..0] 11,12
D                        11,13   MEM_MA0_CLK_L2               AG20    MA0_CLK_L(2)           MA_DATA(62)      AG14 MEM_MA_DATA62                                                                                                                   D
                         11,13   MEM_MA0_CLK_H1                G19    MA0_CLK_H(1)           MA_DATA(61)      AG16 MEM_MA_DATA61
                         11,13   MEM_MA0_CLK_L1                H19    MA0_CLK_L(1)           MA_DATA(60)      AD17 MEM_MA_DATA60
                         11,13   MEM_MA0_CLK_H0                U27    MA0_CLK_H(0)           MA_DATA(59)      AD13 MEM_MA_DATA59
                         11,13   MEM_MA0_CLK_L0                U26    MA0_CLK_L(0)           MA_DATA(58)      AE13 MEM_MA_DATA58
                                                                                             MA_DATA(57)      AG15 MEM_MA_DATA57
                         11,13 MEM_MA0_CS_L1                  AC25    MA0_CS_L(1)            MA_DATA(56)      AE16 MEM_MA_DATA56
                         11,13 MEM_MA0_CS_L0                  AA24    MA0_CS_L(0)            MA_DATA(55)      AG17 MEM_MA_DATA55
                                                                                             MA_DATA(54)      AE18 MEM_MA_DATA54
                         11,13 MEM_MA0_ODT0                   AC28    MA0_ODT(0)             MA_DATA(53)      AD21 MEM_MA_DATA53
                                                                                             MA_DATA(52)      AG22 MEM_MA_DATA52
                         12,13   MEM_MA1_CLK_H2               AE20    MA1_CLK_H(2)           MA_DATA(51)      AE17 MEM_MA_DATA51
                         12,13   MEM_MA1_CLK_L2               AE19    MA1_CLK_L(2)           MA_DATA(50)      AF17 MEM_MA_DATA50
                         12,13   MEM_MA1_CLK_H1                G20    MA1_CLK_H(1)           MA_DATA(49)      AF21 MEM_MA_DATA49
                         12,13   MEM_MA1_CLK_L1                G21    MA1_CLK_L(1)           MA_DATA(48)      AE21 MEM_MA_DATA48
                         12,13   MEM_MA1_CLK_H0                V27    MA1_CLK_H(0)           MA_DATA(47)      AF23 MEM_MA_DATA47
                         12,13   MEM_MA1_CLK_L0               W27     MA1_CLK_L(0)           MA_DATA(46)      AE23 MEM_MA_DATA46
                                                                                             MA_DATA(45)      AJ26 MEM_MA_DATA45
                         12,13 MEM_MA1_CS_L1                  AD27    MA1_CS_L(1)            MA_DATA(44)      AG26 MEM_MA_DATA44
                         12,13 MEM_MA1_CS_L0                  AA25    MA1_CS_L(0)            MA_DATA(43)      AE22 MEM_MA_DATA43
                                                                                             MA_DATA(42)      AG23 MEM_MA_DATA42
                         12,13 MEM_MA1_ODT0                   AC27    MA1_ODT(0)             MA_DATA(41)      AH25 MEM_MA_DATA41
                                                                                             MA_DATA(40)      AF25 MEM_MA_DATA40
                                                                                             MA_DATA(39)      AJ28 MEM_MA_DATA39
                      11,12,13 MEM_MA_CAS_L                   AB25    MA_CAS_L               MA_DATA(38)      AJ29 MEM_MA_DATA38
                      11,12,13 MEM_MA_WE_L                    AB27    MA_WE_L                MA_DATA(37)      AF29 MEM_MA_DATA37
                      11,12,13 MEM_MA_RAS_L                   AA26    MA_RAS_L               MA_DATA(36)      AE26 MEM_MA_DATA36
C                                                                                            MA_DATA(35)      AJ27 MEM_MA_DATA35                                                                                                                   C
                      11,12,13 MEM_MA_BANK2                    N25    MA_BANK(2)             MA_DATA(34)      AH27 MEM_MA_DATA34
                      11,12,13 MEM_MA_BANK1                    Y27    MA_BANK(1)             MA_DATA(33)      AG29 MEM_MA_DATA33
                      11,12,13 MEM_MA_BANK0                   AA27    MA_BANK(0)             MA_DATA(32)      AF27 MEM_MA_DATA32
                                                                                             MA_DATA(31)      E29 MEM_MA_DATA31
                         12,13 MEM_MA_CKE1                     L27    MA_CKE(1)              MA_DATA(30)      E28 MEM_MA_DATA30
                         11,13 MEM_MA_CKE0                     M25    MA_CKE(0)              MA_DATA(29)      D27 MEM_MA_DATA29
                                                                                             MA_DATA(28)      C27 MEM_MA_DATA28
                                                  MEM_MA_ADD15 M27                                            G26 MEM_MA_DATA27
    11,12,13 MEM_MA_ADD[15..0]                                        MA_ADD(15)             MA_DATA(27)
                                                  MEM_MA_ADD14 N24                                            F27 MEM_MA_DATA26
                                                  MEM_MA_ADD13 AC26
                                                                      MA_ADD(14)             MA_DATA(26)
                                                                      MA_ADD(13)             MA_DATA(25)      C28 MEM_MA_DATA25
                                                  MEM_MA_ADD12 N26                                            E27 MEM_MA_DATA24
                                                  MEM_MA_ADD11 P25
                                                                      MA_ADD(12)             MA_DATA(24)
                                                                      MA_ADD(11)             MA_DATA(23)      F25 MEM_MA_DATA23
                                                  MEM_MA_ADD10 Y25                                            E25 MEM_MA_DATA22
                                                  MEM_MA_ADD9
                                                                      MA_ADD(10)             MA_DATA(22)
                                                                N27   MA_ADD(9)              MA_DATA(21)      E23 MEM_MA_DATA21
                                                  MEM_MA_ADD8   R24                                           D23 MEM_MA_DATA20
                                                  MEM_MA_ADD7
                                                                      MA_ADD(8)              MA_DATA(20)
                                                                P27   MA_ADD(7)              MA_DATA(19)      E26 MEM_MA_DATA19
                                                  MEM_MA_ADD6   R25                                           C26 MEM_MA_DATA18
                                                  MEM_MA_ADD5
                                                                      MA_ADD(6)              MA_DATA(18)
                                                                R26   MA_ADD(5)              MA_DATA(17)      G23 MEM_MA_DATA17
                                                  MEM_MA_ADD4   R27                                           F23 MEM_MA_DATA16
                                                  MEM_MA_ADD3
                                                                      MA_ADD(4)              MA_DATA(16)
                                                                T25   MA_ADD(3)              MA_DATA(15)      E22 MEM_MA_DATA15
                                                  MEM_MA_ADD2   U25                                           E21 MEM_MA_DATA14
                                                  MEM_MA_ADD1
                                                                      MA_ADD(2)              MA_DATA(14)
                                                                T27   MA_ADD(1)              MA_DATA(13)      F17 MEM_MA_DATA13
                                                  MEM_MA_ADD0 W24                                             G17 MEM_MA_DATA12
                                                                      MA_ADD(0)              MA_DATA(12)
                                                                                             MA_DATA(11)      G22 MEM_MA_DATA11
                                                  MEM_MA_DQS_H7
                                                              AD15                                            F21 MEM_MA_DATA10
         11,12 MEM_MA_DQS_H[7..0]                                     MA_DQS_H(7)            MA_DATA(10)
                                                  MEM_MA_DQS_L7
                                                              AE15                                            G18 MEM_MA_DATA9
         11,12 MEM_MA_DQS_L[7..0]                                     MA_DQS_L(7)             MA_DATA(9)
B                                                 MEM_MA_DQS_H6
                                                              AG18                                            E17 MEM_MA_DATA8                                                                                                                     B
                                                  MEM_MA_DQS_L6
                                                                      MA_DQS_H(6)             MA_DATA(8)
                                                              AG19    MA_DQS_L(6)             MA_DATA(7)      G16 MEM_MA_DATA7
                                                  MEM_MA_DQS_H5
                                                              AG24                                            E15 MEM_MA_DATA6
                                                  MEM_MA_DQS_L5
                                                                      MA_DQS_H(5)             MA_DATA(6)
                                                              AG25    MA_DQS_L(5)             MA_DATA(5)      G13 MEM_MA_DATA5
                                                  MEM_MA_DQS_H4
                                                              AG27                                            H13 MEM_MA_DATA4
                                                  MEM_MA_DQS_L4
                                                                      MA_DQS_H(4)             MA_DATA(4)
                                                              AG28    MA_DQS_L(4)             MA_DATA(3)      H17 MEM_MA_DATA3
                                                  MEM_MA_DQS_H3 D29                                           E16 MEM_MA_DATA2
                                                  MEM_MA_DQS_L3 C29
                                                                      MA_DQS_H(3)             MA_DATA(2)
                                                                      MA_DQS_L(3)             MA_DATA(1)      E14 MEM_MA_DATA1
                                                  MEM_MA_DQS_H2 C25                                           G14 MEM_MA_DATA0
                                                  MEM_MA_DQS_L2 D25
                                                                      MA_DQS_H(2)             MA_DATA(0)
                                                  MEM_MA_DQS_H1 E19
                                                                      MA_DQS_L(2)
                                                                      MA_DQS_H(1)            MA_DQS_H(8)      J28                   MEM_MA_DQS_H8 11,12
                                                  MEM_MA_DQS_L1 F19                                           J27
                                                                      MA_DQS_L(1)            MA_DQS_L(8)                            MEM_MA_DQS_L8 11,12
                                                  MEM_MA_DQS_H0 F15
                                                  MEM_MA_DQS_L0 G15
                                                                      MA_DQS_H(0)
                                                                      MA_DQS_L(0)                  MA_DM(8)   J25                   MEM_MA_DM8 11,12
                                                    MEM_MA_DM7AF15                                            K25   MEM_MA_CHECK7
        11,12 MEM_MA_DM[7..0]                                         MA_DM(7)               MA_CHECK(7)                                          MEM_MA_CHECK[7..0] 11,12
                                                    MEM_MA_DM6AF19                                            J26   MEM_MA_CHECK6
                                                    MEM_MA_DM5 AJ25
                                                                      MA_DM(6)               MA_CHECK(6)            MEM_MA_CHECK5
                                                                      MA_DM(5)               MA_CHECK(5)      G28
                                                    MEM_MA_DM4AH29                                            G27   MEM_MA_CHECK4
                                                    MEM_MA_DM3 B29
                                                                      MA_DM(4)               MA_CHECK(4)            MEM_MA_CHECK3
                                                                      MA_DM(3)               MA_CHECK(3)      L24
                                                    MEM_MA_DM2 E24                                            K27   MEM_MA_CHECK2
                                                    MEM_MA_DM1 E18
                                                                      MA_DM(2)               MA_CHECK(2)            MEM_MA_CHECK1
                                                                      MA_DM(1)               MA_CHECK(1)      H29
                                                    MEM_MA_DM0 H15                                            H27   MEM_MA_CHECK0
                                                                      MA_DM(0)               MA_CHECK(0)




A                                                                                                                                                                                                                                                  A




                                                                                                                                                                                                                             TECHNOLOGY COPR.
                                                                                                                                                                                 Title
                                                                                                                                                                                                      M2-2 DDR-1
                                                                                                                                                                                 Document Number                                             Rev

                                                                                                                                                                                                               CK804A07                       A
                                                                                                                                                                                 Date:   Tuesday, October 31, 2006   Sheet    7    of   41
    5                                                     4                                                              3                                                   2                                         1
    5                                                   4                                                              3                                                   2                                         1




                                                                                         U1C
                                                                                 MEMORY INTERFACE B
                            11,13    MEM_MB0_CLK_H2                AJ19   MB0_CLK_H(2)          MB_DATA(63)      AH13 MEM_MB_DATA63                 MEM_MB_DATA[63..0] 11,12
D                           11,13    MEM_MB0_CLK_L2                AK19   MB0_CLK_L(2)          MB_DATA(62)      AL13 MEM_MB_DATA62                                                                                                              D
                            11,13    MEM_MB0_CLK_H1                 A18   MB0_CLK_H(1)          MB_DATA(61)      AL15 MEM_MB_DATA61
                            11,13    MEM_MB0_CLK_L1                 A19   MB0_CLK_L(1)          MB_DATA(60)      AJ15 MEM_MB_DATA60
                            11,13    MEM_MB0_CLK_H0                 U31   MB0_CLK_H(0)          MB_DATA(59)      AF13 MEM_MB_DATA59
                            11,13    MEM_MB0_CLK_L0                 U30   MB0_CLK_L(0)          MB_DATA(58)      AG13 MEM_MB_DATA58
                                                                                                MB_DATA(57)      AL14 MEM_MB_DATA57
                            11,13 MEM_MB0_CS_L1                    AE30   MB0_CS_L(1)           MB_DATA(56)      AK15 MEM_MB_DATA56
                            11,13 MEM_MB0_CS_L0                    AC31   MB0_CS_L(0)           MB_DATA(55)      AL16 MEM_MB_DATA55
                                                                                                MB_DATA(54)      AL17 MEM_MB_DATA54
                            11,13 MEM_MB0_ODT0                     AD29   MB0_ODT(0)            MB_DATA(53)      AK21 MEM_MB_DATA53
                                                                                                MB_DATA(52)      AL21 MEM_MB_DATA52
                            12,13    MEM_MB1_CLK_H2                AL19   MB1_CLK_H(2)          MB_DATA(51)      AH15 MEM_MB_DATA51
                            12,13    MEM_MB1_CLK_L2                AL18   MB1_CLK_L(2)          MB_DATA(50)      AJ16 MEM_MB_DATA50
                            12,13    MEM_MB1_CLK_H1                 C19   MB1_CLK_H(1)          MB_DATA(49)      AH19 MEM_MB_DATA49
                            12,13    MEM_MB1_CLK_L1                 D19   MB1_CLK_L(1)          MB_DATA(48)      AL20 MEM_MB_DATA48
                            12,13    MEM_MB1_CLK_H0                W29    MB1_CLK_H(0)          MB_DATA(47)      AJ22 MEM_MB_DATA47
                            12,13    MEM_MB1_CLK_L0                W28    MB1_CLK_L(0)          MB_DATA(46)      AL22 MEM_MB_DATA46
                                                                                                MB_DATA(45)      AL24 MEM_MB_DATA45
                            12,13 MEM_MB1_CS_L1                    AE29   MB1_CS_L(1)           MB_DATA(44)      AK25 MEM_MB_DATA44
                            12,13 MEM_MB1_CS_L0                    AB31   MB1_CS_L(0)           MB_DATA(43)      AJ21 MEM_MB_DATA43
                                                                                                MB_DATA(42)      AH21 MEM_MB_DATA42
                            12,13 MEM_MB1_ODT0                     AD31   MB1_ODT(0)            MB_DATA(41)      AH23 MEM_MB_DATA41
                                                                                                MB_DATA(40)      AJ24 MEM_MB_DATA40
                                                                                                MB_DATA(39)      AL27 MEM_MB_DATA39
                         11,12,13 MEM_MB_CAS_L                     AC29   MB_CAS_L              MB_DATA(38)      AK27 MEM_MB_DATA38
                         11,12,13 MEM_MB_WE_L                      AC30   MB_WE_L               MB_DATA(37)      AH31 MEM_MB_DATA37
                         11,12,13 MEM_MB_RAS_L                     AB29   MB_RAS_L              MB_DATA(36)      AG30 MEM_MB_DATA36
C                                                                                               MB_DATA(35)      AL25 MEM_MB_DATA35                                                                                                              C
                         11,12,13 MEM_MB_BANK2                      N31   MB_BANK(2)            MB_DATA(34)      AL26 MEM_MB_DATA34
                         11,12,13 MEM_MB_BANK1                     AA31   MB_BANK(1)            MB_DATA(33)      AJ30 MEM_MB_DATA33
                         11,12,13 MEM_MB_BANK0                     AA28   MB_BANK(0)            MB_DATA(32)      AJ31 MEM_MB_DATA32
                                                                                                MB_DATA(31)      E31 MEM_MB_DATA31
                            12,13 MEM_MB_CKE1                      M31    MB_CKE(1)             MB_DATA(30)      E30 MEM_MB_DATA30
                            11,13 MEM_MB_CKE0                      M29    MB_CKE(0)             MB_DATA(29)      B27 MEM_MB_DATA29
                                                                                                MB_DATA(28)      A27 MEM_MB_DATA28
                                                      MEM_MB_ADD15 N28                                           F29 MEM_MB_DATA27
        11,12,13 MEM_MB_ADD[15..0]                                        MB_ADD(15)            MB_DATA(27)
                                                      MEM_MB_ADD14 N29                                           F31 MEM_MB_DATA26
                                                      MEM_MB_ADD13 AE31
                                                                          MB_ADD(14)            MB_DATA(26)
                                                                          MB_ADD(13)            MB_DATA(25)      A29 MEM_MB_DATA25
                                                      MEM_MB_ADD12 N30                                           A28 MEM_MB_DATA24
                                                      MEM_MB_ADD11 P29
                                                                          MB_ADD(12)            MB_DATA(24)
                                                                          MB_ADD(11)            MB_DATA(23)      A25 MEM_MB_DATA23
                                                      MEM_MB_ADD10 AA29                                          A24 MEM_MB_DATA22
                                                      MEM_MB_ADD9
                                                                          MB_ADD(10)



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