Service Manuals, User Guides, Schematic Diagrams or docs for : Gigabyte GIGABYTE GIGABYTE 7VT600P-RZ - REV 1.0
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5 4 3 2 1
Model Name:7VT600P-RZ Circuit or PCB layout change
BOM Version:9MVT600PRZ-00-10A for next version
PCB Version:7VT600P-RZ REV:1.0 Date Change Item Reason
D 2004/02/24 7VT600-RZ REV1.0 change to 7VT600P-RZ REV1.0 D
Component value change 2004/01/13
history
Date Change Item Reason
2004/02/24 9MVT600RZ-00-10A==>9MVT600PRZ-00-10A 1.S/B from 8235CE change to 8237CD
2004/03/04 9MVT600PRZ-00-10A==>9MVT600PRZ-00-10A 1.Add VT8237 china package
2004/03/16 9MVT600RZ-00-10A==>9MVT600RZ-00-10A 1.REGULATOR AP1250M APEC
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Digitally signed by dd
C
DN: cn=dd, o=dd, ou=dd, C
[email protected], c=US
Date: 2009.10.23 06:41:37
+07'00'
B B
Project Code:A92185-3
A A
Blue/304.8*200.025/C /60ohm+-15%
PCB ; ~~~~~~~~~~4GBC
GIGABYTE
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 1.0
7VT600P-RZ
Date: , 16, 2004 Sheet 1 of 35
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5 4 3 2 1
Model Name:7VT600P-RZ Revision 1.0
SHEET TITLE SHEET TITLE
D D
1 BOM & PCB MODIFY HISTORY 31 GPIO CONFIGUATION
2 COVER SHEET 32 VIA VT6103L PHY
3 BLOCK DIAGRAM 33 POWER TRACE WIDTH
4,5 AMD CPU SOCKET A 34 TEST POINT
6,7,8,9 KT600 (NORTH BRIDGE) HOST; DDR; AGP,VLINK,POWER/GOUND
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35 JUMPER TABLE
10 CLOCK GENERATOR (ICS94230BF, ICS93738AF)
11,12,13 VT8237 (SOUTH BIRDGE)
C C
14,15 DDR SDRAM DIMMS 1,2,3,DDR TERMINATION
16 AGP SLOT
17,18 PCI SLOT 1,2,3,4,5
19 IDE,USB
20 LPCIO_IT8705
21 BIOS
22 COM,PRT,FDD,KB/MS,IR
B B
23 AC 97 CODEC
24 AUDIO JACK,GAME PORT
25 VIA VT6122 LAN& USB CONNECTOR
26 PANEL,STR LED,FANS
27 DDR POWER
28 ATX CONN,3VDUAL,VDDQ DC POWER
COMPONENT SIDE
(1 oz. Copper)
29 VCORE PHASE PWM FAIRCHILD FAN5091M GND SIDE
(1 oz. Copper)
VCC SIDE
A (1 oz. Copper) A
30 VID,FID CONTROL SOLDER SIDE
(1 oz. Copper)
GIGABYTE
Title
COVER SHEET
Size Document Number Rev
Custom 1.0
7VT600P-RZ
Date: , 16, 2004 Sheet 2 of 35
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5 4 3 2 1
7VT600P-RZ BLOCK DIAGRAM
AMD K7
D D
CLOCK/G & CLOCK/B
VID0~4
PWM/OTHER POWER
VCORE = 1.75V (650-1100MHZ) / SLEEP : 1.3V
VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I) VCCA = 2.5V ; 2_5V = 2.5V PAGE 4, 5 VCORE = 1.75V (650-1100MHZ) / SLEEP : 1.3V
VCC3 = 3.3V PAGE 10 5VSB,-12V,+12V,VCC,VCC3,3VDUAL
DDRVTT,DDR25V,3VSTR,VCC25 PAGE 27,28,29
GAD0~31 VIA KT600 NORTH BRIDGE
AD_STB0,-AD_STB0
AD_STB1,-AD_STB1
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SBA0~7 MAA0~15
AGP SLOT 4X/8X SB_STB,-SB_STB MDD0~63 DDR SDRAM DIMM X 3
-DQSD0~7
VDDQ = 1.5V (AGP POWER 4X) -GBE0~3
VCC3 = 3.3V VCORE = 1.75V (650-1100MHZ) / SLEEP : 1.3V
DQM0~7
+12V = 12V ST0~2 AGP BUS DDR25V = 2.5V(SUSPEND POWER) DDR25V = 2.5V(SUSPEND POWER)
3VDUAL = 3.3V VDDQ = 1.5V (AGP POWER 4X) DDRVTT = 1.25V
VCC = 5V PAGE 16 VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I) PAGE 14,15
PAGE 6,7,8,9
C C
VLAD0~7
CONTROL BUS V LINK RTL8101L & USB CONN
PAGE 25
USB PORTS 0~5(7) VIA VT8235/CE SOUTH BRIDGE PCI LAN
(VT8237/CD)
VCC = 5V
5VSB = 5V
5VUSB = 5V PAGE 19 IDE Primary and Secondary
VCC = 5V
VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I)
3VDUAL = 3.3V(SUSPEND POWER) PAGE 19
VCC3 = 3.3V
AC97 CODEC ALC655/C RTCVDD = 3.3V
PAGE 11,12,13
+12V = 12V
VCC3 = 3.3V
VCC = 5V
AVDD = 5V PAGE 23 PCI BUS
B B
PCI SLOT 1,2,3,4,5
BIOS
+12 = 12V
AUDIO PORTS : FRONT AUDIO -12 = -12V
VCC = 5V
VCC3 = 3V
3VDUAL = 3V PAGE 17,18 VCC = 5V
LIN_ OUT LINE_IN MIC VCC3 = 3V PAGE 21
TELE CD_IN AUX_IN GAME PORT
PAGE 24
LPC BUS
LPC I/O IT8705
VCC = 5V
5VSB = 5V
VBAT = 3V PAGE 20
A
FRONT PANEL /FANS I/O PORTS : A
VCC = 5V
5VSB = 5V
COMA COMB LPT PS2 IR FDD
+12 = 12V
PVCC = 5V PAGE 26 PAGE 22
GIGABYTE
Title
BLOCK DIAGRAM
Size Document Number Rev
Custom 1.0
7VT600P-RZ
Date: , 16, 2004 Sheet 3 of 35
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5 4 3 2 1
-CPURST
SOCKET_AA
-SDATA[0..63] -SDATA0 AA35 AE1 -A20M
6 -SDATA[0..63] SDATA0 A20M -A20M 11
-SDATA1 W37 AG1 FERR C3
-SDATA2 SDATA1 FERR -CPUINIT 1N/4/X
W35 SDATA2 INIT AJ3 -CPUINIT 11
-SDATA3 Y35 AL1 INTR
SDATA3 INTR INTR 11
-SDATA4 U35 AJ1 -IGNNE VCC3
SDATA4 IGNNE -IGNNE 11
-SDATA5 U33 AN3 NMI
SDATA5 NMI NMI 11
-SDATA6 S37 AG3 -CPURST -CPURST 28
-SDATA7 SDATA6 RESET -SMI PWK
D -SDATA8
S33
AA33
SDATA7 0 SMI AN5
AC1 -STPCLK
-SMI 11
VCORE R2 D
SDATA8 STPCLK -STPCLK 11
-SDATA9 AE37 220/6
-SDATA10 SDATA9 PWK VCORE
AC33 SDATA10 PWROK AE3 PWK 28
-SDATA11 AC37 C146
SDATA11 -FERR 11
-SDATA12 Y37 10P/4/X
SDATA12
3
-SDATA13 AA37 N1 PICCLK0 R3 R4
SDATA13 PICCLK PICCLK0 10
-SDATA14 AC35 N3 -PICD0 60.4/6/1 60.4/6/1 R5 C Q2
SDATA14 PICD0/BYPASSCLK -PICD0 11
-SDATA15 S35 N5 -PICD1 680/6 B E MMBT2222A/SOT23
SDATA15 PICD1/BYPASSCLK -PICD1 11
-SDATA16 Q37 R6
-SDATA17 SDATA16 -COREFB FERR R7 1K/6 FERR+
Q35 SDATA17 COREFB- AG13
-SDATA18 COREFB
2
1
N37 SDATA18 COREFB+ AG11
-SDATA19 J33 301/6/1/X
-SDATA20 SDATA19 C1 680P/4/X/50V CPUCLK
G33 SDATA20 CLKIN AN17 CPUCLK 10
-SDATA21 C2 680P/4/X/50V -CPUCLK To CPU RN1
G37 SDATA21 CLKIN AL17 -CPUCLK 10
-SDATA22 E37 1 2
-SDATA23 SDATA22 L17 L18 -PLLBYPASSCLK
-SDATA24
G35
Q33
SDATA23 1 RSTCLK AN19
AL19 -CDICLK0 DIC0 -DICLK0 6 PLLBYPASSCLK
3
5
4
6
VCORE
-SDATA25 SDATA24 RSTCLK VCORE
N33 SDATA25 7 8
-SDATA26 L33 AL21 K7CLKOUT 10nH/6/5% 10nH/6/5%
-SDATA27 SDATA26 K7CLKOUT -K7CLKOUT
N35 SDATA27 K7CLKOUT AN21
-SDATA28 L37 C147 100/8P4R
SDATA28
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-SDATA29 J37 5P/4/N/50V
-SDATA30 SDATA29
A37 SDATA30 ANALOG AJ13
-SDATA31 E35
-SDATA32 SDATA31 SYSVREFMODE L1 L2 VCORE
E31 SDATA32 SYSVREFMODE AA5
-SDATA33 VREFSYS -CDICLK1 DIC1 RN2
E29 SDATA33 VREF_SYS W5 -DICLK1 6
-SDATA34 A27 1 2
-SDATA35 SDATA34 ZN 10nH/6/5% 10nH/6/5% -K7CLKOUT
A25 SDATA35 ZN AC5 3 4 VCORE
-SDATA36 E21 AE5 ZP K7CLKOUT 5 6 R8
-SDATA37 SDATA36 ZP C4 VCORE 100/6/1
C23 SDATA37 7 8
-SDATA38 C27 AJ25 -PLLBYPASS 5P/4/N/50V
C -SDATA39 SDATA38 PLLBYPASS PLLBYPASSCLK C
-SDATA40
A23
A35
SDATA39 2 PLLBYPASSCLK AN15
AL15 -PLLBYPASSCLK 100/8P4R VREFSYS
-SDATA41 SDATA40 PLLBYPASSCLK SL1 SL2
C35 SDATA41
-SDATA42 C33 AN13 PLLMON1 -CDICLK2 DIC2
SDATA42 PLLMON1 -DICLK2 6
-SDATA43 C31 AL13 PLLMON2 R9 BC1
-SDATA44 SDATA43 PLLMON2 -PLLTEST 10nH/6/5%/B 10nH/6/5%/B 100/6/1 1U/6/Y/10V
A29 SDATA44 PLLTEST AC3
-SDATA45 C29
-SDATA46 SDATA45 SC64 COREFB
E23 SDATA46
-SDATA47 C25 S1 SCANCLK1 5P/6/N/50V/B
-SDATA48 SDATA47 SCANCLK1 SCANCLK2 SC2
E17 SDATA48 SCANCLK2 S5
-SDATA49 E13 S3 SCANINTEVAL 4.7U/8/10V/B/X SC3
-SDATA50 SDATA49 SCANINTEVAL SCANSHIFTEN L5 L6 4.7U/8/10V/B/X
E11 SDATA50 SCANSHIFTEN Q5
-SDATA51 C15 -CDICLK3 DIC3 -COREFB
SDATA51 -DICLK3 6
-SDATA52 E9 AA1
-SDATA53 SDATA52 DBRDY -DBREQ 10nH/6/5% 10nH/6/5%
A13 SDATA53 DBREQ AA3
-SDATA54 -FLUSH
-SDATA55
C9
A9
SDATA54
3
SOCKETA FLUSH AL3
C6 0629 ADD APIC VCC25
-SDATA56 SDATA55 P_TCK 5P/4/N/50V 1003
C21 SDATA56 TCK Q1
-SDATA57 A21 U1 P_TDI
-SDATA58 SDATA57 TDI -PICD0 R10 330/6
E19 SDATA58 TDO U5
-SDATA59 P_TMS L19 L20 -PICD1 R11 330/6
C19 SDATA59 TMS Q3
-SDATA60 C17 U3 -P_TRST -CAICLK AIC
SDATA60 TRST -AICLK 6
-SDATA61 A11 FOR PC2001
-SDATA62 SDATA61 10nH/6/5% 10nH/6/5%
A17 SDATA62
-SDATA63 A15 L1 VID0 PICCLK0 SC18 10P/4/B/X
SDATA63 VID0 VID1 C148
VID1 L3
L5 VID2 5P/4/N/50V Put them inside socket462
-CDICLK0 VID2 VID3
W33 SDATAINCLK0 VID3 L7
-CDICLK1 J35 J7 VID4
-CDICLK2 SDATAINCLK1 VID4 VID[4..0]
E27 SDATAINCLK2 VID[4..0] 30
-CDICLK3 E15
B SDATAINCLK3 FID0 FID[0..3] B
FID0 W1 FID[0..3] 30
-DIVAL AN33 W3 FID1
6 -DIVAL SDATAINVAL FID1
Y1 FID2
-DOCLK0 FID2 FID3
6 -DOCLK[0:3] AE35 SDATAOUTCLK0 FID3 Y3
-DOCLK1 C37 VCORE
-DOCLK2 SDATAOUTCLK1 VCORE
A33 SDATAOUTCLK2
-DOCLK3 C11 U37 RN3
SDATAOUTCLK3 SCHECK0 P_TDI PLLMON1 R12 56/6
SCHECK1 Y33 6 5
R13 330/6 -DOVAL AL31 L35 -P_TRST 8 7 PLLMON2 R14 56/6
SDTATOUTVAL SCHECK2 P_TCK -PLLBYPASS R15 680/6
SCHECK3 E33 2 1
R16 680/6 AIN0 AJ29 E25 P_TMS 4 3 ZN R17 40.2/6/1
VCORE R18 680/6 AIN1 SADDIN0 SCHECK4
AL29 SADDIN1 SCHECK5 A31
-AI2 AG33 C13 470/8P4R -CPUINIT RN4 2 1 680/8P4R
-AI3 SADDIN2 SCHECK6 INTR
AJ37 SADDIN3 SCHECK7 A19 4 3
-AI4 AL35 -PLLTEST R19 470/6 -FLUSH 6 5
-AI5 SADDIN4 R20 1K/6/X -DBREQ R21 470/6 NMI
AE33 SADDIN5 SADDOUT0 J1 8 7
-AI6 AJ35 J3 R22 1K/6/X -SMI 4 3
-AI7 SADDIN6 SADDOUT1 -AO2 RN6 -IGNNE RN5
AG37 SADDIN7 SADDOUT2 C7 6 5 680/8P4R
-AI8 AL33 A7 -AO3 SCANINTEVAL 6 5 -STPCLK 8 7
-AI9 SADDIN8 SADDOUT3 -AO4 SCANCLK1 -A20M
AN37 SADDIN9 SADDOUT4 E5 4 3 2 1
-AI10 AL37 A5 -AO5 SCANCLK2 8 7
-AI11 SADDIN10 SADDOUT5 -AO6 SCANSHIFTEN
AG35 SADDIN11 SADDOUT6 E7 2 1
-AI12 AN29 C1 -AO7 COREFB R24 8.2K/6
-AI13 SADDIN12 SADDOUT7 -AO8 330/8P4R
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