Service Manuals, User Guides, Schematic Diagrams or docs for : Gigabyte GIGABYTE GIGABYTE 8I915ME-G - REV 1.03
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5 4 3 2 1
DATE:05/26-1
Model Name: 8I915ME-G Revision 1.03
SHEET TITLE SHEET TITLE
D D
01 COVER SHEET 23 PCI SLOT 1,2
02 BLOCK DIAGRAM 24 PCI SLOT 3
03 BOM & PCB MODIFY HISTORY 25 ITE8712HX
04 P4_LGA775_A 26 HWMO/FAN/FWH BIOS
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05 P4_LGA775_B 27 KB_MS
06 P4_LGA775_C 28 COM/LPT/FDD
C
07 P4_LGA775_D 29 (FRONT+REAR)USB/RING/IDE C
08 VCORE POWER 30 AC97 CODEC ALC655
09 GMCH-GRANTSDALE_HOST 31 AUDIO JACK
10 GMCH-GARNTSDALE_DDR 32 LAN RTL8110S/8100C
11 GMCH-GRANTSDALE_PCI E, DMI 33 ATX POWER CONN.
12 GMCH-GRANTSDALE_INT VGA 34 ALL POWER
13 GMCH-GRANTSDALE_GND 35 FRONT PANEL/BZ
14 GMCH-GRANTSDALE_PWR
B B
15 DDR CHANNEL A
16 DDR CHANNEL B Digitally signed by dd
17 DDR TERMINATION DN: cn=dd, o=dd, ou=dd,
18 FAN & WOL [email protected],
19 ICH6 PCI, USB, DMI, LAN
c=US
20 ICH6 IDE, GPIO, SATA, CTRL
Date: 2009.11.15 20:35:26
21 ICH6 VCC, GND
A
+07'00' A
22 CLK GEN
COMPONENT SIDE GIGABYTE
(1 oz. Copper)
VCC SIDE Title
(1 oz. Copper)
GND SIDE
Cover Sheet
(1 oz. Copper) Size Document Number Rev
SOLDER SIDE Custom GA-8I915ME-G 1.03
(1 oz. Copper)
Date: Tuesday, June 14, 2005 Sheet 1 of 36
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
INTEL Pentium4
LGA775
D
CLOCK GENERATOR D
VID0~4
PWM/OTHER POWER
VCORE = 1.75V / SLEEP : 1.3V PAGE 4, 5, 6,7
VCC3 VCORE = 1.75V (650-1100MHZ) / SLEEP : 1.3V
CKVDD = 3.3V PAGE 22 5VSB,-12V,+12V,VCC,VCC3,3VDUAL
VTT_DDR,2_5VSTR PAGE 8,33,34
CHANNEL A
DDR SDRAM DIMM X 1
GMCH 2_5VSTR = 2.5V(MEMORY,SUSPEND POWER)
PAGE 15
GRANTSDALE MAA0~14 VTT_DDR = 1.25V
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MAA_CPC1~5
MAB_CPC1~5
MDD0~63 CHANNEL B
-DQSD0~7
DM0~7
DDR SDRAM DIMM X1
2_5VSTR = 2.5V(MEMORY,SUSPEND POWER)
VCORE = 1.75V / SLEEP : 1.3V VTT_DDR = 1.25V PAGE 16
2_5VSTR = 2.5V(MEMORY)
VDDQ = 1.5V (AGP POWER 4X, HUBLINK) PAGE 9,10,11,12,13,14
C C
HL0~10
CONTROL BUS HUB LINK
IDE Primary
ICH6
VCC = 5V PAGE 29
USB PORTS 0~7 SERIAL ATA
VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I)
VCC = 5V 3VDUAL = 3.3V(SUSPEND POWER)
5VSB = 5V VCC3 = 3.3V
AMRUSB+ / - 5VUSB = 5V PAGE 29 RTCVDD = 3.3V VCC = 5V PAGE 20
PAGE 19,20,21
PCI BUS
B FWH/HWMO B
PCI SLOT
+12 = 12V
1,2,3 VCC = 5V
VCC3 = 3V PAGE 26
AZALIA -12 = -12V
LINK VCC = 5V
VCC3 = 3V
3VDUAL = 3V PAGE 23,24
LAN RTL8110S/8100C LPC BUS
AC97 LPC ITE8712IX
ALC655 PAGE 32
+12V = 12V
VCC3 = 3.3V VCC = 5V
VCC = 5V 5VSB = 5V
AVDD = 5V PAGE 30 VBAT = 3V PAGE 25
PAGE 35
A AUDIO PORTS : FRONT AUDIO I/O PORTS : A
LIN_ OUT LINE_IN MIC
TELE CD_IN AUX_IN COMA COMB LPT PS2 IR FDD
PAGE 31 PAGE 27,28,29
FRONT PANEL/BZ
VCC = 5V GIGABYTE
5VSB = 5V
+12 = 12V Title
PVCC = 5V PAGE 36 BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom GA-8I915ME-G 1.03
Date: Tuesday, June 14, 2005 Sheet 2 of 36
5 4 3 2 1
5 4 3 2 1
Model Name: 8I915ME-G Circuit or PCB layout change
for next version
Version: 1.03
PAGE Change Item Reason
D D
Component value change
history 2005/01/10
Data Change Item Reason
02/15 FROM 8IGV775-CH1 cost down rev:1.0
03/25 rev:1.02 for EMI & noise &F10 power issue
04/19 FROM 8I915ME-CH1 FOR DIST GV
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05/02 BOM:1.02A FOR 915G+8110S
05/02 BOM:1.02B FOXCON DIP CPU SOCKET for PVT
05/26 BOM:1.03C FOR 1G LAN 120M issue
C 05/30 BOM:1.03D FOR Lite Power inrush current C
06/14 BOM:1.03D FOR PVT
B B
A A
GIGABYTE
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom GA-8I915ME-G 1.03
Date: Tuesday, June 14, 2005 Sheet 3 of 36
5 4 3 2 1
5 4 3 2 1
VCORE
BC1 BC2 BC3 BC4 BC5
10U/12/X/6.3V/X 10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V/X 10U/12/X/6.3V
D VCORE D
BC6 BC7 BC8
10U/12/X/6.3V/X 10U/12/X/6.3V/X 10U/12/X/6.3V
U1A
HA[3..16]
[9] HA[3..16]
HA3 L5 D2 -HADS Closed to
A03# ADS# -HADS [9]
HA4 P6 C2 -BNR
HA5 M5
A04# BNR#
D4 -HIT
-BNR [9] Pin-H1
A05# HIT# -HIT [9]
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HA6 L4 H4 R1
HA7 A06# RSP# -BPRI 49.9/6/1 GTLREF
M4 A07# BPRI# G8 -BPRI [9] VTT_OR
HA8 R4 B2 -DBSY
A08# DBSY# -DBSY [9]
HA9 T5 C1 -DRDY
A09# DRDY# -DRDY [9]
HA10 U6 E4 -HITM BC11 R2 C3
A10# HITM# -HITM [9]
HA11 -IERR 0.01U/6/X/50V 100/6/1 1U/6/Y/10V
HA12
T4
U5
A11# IERR# AB2
P3 -HINIT
*
A12# INIT# -HINIT [20]
HA13 U4 C3 -HLOCK
A13# LOCK# -HLOCK [9]
HA14 V5 E3 -HTRDY C2
A14# TRDY# -HTRDY [9]
HA15 V4 AD3 33P/4/N/50V
HA16 A15# BINIT# -DEFER
W5 A16# DEFER# G7 -DEFER [9]
C N4 F2 -EDRDY C
RSVD EDRDY# -EDRDY [9]
P5 RSVD MCERR# AB3
-HREQ0 K4
[9] -HREQ0 REQ0#
-HREQ1 J5 U2
[9] -HREQ1 REQ1# AP0#
-HREQ2 M6 U3
[9] -HREQ2 REQ2# AP1#
-HREQ3 K6
[9] -HREQ3 REQ3#
-HREQ4 J6 F3 -BR0
[9] -HREQ4 REQ4# BR0# -BR0 [9]
-HADSTB0 R6 G3 TESTHI8
[9] -HADSTB0 ADSTB0# TESTHI08 TESTHI8 [5]
-HPCREQ G5 G4 TESTHI9
[9] -HPCREQ PCREQ# TESTHI09 TESTHI9 [5]
HA[17..31] H5 TESTHI10
[9] HA[17..31] TESTHI10 TESTHI10 [5]
HA17 AB6
HA18 A17#
W6 A18# DP0# J16
HA19 C1
Y6 A19# DP1# H15
HA20 Y4 H16 220P/4/N/50V
HA21 A20# DP2#
AA4 A21# DP3# J17
HA22 AD6
HA23 A22# GTLREF
AA5 A23# GTLREF H1 04/06
HA24 AB5
HA25 A24# -CPURST R6 62/6 -IERR
AC5 A25# RESET# G23 -CPURST [9] VTT_OL
HA26 AB4
HA27 A26# -RS0
AF5 A27# RS0# B3 -RS0 [9]
HA28 AF4 F5 -RS1 C4 R7 62/6 -BR0
A28# RS1# -RS1 [9] VTT_OL
HA29 AG6 A3 -RS2 22P/4/N/50V
A29# RS2# -RS2 [9]
SP-CAP X 4PCS HA30
HA31
AG4
AG5
A30# R8 62/6 -CPURST
A31# VTT_OL
AH4 A32#
AH5 A33#
AJ5 A34#
AJ6 A35#
AC4 RSVD
AE4 RSVD
B -HADSTB1 B
[9] -HADSTB1 AD5 ADSTB1#
CR
LGA775/D/[11SC1-920775-02R] CPU RETAINTION/X
VCORE
04/20 BOM
100U/2V/SPCAP 10U/12/X/6.3V X2
+
+
+
+
EC132 EC133 EC1 EC2
100U/2V/SPCAP[10CL3-201000-11]/X
100U/2V/SPCAP[10CL3-201000-11]/X EC3
100U/2V/SPCAP[10CL3-201000-11]/X
100U/2V/SPCAP[10CL3-201000-11]/X BC5/BC6
+
EC1 +
BC1/BC2
-
EC2
A BC3/BC4 A
+ 100U/2V/SPCAP
+
10U/12/X/6.3V X2 EC4
BC7/BC8 GIGABYTE
Title
P4_LGA775-A
Size Document Number Rev
Custom GA-8I915ME-G 1.03
Date: Tuesday, June 14, 2005 Sheet 4 of 36
5 4 3 2 1
5 4 3 2 1
Closed to VCC3
Pin-H2
R1697 R23 110/6/1 TESTHI0
Note: 49.9/6/1/X GTLREF1
VCC3
VTT_OR Place outside of CPU socket
VCCA & VCOREPLL R1675
R1669 R10 100/6/1 COMP2
define doesn't same as VTT_OL
BC621 R1698 C1339 249/6/1 R11 100/6/1 COMP3
VTT_GMCH old P4 design kit 0.01U/6/X/50V/X 100/6/1/X 1U/6/Y/10V/X 61.9/6/1
3
L1 C1333 C5 R14 60.4/6/1 COMP0
VCCA Q279 0.1U/6/Y/25V 0.1U/6/Y/25V R15 60.4/6/1 COMP1
10UH/0806/S/[10LI2-12100A-01_10LI2-12100A-02_10LI2-12100A-03_10LI2-12100A-04] D 2N7002/S
02/04 for layout R1699 60.4/6/1/X COMP2
C6 BC213 G S R1700 60.4/6/1/X COMP3
D D
1U/6/Y/10V 4.7U/8/Y/10V/X
2
1
VSSA Trace width doesn't TESTHI0
[7,9] GTL_DET
less than 12 Mil
C7 BC214 RN103
L2 1U/6/Y/10V 4.7U/8/Y/10V/X 470/8P4R
VCOREPLL 7 8 FSBSEL0
VTT_GMCH
10UH/0806/S/[10LI2-12100A-01_10LI2-12100A-02_10LI2-12100A-03_10LI2-12100A-04] U1C 5 6 FSBSEL2
As close as possible to 3 4 FSBSEL1
1 2
CPU socket -SMI P2 F26 TESTHI0
[20] -SMI SMI# TESTHI00
-A20M K3 W3 TESTHI1 R22 62/6 TESTHI2_7
[20] -A20M A20M# TESTHI01
-FERR R3 P1 TESTHI11
[20] -FERR FERR#/PBE# TESTHI11
INTR K1 W2 TESTHI12
[20] INTR LINT0 TESTHI12
NMI L1 F25
[20] NMI LINT1 TESTHI02
-IGNNE N2 G25 R24 62/6 -THRMTRIP
[20] -IGNNE IGNNE# TESTHI03
-STPCLK M3 G27 Locate at ICH6 Side
[20] -STPCLK STPCLK# TESTHI04
G26 R25 62/6 -FERR
TESTHI05
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VCCA A23 G24
VSSA VCCA TESTHII06 TESTHI2_7
B23 VSSA TESTHI07 F24
D23 AK6 -FORCEPR
RSVD FORCEPR# -FORCEPR [36]
VCOREPLL C23 G6 RSVD_G6
VCCIOPLL RSVD R26 62/6/X RSVD_G6
VTT_OL
VID0 AM2 L2 -CPUSLP
VID0 SLP# -CPUSLP [20]
VID[0..5] VID1 AL5 AH2 R27 62/6 TESTHI12
[8] VID[0..5] VID1 RSVD
VID2 AM3 N1 CPUPWROK
VID2 PWRGOOD CPUPWROK [20]
VID3 AL6 AL2 -PROCHOT R29 62/6 TESTHI1
VID3 PROCHOT# -PROCHOT [36]
VID4 AK4 M2 -THRMTRIP
VID4 THERMTRIP# -THRMTRIP [20]
VID5 AL4
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