Service Manuals, User Guides, Schematic Diagrams or docs for : Gigabyte GIGABYTE GIGABYTE 8I915P DUO - REV 1.4
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>> Download GIGABYTE 8I915P DUO - REV 1.4 documenatation <<
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5 4 3 2 1
Model Name: 8I915P DUO
REV1.4
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SHEET TITLE SHEET TITLE
tia
D D
01 COVER SHEET 23 PCI SLOT
02 BLOCK DIAGRAM 24 PCI EXPRESS*1 SLOT
03 BOM & PCB MODIFY HISTORY 25 ITE8712HX
en
04 P4_LGA775_A 26 HWMO/FAN/FWH BIOS
05 P4_LGA775_B 27 KB_MS/GAME
id
06 P4_LGA775_C 28 COM/LPT/FDD
C
07 P4_LGA775_D 29 (FRONT+REAR)USB/RING/IDE C
08 VCORE POWER 30 AZALIA CODEC ALC880/CMI9880
nf
09 GMCH-GRANTSDALE_HOST 31 AUDIO JACK
10 GMCH-GARNTSDALE_DDR 32 LAN BCM5705E/5751
co
11 GMCH-GRANTSDALE_PCI E, DMI 33 LAN BCM5751
12 GMCH-GRANTSDALE_INT VGA 34 ATX POWER CONN.
13 GMCH-GRANTSDALE_GND 35 ALL POWER
14 GMCH-GRANTSDALE_PWR e 36 1394 TSB43AB23
B B
15 DDR CHANNEL A 37 FRONT PANEL/BZ
yt
16 DDR CHANNEL B 38 RAID VIA6410
17 DDR TERMINATION 39 RAID IDE CONNECTOR
ab
18 PCI EXPRESS*16 SLOT 40 GPIO TABLE
19 ICH6 PCI, USB, DMI, LAN 41 RESET TABLE
20 ICH6 IDE, GPIO, SATA, CTRL
ig
21 ICH6 VCC, GND
A A
22 CLK GEN
G
COMPONENT SIDE GIGABYTE
(1 oz. Copper)
VCC SIDE Title
(1 oz. Copper)
GND SIDE
Cover Sheet
(1 oz. Copper) Size Document Number Rev
SOLDER SIDE
(1 oz. Copper)
Custom 8I915P DUO 1.4
Date: Thursday, April 07, 2005 Sheet 1 of 41
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
INTEL Pentium4
LGA775
l
tia
D
CLOCK GENERATOR D
VID0~4
PWM/OTHER POWER
VCORE = 1.75V / SLEEP : 1.3V PAGE 4, 5, 6,7
VCC3 VCORE = 1.75V (650-1100MHZ) / SLEEP : 1.3V
CKVDD = 3.3V PAGE 22 5VSB,-12V,+12V,VCC,VCC3,3VDUAL
VTT_DDR,2_5VSTR PAGE 8,34,35
en
CHANNEL A
DDRII DIMM X 1
GMCH DDRI DIMM X 1
GAD0~31 2_5VSTR = 2.5V(MEMORY,SUSPEND POWER)
ADSTB0,ADSTB0- MAA0~14 VTT_DDR = 1.25V PAGE 15,17
ADSTB1,ADSTB1-
GRANTSDALE MAA_CPC1~5
SBA0~7 MAB_CPC1~5
PCI EXPRESS SBSTB,SBSTB- MDD0~63 CHANNEL B
BY 16 PORTS -DQSD0~7 DDRII DIMM X 1
id
VDDQ = 1.5V (AGP POWER 4X) GCBE0~3- DDRI DIMM X 1
VCC3 = 3.3V DM0~7
+12V = 12V ST0~2
3VDUAL = 3.3V 2_5VSTR = 2.5V(MEMORY,SUSPEND POWER)
VCC = 5V PAGE 18 VCORE = 1.75V / SLEEP : 1.3V VTT_DDR = 1.25V PAGE 16,17
2_5VSTR = 2.5V(MEMORY)
VDDQ = 1.5V (AGP POWER 4X, HUBLINK) PAGE 9,10,11,12,13,14
C C
AGPUSB+ / -
nf
HL0~10
CONTROL BUS
HUB LINK
IDE Primary
ICH6
co
VCC = 5V PAGE 29
USB PORTS 0~7 SERIAL ATA
VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I)
VCC = 5V 3VDUAL = 3.3V(SUSPEND POWER)
5VSB = 5V VCC3 = 3.3V
AMRUSB+ / - 5VUSB = 5V PAGE 29 RTCVDD = 3.3V VCC = 5V PAGE 20
PAGE 19,20,21
AZALIA
B
AC97/Azalia
LINK
PCI BUS
e PCI SLOT
PCI EXPRESS SLOT
FWH/HWMO B
yt
VCC = 5V
+12 = 12V VCC3 = 3V PAGE 26
-12 = -12V
ALC880/CMI9880
+12V = 12V
VCC = 5V
VCC3 = 3V
3VDUAL = 3V PAGE 23,24
VCC3 = 3.3V
VCC = 5V
AVDD = 5V PAGE 30
LAN BCM5721/5751
ab
LPC BUS
LPC ITE8712HX
AUDIO PORTS : FRONT AUDIO PAGE 32,33
LIN_ OUT LINE_IN MIC VCC = 5V
5VSB = 5V
VBAT = 3V PAGE 25
TELE CD_IN AUX_IN
PAGE 31 1394 IT TSB43AB23
ig
PAGE 36
A I/O PORTS : A
RAID VIA6410 COMA COMB LPT PS2 IR FDD
G
PAGE 27,28,29
FRONT PANEL/BZ
VCC = 5V PAGE 38,39 GIGABYTE
5VSB = 5V
+12 = 12V Title
PVCC = 5V PAGE 37 BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 8I915P DUO 1.4
Date: Thursday, April 07, 2005 Sheet 2 of 41
5 4 3 2 1
5 4 3 2 1
Model Name: 8I915P DUO Circuit or PCB layout change
Version: 1.4 for next version
l
PAGE Change Item Reason
tia
D 0317 LIB CHANGE D
Component value change
2004/05/19
2004/05/19
history
Data Change Item Reason
en
0317 ADD 2ND SOUSE *** *** *********************************
L10 1UH/8/180mA/S(10LI2-07100B-01/10LI2-041001-04) 1UH/8/180mA/S(10LI2-07100B-01/10LI2-041001-04/10LI2-07100B-11)
L15 1UH/8/180mA/S(10LI2-07100B-01/10LI2-041001-04) 1UH/8/180mA/S(10LI2-07100B-01/10LI2-041001-04/10LI2-07100B-11)
Q190 SUD50N024-09P/APM2014N/IRLR3715/TO252 10IF4-083918-01R_10IF4-492409-01R_10IF4-098880-10R/TO252
Q191 SUD50N024-09P/APM2014N/IRLR3715/TO252 10IF4-083918-01R_10IF4-492409-01R_10IF4-098880-10R/TO252
Q42 SUD50N024-09P/TO252 10IF4-083918-01R_10IF4-492409-01R_10IF4-098880-10R/TO252
Q44 SUD50N024-09P/TO252 10IF4-083918-01R_10IF4-492409-01R_10IF4-098880-10R/TO252
LIB CHANGE *** *** *********************************
id
DL2 0.6uH/D/30A/5018/3PM/(TAI/EMC) 0.6uH/TO-5018/40A/1P/[11LC5-40600C-D1]
DL3 0.6uH/D/30A/5018/3PM/(TAI/EMC) 0.6uH/TO-5018/40A/1P/[11LC5-40600C-D1]
DL4 0.6uH/D/30A/5018/3PM/(TAI/EMC) 0.6uH/TO-5018/40A/1P/[11LC5-40600C-D1]
DL5 0.6uH/D/30A/5018/3PM/(TAI/EMC) 0.6uH/TO-5018/40A/1P/[11LC5-40600C-D1]
L1 10UH/8/100mA/S(10LI2-00100A-01/02/03) 10UH//120mA/8/S/[10LI2-12100A-01_10LI2-12100A-02_10LI2-12100A-03_10LI2-12100A-13]
C L2 10UH/8/100mA/S(10LI2-00100A-01/02/03) 10UH//120mA/8/S/[10LI2-12100A-01_10LI2-12100A-02_10LI2-12100A-03_10LI2-12100A-13] C
0401 Q187 ADD 2ND SOURCE 10GL6-501085-01R
nf
0407 N/B VERSION CHANGE TO C2 10HB1-032915-25
co
B
e B
yt
ab
ig
A A
GIGABYTE
G
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 8I915P DUO 1.4
Date: Thursday, April 07, 2005 Sheet 3 of 41
5 4 3 2 1
5 4 3 2 1
VCORE
BC1 BC4 BC5
10U/12/X/6.3V/X 10U/12/X/6.3V 10U/12/X/6.3V/X
l
tia
D VCORE D
BC6 BC7 BC8 BC9 BC10
10U/12/X/6.3V 10U/12/X/6.3V/X 10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V/X
en
U1A
HA[3..16]
(9) HA[3..16]
HA3 L5 D2 -HADS Closed to
A03# ADS# -HADS (9)
HA4 P6 C2 -BNR
A04# BNR# -BNR (9) Pin-H1
HA5 M5 D4 -HIT
A05# HIT# -HIT (9)
HA6 L4 H4 R1
HA7 A06# RSP# -BPRI 49.9/6/1 GTLREF
M4 A07# BPRI# G8 -BPRI (9) VTT_OR
HA8 R4 B2 -DBSY
A08# DBSY# -DBSY (9)
HA9 T5 C1 -DRDY
A09# DRDY# -DRDY (9)
HA10 U6 E4 -HITM BC11 R2 C3
A10# HITM# -HITM (9)
HA11 -IERR 0.01U/6/X/50V 100/6/1 1U/6/Y/10V
T4 AB2 *
id
HA12 A11# IERR# -HINIT
U5 A12# INIT# P3 -HINIT (20)
HA13 U4 C3 -HLOCK
A13# LOCK# -HLOCK (9)
HA14 V5 E3 -HTRDY C2
A14# TRDY# -HTRDY (9)
HA15 V4 AD3 33P/4/N/50V
HA16 A15# BINIT# -DEFER
W5 A16# DEFER# G7 -DEFER (9)
C N4 F2 -EDRDY C
RSVD EDRDY# -EDRDY (9)
P5 RSVD MCERR# AB3
-HREQ0 K4
(9) -HREQ0 REQ0#
-HREQ1 J5 U2
(9) -HREQ1 REQ1# AP0# TP_CPU1
nf
-HREQ2 M6 U3
(9) -HREQ2 REQ2# AP1# TP_CPU2
-HREQ3 K6
(9) -HREQ3 REQ3#
-HREQ4 J6 F3 -BR0
(9) -HREQ4 REQ4# BR0# -BR0 (9)
-HADSTB0 R6 G3 TESTHI8
(9) -HADSTB0 ADSTB0# TESTHI08 TESTHI8 (5)
-HPCREQ G5 G4 TESTHI9
HA[17..31] (9) -HPCREQ PCREQ# TESTHI09 TESTHI9 (5)
H5 TESTHI10
(9) HA[17..31] TESTHI10 TESTHI10 (5)
HA17 AB6
HA18 A17#
W6 A18# DP0# J16 TP_CPU3
HA19 C1
Y6 A19# DP1# H15 TP_CPU4
HA20 Y4 H16 220P/4/N/25V
A20# DP2# TP_CPU5
HA21 AA4 J17
co
A21# DP3# TP_CPU6
HA22 AD6 R1539 62/6/X -IERR
A22# VTT_OR
HA23 AA5 H1 GTLREF
HA24 A23# GTLREF
AB5 A24#
HA25 AC5 G23 -CPURST R6 62/6 -IERR
A25# RESET# -CPURST (9) VTT_OL
HA26 AB4
HA27 A26# -RS0
AF5 A27# RS0# B3 -RS0 (9)
HA28 AF4 F5 -RS1 C4 R7 62/6 -BR0
A28# RS1# -RS1 (9) VTT_OL
SP-CAP X 4PCS HA29
HA30
AG6
AG4
A29# RS2# A3 -RS2
-RS2 (9)
22P/4/N/50V
HA31 A30# R8 62/6 -CPURST
AG5 A31# VTT_OL
AH4 A32#
VCORE AH5 A33#
AJ5 A34#
AJ6 A35#
AC4 RSVD
AE4
e
+
+
B SEC1 SEC2 -HADSTB1 AD5 RSVD B
(9) -HADSTB1 ADSTB1#
100U/4V/SPCAP/X
LGA775
100U/4V/SPCAP/X
yt
VCORE
+
+
+
+
EC1 EC2 EC129 EC130
100U/4V/SPCAP/9m/X 100U/4V/SPCAP/9m/X
ab
100U/4V/SPCAP/X 100U/4V/SPCAP/X CR
CPU RETAINTION/X
ig
A A
GIGABYTE
G
Title
P4_LGA775-A
Size Document Number Rev
Custom 8I915P DUO 1.4
Date: Thursday, April 07, 2005 Sheet 4 of 41
5 4 3 2 1
5 4 3 2 1
VCC3
Note:
Place outside of CPU socket
VCCA & VCOREPLL R1538 R1593
249/6/1 49.9/6/1/X GTLREF1 R10 100/6/1 COMP2
define doesn't same as VTT_OR VTT_OL
R11 100/6/1 COMP3
3
VTT_GMCH old P4 design kit
10UH//120mA/8/S/[10LI2-12100A-01_10LI2-12100A-02_10LI2-12100A-03_10LI2-12100A-13] R23
L1 Q262 R1594 C1290 C5 R14 60.4/6/1 COMP0
l
VCCA D 110/6/1 100/6/1/X 1U/6/Y/10V/X 0.1U/6/Y/25V R15 60.4/6/1 COMP1
2N7002/SOT23
G S
tia
D C6 BC213 R17 SOT23 R1595 60.4/6/1/X COMP2 D
(7,9) GTL_DET
2
1
1U/6/Y/10V 4.7U/8/Y/10V 0/SHT/X TESTHI0 R1596 60.4/6/1/X COMP3
VSSA Trace width doesn't
R1224 C439
less than 12 Mil 61.9/6/1 0.1U/6/Y/25V
C7 BC214 RN103
L2 1U/6/Y/10V 4.7U/8/Y/10V 470/8P4R
VCOREPLL 7 8 FSBSEL0
VTT_GMCH
U1C 5 6 FSBSEL2
10UH//120mA/8/S/[10LI2-12100A-01_10LI2-12100A-02_10LI2-12100A-03_10LI2-12100A-13]
As close as possible to 3 4 FSBSEL1
1 2
CPU socket -SMI P2 F26 TESTHI0
(20) -SMI SMI# TESTHI00
en
-A20M K3 W3 TESTHI1 R22 62/6 TESTHI2_7
(20) -A20M A20M# TESTHI01
-FERR R3 P1 TESTHI11
(20) -FERR FERR#/PBE# TESTHI11
INTR K1 W2 TESTHI12
(20) INTR LINT0 TESTHI12
NMI L1 F25
(20) NMI LINT1 TESTHI02
FSBSEL1 -IGNNE N2 G25 R24 62/6 -THRMTRIP
(20) -IGNNE IGNNE# TESTHI03
-STPCLK M3 G27 Locate at ICH6 Side
(20) -STPCLK STPCLK# TESTHI04
VCC G26 R25 62/6 -FERR
TESTHI05
3
VCCA A23 G24
Q278 VSSA VCCA TESTHII06 TESTHI2_7
D
B23 VSSA TESTHI07 F24
R1598 D23 AK6 -FORCEPR
RSVD RSVD -FORCEPR (37)
2N7002/SOT23 VCOREPLL C23 G6 RSVD_G6
8.2K/6 G S VCCIOPLL RSVD R26 62/6/X RSVD_G6
VTT_OL
VID0 AM2 L2 -CPUSLP
id
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