Service Manuals, User Guides, Schematic Diagrams or docs for : Gigabyte GIGABYTE GIGABYTE GA-M55PLUS-S3G - REV 2.1
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GA-M55plus-S3G
SHEET TITLE SHEET TITLE Revision:2.1
01 COVER SHEET 26 CODEC ALC883
02 BOM & PCB MODIFY HISTORY 27 AUDIO JACK, L_OUT, F_AUDIO
03 BLOCK DIAGRAM 28 H/W MONITOR & FAN CONTROL
04 PROCESSOR HT INTERFACE 29 IDE1/IDE2/FDD
05 PROCESSOR DDR2 INTERFACE 30 PWM ISL6566
06 PROCESSOR DDR2 INTERFACE 31 COMA, LPT PORT
07 PROCESSOR CONTROL & DEBUG 32 DDR18V,DDRVTT,5VDAUL,VCC12, POWER
08 DIMM 1,2 33 POWER SEQUENCE
09 DIMM 3,4 34 BIOS ATX POWER CONNCTOR
10 DIMM TERMINATION 35 FRONT PANEL
11 C51 CPU 36 ITE 8716GB/CX
12 C51 HT 37 Marvell 88E1116
13 C51 PCI-EXPRESS 38 TI TSB43AB23 1394
14 C51 RGB
15 C51 PWR/GND
16 MCP51 HT BUS
17 MCP51 PCI BUS/CLOCK/RESET
18 MCP51 SATA/IDE
19 MCP51 AZILIA/USB
20 MCP51 RGMII
21 MCP51 PWR/GND
22 PCI EXPRESS X16 SLOT
23 F_USB1/F_USB2 CONN /PCI_E x1 SLOT
24 PCI 1,2,3 SLOT GIGABYTE
Title
25 PCI 4 SLOT BLOCK DIAGRAM
Size Document Number Rev
Custom 2.1
GA-M55plus-S3G
Date: Monday, September 04, 2006 Sheet 1 of 38
5 4 3 2 1
Model Name:GA-M55plus-S3G
Circuit or PCB layout change for next version
Component value change history Version:2.1
P-Code: Date Change Item Reason
D
Date Change Item Reason 2006.03.17 0.1 Gerber Out D
2006.03.22 0.1 New BOM Release. PCB:0.1
2006.04.14 1.0 Gerber Out Rename to GA-M55plus-S3G
2006.04.18 1.0A D_BOM Release. PCB:1.0 LAN_USB remove 11NR6-702010-A1R Remove BIOS socket
2006.06.06 1.1 Gerber Out Modify DVI I2C PU ,74LVC08A change to SOIC
TPM no POP, Remove BIOS socket RM use plastic, F_PANEL use color
2006.06.13 1.2 Gerber Out Change VDDA25 generate method.
Remove Power LED dual color schematic Add AMD Validation circuit
2006.08.17 2.1 Gerber Out Copy from 1.2 change to 2.1
2006.05.02 1.0B P_BOM Release. PCB:1.0 RM change to orange. PCIE x16 change to blue. 11AC1-021164-81R
CPU fan speed. 15K-->8.2K Update new packing list BC7 for EMI
2006.05.08 1.0B ECN Release. PCB:1.0 Add VGA cap: 12PC1-V00001-01R, and Q74 2nd source.
2006.06.07 1.1A E_BOM Release. PCB:1.1 Modify DVI I2C PU ,74LVC08A change to SOIC
2006.06.12 1.2A E_BOM Release. PCB:1.2 Change VDDA25 generate method.
2006.06.28 1.2A P_BOM Release. PCB:1.2 For PVT use. Add packing list.
C C
2006.07.07 1.2B P_BOM Release. PCB:1.2 Add ESD protect diode.
2006.08.29 2.1A P_BOM Release. PCB:2.1 Change NB to NBP chip, and add packing list
2006.09.04 2.1A ECN Release. PCB:2.1 Change driver CD.
2006.09.04 2.1B P_BOM Release. PCB:2.1 Fix ON_0FF safe mode.
B B
A A
GIGABYTE
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 2.1
GA-M55plus-S3G
Date: Monday, September 04, 2006 Sheet 2 of 38
5 4 3 2 1
BLOCK DIAGRAM
DDRII SDRAM CONN 1 1L
POWER
SUPPLY VREG
CONNECTOR 128-BIT 200/266/333/400MHZ DDRII SDRAM CONN 2 1H
AMD K8 CPU
SOCKET AM2
DDRII SDRAM CONN 3 2L
DDRII SDRAM CONN 4 2H
HT 16X16 1GHZ
NVIDIA
C51G
HT 8X8 1GHZ PCI SLOT 1
PRIMARY IDE
PCI SLOT 2
ATA 133 PCI 33MHZ
SECONDARY IDE
INTEGRATED SATA
NVIDIA AZILIA RTL883 CODEC
SATA2 CONN x4
MCP51
USB2.0 X8 PORT
FLOPPY CONN LPC BUS 33MHZ
SIO
PS2/KB CONN
BACK PANEL
PARALLEL CONN USB2.0 PORTS 0-1
X2/1394
SERIAL CONN 4MB FLASH USB2.0 PORTS 2-3
X2/GBIT LAN
FRONT PANEL
USB2.0 PORTS 4-5
USB2.0 PORTS 6-7
GIGABYTE
Title
BLOCK DIAGRAM
Size Document Number Rev
Custom 2.1
GA-M55plus-S3G
Date: Monday, September 04, 2006 Sheet 3 of 38
CPU_VDD_RUN = VCORE
L0_CADIN_L[0..15]
CPU_VDDA_RUN = VDDA25
L0_CADIN_L[0..15] <11>
L0_CADIN_H[0..15]
L0_CADIN_H[0..15] <11>
VLDT_RUN = VCC12_HT
L0_CLKIN_L[0..1]
L0_CLKIN_H[0..1]
L0_CLKIN_L[0..1] <11> CPU_VDDIO_SUS = DDR18V
L0_CLKIN_H[0..1] <11>
L0_CADOUT_L[0..15]
L0_CADOUT_L[0..15] <11>
CPU_VTT_SUS = DDRVTT
L0_CADOUT_H[0..15]
L0_CADOUT_H[0..15] <11>
L0_CLKOUT_L[0..1]
L0_CLKOUT_L[0..1] <11> VLDT_A = VCC12_HT
L0_CLKOUT_H[0..1]
L0_CLKOUT_H[0..1] <11> VLDT_B = HT12B
M2CPUA
HYPERTRANSPORT
L0_CLKIN_H1 N6 AD5 L0_CLKOUT_H1
L0_CLKIN_L1 L0_CLKIN_H(1) L0_CLKOUT_H(1) L0_CLKOUT_L1
P6 L0_CLKIN_L(1) L0_CLKOUT_L(1) AD4
L0_CLKIN_H0 N3 AD1 L0_CLKOUT_H0
L0_CLKIN_L0 L0_CLKIN_H(0) L0_CLKOUT_H(0) L0_CLKOUT_L0
N2 L0_CLKIN_L(0) L0_CLKOUT_L(0) AC1
VCC12_HT R3 49.9/4/1 V4 Y6 1
R4 49.9/4/1 L0_CTLIN_H(1) L0_CTLOUT_H(1) TP78
GND V5 L0_CTLIN_L(1) L0_CTLOUT_L(1) W6 1 TP79
L0_CTLIN_H0 U1 W2 L0_CTLOUT_H0
<11> L0_CTLIN_H0 L0_CTLIN_H(0) L0_CTLOUT_H(0) L0_CTLOUT_H0 <11>
L0_CTLIN_L0 V1 W3 L0_CTLOUT_L0
<11> L0_CTLIN_L0 L0_CTLIN_L(0) L0_CTLOUT_L(0) L0_CTLOUT_L0 <11>
L0_CADIN_H15 U6 Y5 L0_CADOUT_H15
L0_CADIN_L15 L0_CADIN_H(15) L0_CADOUT_H(15) L0_CADOUT_L15
V6 L0_CADIN_L(15) L0_CADOUT_L(15) Y4
L0_CADIN_H14 T4 AB6 L0_CADOUT_H14
L0_CADIN_L14 L0_CADIN_H(14) L0_CADOUT_H(14) L0_CADOUT_L14
T5 L0_CADIN_L(14) L0_CADOUT_L(14) AA6
L0_CADIN_H13 R6 AB5 L0_CADOUT_H13
L0_CADIN_L13 L0_CADIN_H(13) L0_CADOUT_H(13) L0_CADOUT_L13
T6 L0_CADIN_L(13) L0_CADOUT_L(13) AB4
L0_CADIN_H12 P4 AD6 L0_CADOUT_H12
L0_CADIN_L12 L0_CADIN_H(12) L0_CADOUT_H(12) L0_CADOUT_L12
P5 L0_CADIN_L(12) L0_CADOUT_L(12) AC6
L0_CADIN_H11 M4 AF6 L0_CADOUT_H11
L0_CADIN_L11 L0_CADIN_H(11) L0_CADOUT_H(11) L0_CADOUT_L11
M5 L0_CADIN_L(11) L0_CADOUT_L(11) AE6
L0_CADIN_H10 L6 AF5 L0_CADOUT_H10
L0_CADIN_L10 L0_CADIN_H(10) L0_CADOUT_H(10) L0_CADOUT_L10
M6 L0_CADIN_L(10) L0_CADOUT_L(10) AF4
L0_CADIN_H9 K4 AH6 L0_CADOUT_H9
L0_CADIN_L9 L0_CADIN_H(9) L0_CADOUT_H(9) L0_CADOUT_L9
K5 L0_CADIN_L(9) L0_CADOUT_L(9) AG6
L0_CADIN_H8 J6 AH5 L0_CADOUT_H8
L0_CADIN_L8 L0_CADIN_H(8) L0_CADOUT_H(8) L0_CADOUT_L8
K6 L0_CADIN_L(8) L0_CADOUT_L(8) AH4
L0_CADIN_H7 U3 Y1 L0_CADOUT_H7
L0_CADIN_L7 L0_CADIN_H(7) L0_CADOUT_H(7) L0_CADOUT_L7
U2 L0_CADIN_L(7) L0_CADOUT_L(7) W1
L0_CADIN_H6 R1 AA2 L0_CADOUT_H6
L0_CADIN_L6 L0_CADIN_H(6) L0_CADOUT_H(6) L0_CADOUT_L6
T1 L0_CADIN_L(6) L0_CADOUT_L(6) AA3
L0_CADIN_H5 R3 AB1 L0_CADOUT_H5
L0_CADIN_L5 L0_CADIN_H(5) L0_CADOUT_H(5) L0_CADOUT_L5
R2 L0_CADIN_L(5) L0_CADOUT_L(5) AA1
L0_CADIN_H4 N1 AC2 L0_CADOUT_H4
L0_CADIN_L4 L0_CADIN_H(4) L0_CADOUT_H(4) L0_CADOUT_L4
P1 L0_CADIN_L(4) L0_CADOUT_L(4) AC3
L0_CADIN_H3 L1 AE2 L0_CADOUT_H3
L0_CADIN_L3 L0_CADIN_H(3) L0_CADOUT_H(3) L0_CADOUT_L3
M1 L0_CADIN_L(3) L0_CADOUT_L(3) AE3
L0_CADIN_H2 L3 AF1 L0_CADOUT_H2
L0_CADIN_L2 L0_CADIN_H(2) L0_CADOUT_H(2) L0_CADOUT_L2
L2 L0_CADIN_L(2) L0_CADOUT_L(2) AE1
L0_CADIN_H1 J1 AG2 L0_CADOUT_H1
L0_CADIN_L1 L0_CADIN_H(1) L0_CADOUT_H(1) L0_CADOUT_L1
K1 L0_CADIN_L(1) L0_CADOUT_L(1) AG3
L0_CADIN_H0 J3 AH1 L0_CADOUT_H0
L0_CADIN_L0 L0_CADIN_H(0) L0_CADOUT_H(0) L0_CADOUT_L0
J2 L0_CADIN_L(0) L0_CADOUT_L(0) AG1
SOCKET_M2 M2/[12KRC-04K807-41R]
GIGABYTE
Title
CPU HYPER TRANSPORT
Size Document Number Rev
Custom 2.1
GA-M55plus-S3G
Date: Monday, September 04, 2006 Sheet 4 of 38
M2CPUB M2CPUC
MEMORY INTERFACE A MEMORY INTERFACE B
DCLKA2 AG21 AE14 MDA63 DCLKB2 AJ19 AH13 MDB63
<8,10> DCLKA2 MA0_CLK_H(2) MA_DATA(63) MDA[0..63] <8,9> <8,10> DCLKB2 MB0_CLK_H(2) MB_DATA(63) MDB[0..63] <8,9>
-DCLKA2 AG20 AG14 MDA62 -DCLKB2 AK19 AL13 MDB62
<8,10> -DCLKA2 MA0_CLK_L(2) MA_DATA(62) <8,10> -DCLKB2 MB0_CLK_L(2) MB_DATA(62)
DCLKA1 G19 AG16 MDA61 DCLKB1 A18 AL15 MDB61
<8,10> DCLKA1 MA0_CLK_H(1) MA_DATA(61) <8,10> DCLKB1 MB0_CLK_H(1) MB_DATA(61)
-DCLKA1 H19 AD17 MDA60 -DCLKB1 A19 AJ15 MDB60
<8,10> -DCLKA1 MA0_CLK_L(1) MA_DATA(60) <8,10> -DCLKB1 MB0_CLK_L(1) MB_DATA(60)
DCLKA0 U27 AD13 MDA59 DCLKB0 U31 AF13 MDB59
<8,10> DCLKA0 MA0_CLK_H(0) MA_DATA(59) <8,10> DCLKB0 MB0_CLK_H(0) MB_DATA(59)
-DCLKA0 U26 AE13 MDA58 -DCLKB0 U30 AG13 MDB58
<8,10> -DCLKA0 MA0_CLK_L(0) MA_DATA(58) <8,10> -DCLKB0 MB0_CLK_L(0) MB_DATA(58)
AG15 MDA57 AL14 MDB57
MA_DATA(57) MDA56 MB_DATA(57) MDB56
<8,10> -CSA1 AC25 MA0_CS_L(1) MA_DATA(56) AE16 <8,10> -CSB1 AE30 MB0_CS_L(1) MB_DATA(56) AK15
AA24 AG17 MDA55 AC31 AL16 MDB55
<8,10> -CSA0 MA0_CS_L(0) MA_DATA(55) <8,10> -CSB0 MB0_CS_L(0) MB_DATA(55)
AE18 MDA54 AL17 MDB54
MODT_A0 AC28 MA_DATA(54) MDA53 MODT_B0 AD29 MB_DATA(54) MDB53
<8,10> MODT_A0 MA0_ODT(0) MA_DATA(53) AD21 <8,10> MODT_B0 MB0_ODT(0) MB_DATA(53) AK21
AG22 MDA52 AL21 MDB52
DCLKA5 MA_DATA(52) MDA51 DCLKB5 MB_DATA(52) MDB51
<9,10> DCLKA5 AE20 MA1_CLK_H(2) MA_DATA(51) AE17 <9,10> DCLKB5 AL19 MB1_CLK_H(2) MB_DATA(51) AH15
-DCLKA5 AE19 AF17 MDA50 -DCLKB5 AL18 AJ16 MDB50
<9,10> -DCLKA5 MA1_CLK_L(2) MA_DATA(50) <9,10> -DCLKB5 MB1_CLK_L(2) MB_DATA(50)
DCLKA4 G20 AF21 MDA49 DCLKB4 C19 AH19 MDB49
<9,10> DCLKA4 MA1_CLK_H(1) MA_DATA(49) <9,10> DCLKB4 MB1_CLK_H(1) MB_DATA(49)
-DCLKA4 G21 AE21 MDA48 -DCLKB4 D19 AL20 MDB48
<9,10> -DCLKA4 MA1_CLK_L(1) MA_DATA(48) <9,10> -DCLKB4 MB1_CLK_L(1) MB_DATA(48)
DCLKA3 V27 AF23 MDA47 DCLKB3 W29 AJ22 MDB47
<9,10> DCLKA3 MA1_CLK_H(0) MA_DATA(47) <9,10> DCLKB3 MB1_CLK_H(0) MB_DATA(47)
-DCLKA3 W27 AE23 MDA46 -DCLKB3 W28 AL22 MDB46
<9,10> -DCLKA3 MA1_CLK_L(0) MA_DATA(46) <9,10> -DCLKB3 MB1_CLK_L(0) MB_DATA(46)
AJ26 MDA45 AL24 MDB45
MA_DATA(45) MDA44 MB_DATA(45) MDB44
<9,10> -CSA3 AD27 MA1_CS_L(1) MA_DATA(44) AG26 <9,10> -CSB3 AE29 MB1_CS_L(1) MB_DATA(44) AK25
AA25 AE22 MDA43 AB31 AJ21 MDB43
<9,10> -CSA2 MA1_CS_L(0) MA_DATA(43) <9,10> -CSB2 MB1_CS_L(0) MB_DATA(43)
AG23 MDA42 AH21 MDB42
MODT_A1 AC27 MA_DATA(42) MDA41 MODT_B1 AD31 MB_DATA(42) MDB41
<9,10> MODT_A1 MA1_ODT(0) MA_DATA(41) AH25 <9,10> MODT_B1 MB1_ODT(0) MB_DATA(41) AH23
AF25 MDA40 AJ24 MDB40
MA_DATA(40) MDA39 MB_DATA(40) MDB39
MA_DATA(39) AJ28 MB_DATA(39) AL27
-SCASA AB25 AJ29 MDA38 -SCASB AC29 AK27 MDB38
<8,9,10> -SCASA MA_CAS_L MA_DATA(38) <8,9,10> -SCASB MB_CAS_L MB_DATA(38)
-SWEA AB27 AF29 MDA37 -SWEB AC30 AH31 MDB37
<8,9,10> -SWEA MA_WE_L MA_DATA(37) <8,9,10> -SWEB MB_WE_L MB_DATA(37)
-SRASA AA26 AE26 MDA36 -SRASB AB29 AG30 MDB36
<8,9,10> -SRASA MA_RAS_L MA_DATA(36) <8,9,10> -SRASB MB_RAS_L MB_DATA(36)
AJ27 MDA35 AL25 MDB35
SBAA2 MA_DATA(35) MDA34 SBAB2 MB_DATA(35) MDB34
<8,9,10> SBAA2 N25 MA_BANK(2) MA_DATA(34) AH27 <8,9,10> SBAB2 N31 MB_BANK(2) MB_DATA(34) AL26
SBAA1 Y27 AG29 MDA33 SBAB1 AA31 AJ30 MDB33
<8,9,10> SBAA1 MA_BANK(1) MA_DATA(33) <8,9,10> SBAB1 MB_BANK(1) MB_DATA(33)
SBAA0 AA27 AF27 MDA32 SBAB0 AA28 AJ31 MDB32
<8,9,10> SBAA0 MA_BANK(0) MA_DATA(32) <8,9,10> SBAB0 MB_BANK(0) MB_DATA(32)
E29 MDA31 E31 MDB31
CKEA1 MA_DATA(31) MDA30 CKEB1 MB_DATA(31) MDB30
<9,10> CKEA1 L27 MA_CKE(1) MA_DATA(30) E28 <9,10> CKEB1 M31 MB_CKE(1) MB_DATA(30) E30
CKEA0 M25 D27 MDA29 CKEB0 M29 B27 MDB29
<8,10> CKEA0 MA_CKE(0) MA_DATA(29) <8,10> CKEB0 MB_CKE(0) MB_DATA(29)
C27 MDA28 A27 MDB28
MAAA15 MA_DATA(28) MDA27 MAAB15 MB_DATA(28) MDB27
M27 MA_ADD(15) MA_DATA(27) G26 N28 MB_ADD(15) MB_DATA(27) F29
<8,9,10> MAAA[0..15] MAAA14 N24 F27 MDA26 <8,9,10> MAAB[0..15] MAAB14 N29 F31 MDB26
MAAA13 MA_ADD(14) MA_DATA(26) MDA25 MAAB13 MB_ADD(14) MB_DATA(26) MDB25
AC26 MA_ADD(13) MA_DATA(25) C28 AE31 MB_ADD(13) MB_DATA(25) A29
MAAA12 N26 E27 MDA24 MAAB12 N30 A28 MDB24
MAAA11 MA_ADD(12) MA_DATA(24) MDA23 MAAB11 MB_ADD(12) MB_DATA(24) MDB23
P25 MA_ADD(11) MA_DATA(23) F25 P29 MB_ADD(11) MB_DATA(23) A25
MAAA10 Y25 E25 MDA22 MAAB10 AA29 A24 MDB22
MAAA9 MA_ADD(10) MA_DATA(22) MDA21 MAAB9 MB_ADD(10) MB_DATA(22) MDB21
N27 MA_ADD(9) MA_DATA(21) E23 P31 MB_ADD(9) MB_DATA(21) C22
MAAA8 R24 D23 MDA20 MAAB8 R29 D21 MDB20
MAAA7 MA_ADD(8) MA_DATA(20) MDA19 MAAB7 MB_ADD(8) MB_DATA(20) MDB19
P27 MA_ADD(7) MA_DATA(19) E26 R28 MB_ADD(7) MB_DATA(19) A26
MAAA6 R25 C26 MDA18 MAAB6 R31 B25 MDB18
MAAA5 MA_ADD(6) MA_DATA(18) MDA17 MAAB5 MB_ADD(6) MB_DATA(18) MDB17
R26 MA_ADD(5) MA_DATA(17) G23 R30 MB_ADD(5) MB_DATA(17) B23
MAAA4 R27 F23 MDA16 MAAB4 T31 A22 MDB16
MAAA3 MA_ADD(4) MA_DATA(16) MDA15 MAAB3 MB_ADD(4) MB_DATA(16) MDB15
T25 MA_ADD(3) MA_DATA(15) E22 T29 MB_ADD(3) MB_DATA(15) B21
MAAA2 U25 E21 MDA14 MAAB2 U29 A20 MDB14
MAAA1 MA_ADD(2) MA_DATA(14) MDA13 MAAB1 MB_ADD(2) MB_DATA(14) MDB13
T27 MA_ADD(1) MA_DATA(13) F17 U28 MB_ADD(1) MB_DATA(13) C16
MAAA0 W24 G17 MDA12 MAAB0 AA30 D15 MDB12
MA_ADD(0) MA_DATA(12) MDA11 MB_ADD(0) MB_DATA(12) MDB11
MA_DATA(11) G22 MB_DATA(11) C21
DQSA7 AD15 F21 MDA10 DQSB7 AK13 A21 MDB10
-DQSA7 MA_DQS_H(7) MA_DATA(10) MDA9 -DQSB7 MB_DQS_H(7) MB_DATA(10) MDB9
AE15 MA_DQS_L(7) MA_DATA(9) G18 AJ13 MB_DQS_L(7) MB_DATA(9) A17
DQSA6 AG18 E17 MDA8 DQSB6 AK17 A16 MDB8
-DQSA6 MA_DQS_H(6) MA_DATA(8) MDA7 -DQSB6 MB_DQS_H(6) MB_DATA(8) MDB7
AG19 MA_DQS_L(6) MA_DATA(7) G16 AJ17 MB_DQS_L(6) MB_DATA(7) B15
DQSA5 AG24 E15 MDA6 DQSB5 AK23 A14 MDB6
-DQSA5 MA_DQS_H(5) MA_DATA(6) MDA5 -DQSB5 MB_DQS_H(5) MB_DATA(6) MDB5
AG25 MA_DQS_L(5) MA_DATA(5) G13 AL23 MB_DQS_L(5) MB_DATA(5) E13
DQSA4 AG27 H13 MDA4 DQSB4 AL28 F13 MDB4
-DQSA4 MA_DQS_H(4) MA_DATA(4) MDA3 -DQSB4 MB_DQS_H(4) MB_DATA(4) MDB3
AG28 MA_DQS_L(4) MA_DATA(3) H17 AL29 MB_DQS_L(4) MB_DATA(3) C15
-DQSA[0..8] DQSA3 D29 E16 MDA2 -DQSB[0..8] DQSB3 D31 A15 MDB2
-DQSA[0..8] <8,9> MA_DQS_H(3) MA_DATA(2) -DQSB[0..8] <8,9> MB_DQS_H(3) MB_DATA(2)
-DQSA3 C29 E14 MDA1 -DQSB3 C31 A13 MDB1
DQSA[0..8] DQSA2 MA_DQS_L(3) MA_DATA(1) MDA0 DQSB[0..8] DQSB2 MB_DQS_L(3) MB_DATA(1) MDB0
DQSA[0..8] <8,9> C25 MA_DQS_H(2) MA_DATA(0) G14 DQSB[0..8] <8,9> C24 MB_DQS_H(2) MB_DATA(0) D13
-DQSA2 D25 -DQSB2 C23
DQSA1 MA_DQS_L(2) DQSB1 MB_DQS_L(2)
E19 MA_DQS_H(1) MA_DQS_H(8) J28 D17 MB_DQS_H(1) MB_DQS_H(8) J31
-DQSA1 F19 J27 -DQSB1 C17 J30
DQSA0 MA_DQS_L(1) MA_DQS_L(8) DQSB0 MB_DQS_L(1) MB_DQS_L(8)
F15 MA_DQS_H(0) C14 MB_DQS_H(0)
-DQSA0 G15 J25 -DQSB0 C13 J29
MA_DQS_L(0) MA_DM(8) MB_DQS_L(0) MB_DM(8)
DMA[0:8] DMA7 AF15 K25 DMB[0..8] DMB7 AJ14 K29
DMA[0..8] <8,9> MA_DM(7) MA_CHECK(7) DMB[0..8] <8,9> MB_DM(7) MB_CHECK(7)
DMA6 AF19 J26 DMB6 AH17 K31
DMA5 MA_DM(6) MA_CHECK(6) DMB5 MB_DM(6) MB_CHECK(6)
AJ25 MA_DM(5) MA_CHECK(5) G28 AJ23 MB_DM(5) MB_CHECK(5) G30
DMA4 AH29 G27 DMB4 AK29 G29
DMA3 MA_DM(4) MA_CHECK(4) DMB3 MB_DM(4) MB_CHECK(4)
B29 MA_DM(3) MA_CHECK(3) L24 C30 MB_DM(3) MB_CHECK(3) L29
DMA2 E24 K27 DMB2 A23 L28
DMA1 MA_DM(2) MA_CHECK(2) DMB1 MB_DM(2) MB_CHECK(2)
E18 MA_DM(1) MA_CHECK(1) H29 B17 MB_DM(1) MB_CHECK(1) H31
DMA0 H15 H27 DMB0 B13 G31
MA_DM(0) MA_CHECK(0) MB_DM(0) MB_CHECK(0)
GIGABYTE
Title
CPU DDRII MEMORY
Size Document Number Rev
Custom 2.1
GA-M55plus-S3G
Date: Monday, September 04, 2006 Sheet 5 of 38
DDR18V VDDA25
-CPURST_C R21 300/4 -CPURST R26 1K/4
CPU_PWRGD_C R22 300/4 CPU_PWRGD R33 1K/4
HTSTOP_L_C R23 300/4 -HTSTOP_L R36 1K/4
DDR18V
VDDA25 FB1 30/6/4A/S DDR18V
U3D
14
C3 C13 C4
12 4.7u/8/Y5V/10V/Z 0.22u/6/X5R/10V/K
11 M2CPUD
2
4
6
8
13 3.3n/4/X7R/50V/K MISC
74LVC08AD/SO14[10TC1-117408-01R_10TC1-117408-02R] GND C10 RN251 R65 R56 R57
3.9n/4/X7R/50V/K GND VDDA1 300/8P4R/X 300/4 300/4
D10 VDDA2
DDR18V CPUCLK0_H C1 CLKIN_H 300/4/X
7
<11> CPUCLK0_H
GND A8
1
3
5
7
R5 CLKIN_H
B8 CLKIN_L
<11> CPUCLK0_L CPUCLK0_L C2 169/4/1CLKIN_L
GND U3A CPU_PWRGD_C C9 D2 CPU_VID5 3VDUAL
14
PWROK VID(5) VID5 <30>
3.9n/4/X7R/50V/K HTSTOP_L_C D8 D1 CPU_VID4
LDTSTOP_L VID(4) VID4 <30>
<12,16> -HTMCP_PWRGD -HTMCP_PWRGD 1 -CPURST_C C7 C1 CPU_VID3
RESET_L VID(3) VID3 <30>
3 CPU_PWRGD_C E3 CPU_VID2
VID(2) VID2 <30>
CPU_PWRGD 2 ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo