Service Manuals, User Guides, Schematic Diagrams or docs for : HAIER LCD L32V6-A8K haier_l32v6_a8k_scd_435
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5 4 3 2 1
TA1- 5 4 TA1-- TC1- 5 4 TC1--
TA1+ 6 3 TA1++ TC1+ 6 3 TC1++
Y1_G TB1- TB1-- TCLK1- TCLK1--
U1A SVP_CX32 7 2 7 2
C1 100pF TB1+ 8 1 TB1++ TCLK1+ 8 1 TCLK1++
PR1_G TV_G
C2 0.1uF 169 40 TD1+ LP1 DLP31DN900ML4 LP2 DLP31DN900ML4
R1 TV_V CVBS1 TD1P
Y1_G C3 100pF_DNS 41 TD1-
PB1_G TD1M
HD_Y1 C4 0.1uF 180
C5 100pF_DNS Y_G1 TC1+ TD1- TD1--
Y2_G A/H_GND TC1P 44 5 4
0R_DNS C6 0.1uF 181 45 TC1- TD1+ 6 3 TD1++
A/H_Y Y_G2 TC1M
USE COPPER C7 100pF 7 2
D PR2_G AV_TO_CX_G D
AV_TO_CX C8 0.1uF 182 48 TB1+ 8 1
R2 1K_DNS Y_G3 TB1P TB1-
PB2_G PC_GIN_G TB1M 49
C9 0.1uF 183 LP3 DLP31DN900ML4
VGA_GIN PC_G
50 TA1+
PC_RIN_G TA1P
PR1_G C10 100pF_DNS 51 TA1-
C11 0.1uF TA1M
PC_GIN_G HD_PR1 188 PR_R1
A/H_GND C12 100pF_DNS 42 TCLK1+
C13 0.1uF TCLK1P TCLK1-
A/H_PR
C14 100pF
189 PR_R2 TCLK1M 43 3.3V POWER LVDS33
VGA_GND PC_BIN_G S/Y1_G
S/Y1
C15 0.1uF 190 PR_R3
FOR LVDS FB1
R4 1K_DNS 46 CX_LVDS_VDD 1 2
PC_RIN_G LVDSVCC
C16 0.1uF 191
VGA_RIN PC_R
C17 100pF C19 C20 C21 C22 + 150_Ohm_600mA
USE COPPER
R414 0R_DNS S/C1
S/Y1_G
C18 0.1uF 192 C
SVP-CX32_208 LVDSGND 47
0.1uF 0.1uF 0.1uF 10uF/16V
AV_TO_CX_G PB1_G C23 100pF_DNS
C24 0.1uF
(1/4) CX_LVDS_VSS
HD_PB1 196 PB_B1 PLL_VCC 39
C25 100pF_DNS
A/H_PB
A/H_GND
C27 100pF
C26 0.1uF 197 PB_B2
ANALOG I/O
38
S/Y2/V2
S/Y2_G
C28 0.1uF 198 PB_B3
LVDS & MISC PLL_GND
C30 20pF
C29 0.1uF 199 52
VGA_BIN PC_B LVDS_VDDP
C C
PC_BIN_G R5 1K_DNS
R6
171 204 1M_DNS
FS1 XTALO Y1 LAYOUT: Place xtal
170 14.318MHz C33 20pF
C34 100pF FS2 circuit as compact
S/Y2_G XTALI 205
173 and close to chip
S/C2 FB1
as possible
C35 0.1uF 172 159
FB2 AIN_VS VGA_VSIN
CX_VREFN_1
158
CX_VREFP_1
AIN_HS VGA_HSIN
CX_VREFP_1 174
C36 VREFP_1 R7 4k7->470R
TESTMODE 157
CX_VREFN_1 175 3V_SDA 3V_SCL
VREFN_1 3V_SDA 3V_SCL
0.1uF_DNS
C37 C38 CX_VREFP_2 184 163 R8 75R R9 R10
VREFP_2 CVBS_OUT1 CX_CVBS_OUT1
0.1uF 0.1uF PVDD 68R 68R
CX_VREFN_2 185 162
VREFN_2 CVBS_OUT2
R11 0R_DNS
CX_VREFN_2
CX_VREFP_2
CX_VD33
B C39 R12 0R CN1 B
ODSEL1 1 2
0.1uF_DNS 3 4
C40 C41 R401 0R U37 PVDD 5 6
+12V 7 8
1 S1 D1 8 9 10
0.1uF 0.1uF R402 0R 2 7
S2 D2 TD1++ 11 12 TD1--
3 S3 D3 6 13 14
R403 0R_DNS R407 4 5 TCLK1++ TCLK1--
CX_VD33 10K G D4 TC1++ 15 16 TC1--
R404 0R_DNS C438 TB1++ 17 18 TB1--
CEM9435A TA1++ 19 20 TA1--
R405 0R_DNS 1nF 21 22
VCC 23 24
R406 0R_DNS 12X2 2mm
R410
R412 0R_DNS 1K panel
DEFINITION Pin Name VCC-USB
Power for
R413 0R_DNS PVDD
PVDD
YPbPr1 Y_G1,PB_B1,PR_R1
3
R408
1 Q16
USB/YPbPr2 Y_G2,PB_B2,PR_R2 PANEL_PWR
C439 +
S/YC_1 PR_R3,C 10K
R409
10K
MMBT3904 0.1uF
PRELIMINARY
2
A A
S/YC_2 PB_B3,FB2 C440
22uF/16V Fuzhou Walasey Technology Limited Company
TUNER CVBS1
Title
AV1-4 SWITCH Y_G3 BLOCK DIAGRAM
NC FS2 Size Document Number Rev
B 50TR05A FLAT PANEL TV_MAIN 1.0
VGA_RGB PC_R,PC_G,PC_B
Date: Monday, February 27, 2006 Sheet 1 of 21
5 4 3 2 1
5 4 3 2 1
VCC
CX_VD33
R15
E_PWM
R16
R17 0R_DNS
4K7
1K5 U1B SVP_CX32 uP_A[0..7]
D R18 1K 100RX4 D
BRT_CNTL 8051_A0
64 RP1 4 5 uP_A0
ADDR0
3
R19 10K R418 65 8051_A1 3 6 uP_A1
CX_PWM0 8K2 + C42 C43 CX_PWM0 ADDR1 8051_A2 uP_A2
1 55 PWM0 ADDR2 66 2 7
Q1 67 8051_A3 1 8 uP_A3
MMBT3904 10uF/16V 0.1uF ADDR3 8051_A4 RP2
ADDR4 68 4 5 100RX4 uP_A4
C44 CX_SCL 8051_A5 uP_A5
2
57 SCL ADDR5 69 3 6
70 8051_A6 2 7 uP_A6
100pF CX_SDA ADDR6 8051_A7 uP_A7
58 SDA ADDR7 71 1 8 uP_AD[0..7]
83 8051_AD0 1 8 uP_AD0
CX_GPIO0 A_D0 8051_AD1 uP_AD1
60 GPIO0 A_D1 82 2 7
CX_GPIO1 59 81 8051_AD2 RP3 3 6 100RX4 uP_AD2
GPIO1 A_D2 8051_AD3 uP_AD3
A_D3 80 4 5
79 8051_AD4 1 8 uP_AD4
A_D4 8051_AD5 uP_AD5
8051_WR# 62 WR# A_D5 78 2 7
77 8051_AD6 RP4 3 6 100RX4 uP_AD6
A_D6 8051_AD7 uP_AD7
63 76 4 5
8051_RD# RD#
SVP-CX32_208 A_D7
61
8051_CS2CX
CX_INT# 56
CS
INTN
(2/4) DP0
DP1
37
36
DP0
DP1
DP2
DP0
DP1
I2C Slave Address is 35
C fixed to 0x7e/0x7f 8051_ALE 84 ALE
CPU INTERFACE DP2
DP3 34 DP3
DP4
DP2
DP3 C
33
R22 100R CX_SDA
5V_SB DIGITAL OUT DP4
DP5 32 DP5
DP6
DP4
DP5
3V_SDA RESET_H 86 RESET DP6 31 DP6
R23 100R CX_SCL 30 DP7
3V_SCL DP7 DP8 DP7
DP8 29 DP8
85 26 DP9
V5SF DP9 DP10 DP9
DP10 25 DP10
C45 24 DP11
DP11 DP12 DP11
C46 C47 22
DP12 DP13 DP12
68pF_DNS DP_HS- 4 21
DHS_2EX DP_HS DP13 DP14 DP13
68pF_DNS 0.1uF 18
DP14 DP15 DP14
DP_VS- 5 17
DVS_2EX DP_VS DP15 DP16 DP15
DP16 16 DP16
DP_CLK- 23 15 DP17
CLK_2EX DP_CLK DP17 DP18 DP17
DP18 14 DP18
DP_DE_FLD- 6 11 DP19
FIELD DP_DE_FLD DP19 DP20 DP19
DP20 10 DP20
9 DP21
DP21 DP22 DP21
3.3V_SB 8
DP22 DP23 DP22
DP23 7 DP23
R24 4K7_DNS
CX_GPIO0
B R25 4K7 B
3.3V_SB
R26 4K7_DNS
CX_GPIO1
R27 4K7
Pin Name Pin No. 1 (HIGH) 0 (LOW)
A GPIO0 MPU in A/D Multiplix Mode MPU in A/D Separate Mode A
GPIO1 Use Rising Edge of WR# to latch data Use Falling Edge of WR# to latch data
Fuzhou Walasey Technology Limited Company
Title
BLOCK DIAGRAM
Size Document Number Rev
PRELIMINARY B 50TR05A FLAT PANEL TV_MAIN 1.0
Date: Monday, February 27, 2006 Sheet 2 of 21
5 4 3 2 1
5 4 3 2 1
CX_DQM0 R28 15R DQM1
A11
CX_DQM1 R29 15R DQM0
CX_DQM2 R30 15R DQM2 CX_MA11 R31 0R
CX_BA0
CX_DQM3 R32 15R DQM3 CX_WE#
CX_CAS#
CX_RAS#
CX_MCLK
CX_CLKE
D RP5 0RX4 D
U1C SVP_CX32 CX_MD7 4 5 DQ8
CX_MD6 DQ9
67
68
19
18
17
22
23
3 6
CX_MA0 124 155 CX_MD0 CX_MD5 2 7 DQ10 U2 2Mx32_SDRAM
CX_MA1 MA0 MD0 CX_MD1 CX_MD4 DQ11 DQM0 CX_MA0
123 154 1 8 16 A0 25
CKE
CLK
RAS
CAS
WE
BA0
BA1
CX_MA2 MA1 MD1 CX_MD2 DQM1 DQM0 CX_MA1
122 MA2 MD2 153 71 DQM1 A1 26
CX_MA3 121 152 CX_MD3 RP6 0RX4 DQM2 28 CX_MA2
CX_MA4 MA3 MD3 CX_MD4 CX_MD3 DQ12 DQM3 DQM2 A2 27 CX_MA3
118 MA4 MD4 151 4 5 59 DQM3 A3 60
CX_MA5 117 150 CX_MD5 CX_MD2 3 6 DQ13 CX_MA4
CX_MA6 MA5 MD5 CX_MD6 CX_MD1 DQ14 DQ0 A4 61 CX_MA5
116 MA6 MD6 149 2 7 2 DQ0 A5 62
CX_MA7 115 148 CX_MD7 CX_MD0 1 8 DQ15 DQ1 4 63 CX_MA6
CX_MA8 MA7 MD7 DQ2 DQ1 A6 CX_MA7
114 MA8 5 DQ2 A7 64
CX_MA9 113 145 CX_MD8 RP7 0RX4 DQ3 7 65 CX_MA8
CX_MA10 MA9 MD8 CX_MD9 CX_MD15 DQ0 DQ4 DQ3 A8 CX_MA9
125 MA10 MD9 144 4 5 8 DQ4 A9 66
CX_MA11 126 143 CX_MD10 CX_MD14 3 6 DQ1 DQ5 10 CX_MA10 CX_VDDM
MA11 MD10 CX_MD11 CX_MD13 DQ2 DQ6 DQ5 A10/AP 24
142 2 7 11
CX_DQM0
SVP-CX32_208 MD11
MD12 141 CX_MD12
CX_MD13
CX_MD12 1 8 DQ3 DQ7
DQ8
13
DQ6
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