Service Manuals, User Guides, Schematic Diagrams or docs for : HP CQ56 Pavilion G56 DAAX3MB16A1 623909-001 rev-a AX3E-DDR2
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1 2 3 4 5 6 7 8
PCB STACK UP Wimbledon AX3/5 BLOCK DIAGRAM 01
6L
A A
B B
C C
Azalia
Realtek
RTL8103EL
PAGE 29
D D
PROJECT :AX3
Quanta Computer Inc.
Size Document Number Rev
Custom 2A
Block Diagram
NB5 Date: Friday, January 29, 2010 Sheet 1 of 30
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3V
L26
9,17,27,28 +1.05V
9,11,17,19,28,30 +3V
02
+3V_CK_MAIN
HCB1608KF-181T15_6
U10
C365 C360 C331 C361 C348 C329
10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 +3V_CK_MAIN 23 61
A VDDPLL3 CPUCLKT0 CLK_CPU_BCLK 3 A
16 VDD48 CPUCLKC0 60 CLK_CPU_BCLK# 3
L28
9
4
VDDPCI
VDDREF
CK505 CPUCLKT1
58 CLK_MCH_BCLK 5
+3V_CK_CPU 46 57
VDDSRC CPUCLKC1 CLK_MCH_BCLK# 5
HCB1608KF-181T15_6 +3V_CK_CPU 62
VDDCPU
CPUT2_ITP/SRCT8 54
C376 C370 +3V_CK_MAIN2 19 53
10U/6.3V_8 0.1U/10V_4 VDD96I/O CPUC2_ITP/SRCC8
27
VDDPLL3I/O
10/21 Montevina
33 VDDSRCI/O DOTT_96/SRCT0 20 DREFCLK 6
43 21 DREFCLK# 6
VDDSRCI/O DOTC_96/SRCC0
52 VDDSRCI/O
L22 24
27MHz_Nonss/SRCCLK1/SE1 DREFSSCLK
+3V_CK_MAIN2 56 25
VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2 DREFSSCLK#
HCB1608KF-181T15_6 55 NC
28
C333 C330 C342 C374 C332 C373 C353 SRCCLKT2/SATACL
29
10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 CG_XIN SRCCLKC2/SATACL
3 X1
CG_XOUT 2 31
X2 SRCCLKT3/CR#_C
32
SRCCLKC3/CR#_D
34 CLK_PCIE_3GPLL
R183 *100K/F_4 SRCCLKT4
SRCCLKC4 35 CLK_PCIE_3GPLL#
+3V 16 CK_PWG 63 45
+3V CK_PWRGD/PD# PCI_STOP# PM_STPPCI# 16
CPU_BSEL1 R181 2.2K_4 FSB 64 44
FSLB/TEST_MODE CPU_STOP# PM_STPCPU# 16
48 CLK_PCIE_ICH 15
SRCCLKT6
SRCCLKC6 47 CLK_PCIE_ICH# 15
2
R165 R157 10,11 CGCLK_SMB 7 51
SCLK SRCCLKT7/CR#_F CLK_PCIE_WLAN
2
B R164 Q9 10K/F_4 10K/F_4 6 50 B
10,11 CGDAT_SMB SDATA SRCCLKC7/CR#_E CLK_PCIE_WLAN# 21
10K/F_4 2N7002E
16 PDAT_SMB 3 1 CGDAT_SMB 37
1
SRCCLKT9 CLK_PCIE_LAN 20
22 GND SRCCLKC9 38 CLK_PCIE_LAN# 20
TME 26 GND
18 GND48 SRCCLKT10 41 CLK_PCIE_SATA 14
59 GNDCPU SRCCLKC10 42 CLK_PCIE_SATA# 14
+3V 15
GNDPCI
1 40
GNDREF SRCCLKT11/CR#_H
30 39
GNDSRC SRCCLKC11/CR#_G
2
Q8 36
2N7002E GNDSRC
49
CGCLK_SMB GNDSRC
16 PCLK_SMB 3 1 8
PCICLK0/CR#_A R_CLK_MCH_OE# R160 475/F_4
10 CLK_MCH_OE# 6
PCICLK1/CR#_B TME R158 33_4
PCICLK2/TME 11 PCLK_DEBUG 21
12 R_PCLK_KBC R155 33_4 PCLK_KBC
PCICLK3 27M_SEL
0=overclocking PCICLK4/27_SELECT
13
of CPU and Y3
65 ITP_EN R152 33_4 PCLK_ICH 15
CG_XIN 1 CG_XOUT EPAD
SRC Allowed 2
14 R147 22_4 CLK_48M_USB 16
PCI_F5/ITP_EN R148 22_4
1 = overclocking 14.318MHZ CLK_48M_CR 18
1
1
17 FSA R149 2.2K_4 CPU_BSEL0
of CPU and SRC C367 C372 USB_48MHZ/FSLA R171 10K/F_4 CPU_BSEL2
5 FSC R172 33_4
not Allowed 33P/50V_4 33P/50V_4 CLK_14M_ICH 16
2
2
FSLC/TST_SL/REF
ICS9LPRS355BKLF MLF64
+3V
C
DB:Change from 27P to 33P(TXC suggestion) C
CK505 QFN64
2
des R153 27M_SEL Silego SLG8SP513VTR AL8SP513000
*10K/F_4 PIN20 PIN21 PIN24 PIN25 +3V
PIN13 Realtek RTM875N-606-VD-GR AL000875000
1
27M_SEL CLK_MCH_OE# R161 10K/F_4
ICS ICS9LPRS355BKLFT ALPRS355000
2
0=UMA DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100
int R156
10K/F_4 1 = External
SRCT0 SRCC0 27Mout-NSS 27Mout-SS
1
VGA
0=UMA PCLK_KBC
1 = External VGA C336 *33P/50V_4
C328 *27P/50V_4 PCLK_ICH
CPU Clock select FSC FSB FSA CPU SRC PCI
+3V C338 *33P/50V_4 PCLK_DEBUG
CPU_BSEL0 R142 *0_4/S
1 0 1 100 100 33
3 CPU_BSEL0 MCH_BSEL0 6
short0402 0 0 1 133 100 33 C314 *10P/50V_4 CLK_48M_USB
0 1 1 166 100 33 C315 *10P/50V_4 CLK_48M_CR
*10K/F_4 R145 *1K/F_4
R150 0 1 0 200 100 33 C354 *33P/50V_4 CLK_14M_ICH
R_PCLK_KBC 3 CPU_BSEL1 CPU_BSEL1 R184 *0_4/S MCH_BSEL1 6
D short0402 D
0 0 0 266 100 33 for EMI
ITP_EN
R182 *1K/F_4
1 0 0 333 100 33
+1.05V
R159 1 1 0 400 100 33
10K/F_4 *10K/F_4 3 CPU_BSEL2 CPU_BSEL2 R169 *0_4/S MCH_BSEL2 6
R154 short0402 1 1 1 RSVD 100 33 PROJECT :AX3
R168 *1K/F_4
1K to NB only when
XDP is implement.No
Quanta Computer Inc.
+1.05V
Enable ITP CLK XDP can use 0 ohm
Size Document Number Rev
Custom 2A
Clock Generator
NB5 Date: Tuesday, February 23, 2010 Sheet 2 of 30
1 2 3 4 5 6 7 8
5 4 3 2 1
5 H_A#[35:3]
H_A#3
H_A#4
J4
L5
U18A
A[3]# ADS#
H1
E2
H_ADS# 5
5 H_D#[63:0]
H_D#0 E22
U18B
Y22 H_D#32
H_D#[63:0]
03
A[4]# BNR# H_BNR# 5 D[0]# D[32]#
ADDR GROUP 0
ADDR GROUP 0
H_A#5 L4 G5 H_D#1 F24 AB24 H_D#33
A[5]# BPRI# H_BPRI# 5 D[1]# D[33]#
H_A#6 K5 H_D#2 E26 V24 H_D#34
H_A#7 A[6]# H_D#3 D[2]# D[34]# H_D#35
M3 H5 H_DEFER# 5 G22 V26
H_A#8 A[7]# DEFER# H_D#4 D[3]# D[35]# H_D#36
N2 F21 H_DRDY# 5 F23 V23
H_A#9 A[8]# DRDY# H_D#5 D[4]# D[36]# H_D#37
J1 E1 H_DBSY# 5 G25 T22
D H_A#10 A[9]# DBSY# H_D#6 D[5]# D[37]# H_D#38 D
N3 A[10]# E25 D[6]# D[38]# U25
DATA GRP 0
DATA GRP 2
DATA GRP 2
H_A#11 P5 F1 H_D#7 E23 U23 H_D#39
A[11]# BR0# HBREQ#0 5 D[7]# D[39]#
H_A#12 P2 H_D#8 K24 Y25 H_D#40
A[12]# D[8]# D[40]#
CONTROL
H_A#13 L2 D20 H_IERR# R83 49.9/F_4 +1.05V H_D#9 G24 W22 H_D#41
H_A#14 A[13]# IERR# H_D#10 D[9]# D[41]# H_D#42
P4 B3 H_INIT# 14 J24 Y23
H_A#15 A[14]# INIT# H_D#11 D[10]# D[42]# H_D#43
P1 A[15]# J23 D[11]# D[43]# W24
H_A#16 R1 H4 H_D#12 H22 W25 H_D#44
A[16]# LOCK# H_LOCK# 5 D[12]# D[44]#
5 H_ADSTB#0 M1 H_D#13 F26 AA23 H_D#45
ADSTB[0]# H_CPURST# 5 D[13]# D[45]#
5 H_REQ#[4:0] C1 H_D#14 K22 AA24 H_D#46
H_REQ#0 RESET# H_RS#0 H_D#15 D[14]# D[46]# H_D#47
K3 F3 H23 AB25
H_REQ#1 REQ[0]# RS[0]# H_RS#1 D[15]# D[47]#
H2 REQ[1]# RS[1]# F4 5 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 5
H_REQ#2 K2 G3 H_RS#2 H_RS#[2:0] 5 5 H_DSTBP#0 H26 AA26
REQ[2]# RS[2]# DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
H_REQ#3 J3 G2 5 H_DINV#0 H25 U22
REQ[3]# TRDY# H_TRDY# 5 DINV[0]# DINV[2]# H_DINV#2 5
H_REQ#4 L1
H_A#[35:3] REQ[4]# H_D#[63:0] H_D#[63:0]
G6 H_HIT# 5
H_A#17 HIT# H_D#16 H_D#48
Y2 E4 H_HITM# 5 N22 AE24
H_A#18 A[17]# HITM# H_D#17 D[16]# D[48]# H_D#49
U5 A[18]# K25 D[17]# D[49]# AD24
ADDR GROUP 1
ADDR GROUP 1
H_A#19 R3 AD4 H_D#18 P26 AA21 H_D#50
H_A#20 A[19]# BPM[0]# H_D#19 D[18]# D[50]# H_D#51
W6 AD3 R23 AB22
A[20]# BPM[1]# D[19]# D[51]#
XDP/ITP SIGNALS
H_A#21 U4 AD1 H_D#20 L23 AB21 H_D#52
H_A#22 A[21]# BPM[2]# H_D#21 D[20]# D[52]# H_D#53
Y5
A[22]# BPM[3]#
AC4 01/06 MV del TP for ESD. M24
D[21]# D[53]#
AC26
DATA GRP 1
DATA GRP 3
H_A#23 U1 AC2 H_D#22 L22 AD20 H_D#54
H_A#24 A[23]# PRDY# H_D#23 D[22]# D[54]# H_D#55
R4 A[24]# PREQ# AC1 M23 D[23]# D[55]# AE22
H_A#25 T5 AC5 ITP_TCK H_D#24 P25 AF23 H_D#56
H_A#26 A[25]# TCK ITP_TDI H_D#25 D[24]# D[56]# H_D#57
T3 A[26]# TDI AA6 P23 D[25]# D[57]# AC25
H_A#27 W2 AB3 ITP_TDO H_D#26 P22 AE21 H_D#58
H_A#28 A[27]# TDO ITP_TMS H_D#27 D[26]# D[58]# H_D#59
W5 AB5 T24 AD21
H_A#29 A[28]# TMS ITP_TRST# H_D#28 D[27]# D[59]# H_D#60
Y4 A[29]# TRST# AB6 R24 D[28]# D[60]# AC22
H_A#30 U2 C20 H_D#29 L25 AD23 H_D#61
A[30]# DBR# SYS_RST# 16 +1.05V D[29]# D[61]#
H_A#31 V4 H_D#30 T25 AF22 H_D#62
C H_A#32 A[31]# R85 *0_4 H_D#31 D[30]# D[62]# H_D#63 C
W3 A[32]# H_PROCHOT# N25 D[31]# D[63]# AC23
H_A#33 AA4 THERMAL 5 H_DSTBN#1 L26 AE25
A[33]# DSTBN[1]# DSTBN[3]# H_DSTBN#3 5
H_A#34 AB2 R84 R272 5 H_DSTBP#1 M26 AF24
A[34]# DSTBP[1]# DSTBP[3]# H_DSTBP#3 5
H_A#35 AA3 D21 H_PROCHOT#_R 68_4 +1.05V 1K/F_4 5 H_DINV#1 N24 AC20
A[35]# PROCHOT# DINV[1]# DINV[3]# H_DINV#3 5
5 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 H_THERMDA 4
B25 H_GTLREF AD26 R26 COMP0 R279 27.4/F_4 COMP0/2 COMP1/3
THERMDC H_THERMDC 4 GTLREF COMP[0]
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