Service Manuals, User Guides, Schematic Diagrams or docs for : HP HP_OmniBook_XE3 7113d_LA-733B
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A B C D E
1 1
2 2
Hurricane 1.6
N32N LA-733 REV. 4A SCHEMATIC DOCUMENT
3
uPGA2 COPPERMINE with Geyserville 3
4 4
Compal Electronics, inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-733
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
B 401138 4C
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Tuesday, August 21, 2001 Sheet 1 of 47
A B C D E
A B C D E
Revision History
Compal confidential
Date:06/28/2000 Rev#: 2.0 description: MP-test for H1.5
Model Name : N32N Date:12/20/2000 Rev#: 3.0 description: C1-test for H1.6
Board Name : LA-733 Date:02/02/2001 Rev#: 4.0 description: C2-test for H1.6
Date:03/05/2001 Rev#: 4A description: C3-test for H1.6
HP Model Name : Hurricane 1.6
1 1
Gerserville Coppermine (uPGA2) CPU
SPR CONN. Tech. page 3,4,5
HCLK_CPU
page 33 page 6
HA#(3..31) HD#(0..63) Y1
14.318MHZ
14M_3V
PCLK_MTXC Clock
14M_5V
440ZXM HCLK_CPU Generator
CRT CONN.
VGA Board 14M_3V
DCLKWR Buffer PCLK_DOCK
2
page 24 CONN. AGP Bus
page 7,8,9
DCLKO page 10 +3V
+3VS
PCLK_PCM
2
page 23
MA(0..13)
MD(0..63)
Dot-Matrix, Button AD(0..31)
Board, FDD, CLK_SDRAM(0..3)
144Pin S.O.Dimm
Touch-PAD Socket PCLK_PIIX4
CONN.page 32 page 11,12 +3V
PCI BUS
Audio CD-DJ
CardBus ESS OZ163 CLK_48MHZ
Mini PCI IDE (HDD/CR-ROM) page 20 PIIX4M
Socket TI1420 Solt1/2 ES1988 page 21,22 page 13,14
14M_3V
3 +3V / +3VS 3
page 15,16 page 17
page 31 USB Port 0 (5VS Tolerant)
and Port 1
page 28
EQ & SA(0..15)
Speaker AMP. SD(0..15)
PCLK_SIO
ISA BUS
page 18,19
14M_5V DC-DC Screw Hole
Super IO KeyBoard Interface & RTC page 39
37N869 RESET CKT
page 32
87570 page 30
page 27 page 25,26
PIO SIO Touch Pad SMBus SUS_ON Power CKT DC/DC MAX1632
page 28 page 28 CONN. page 25
4 page 34 MAX1711 4
FIR FDD KBD page 34,36,37,38
page 28 page 26 page 29
BIOS PS/2 SM Bus Compal Electronics, inc.
page 29 page 29 Battery Charge Title
SCHEMATIC, M/B LA-733
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL page 35 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 4C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401138
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, August 21, 2001 Sheet 2 of 47
A B C D E
TESTLO1
TESTHI TESTLO2
RTTIMPEDP +VCPU_IO
DBSY# 7 R75
1 2 R276
+VCPU_IO DRDY# 7
L7 LQG21N4R7K10 Add 1 2 BSEL0 1 2 RTTIMPEDP
1
C107
CAP. by
1
LO/HI# 10UF_10V_1206 + C552 1.5K 56.2_1%
6 CPU_LO/HI# Charles
EDGCTRLP R250
BSEL1 .01UF at 6/22 1 2 BSEL1
BSEL0
2
2
0 R249
AD19
AD17
AD20
AA12
AB15
AA16
AB19
AA17
1 2 EDGCTRLP
AA3
U21
R21
U19
V20
V18
P21
P20
T21
M2
G4
R2
N5
H4
Y5
T1
L2
HD[0..63] U7A 110_1%
9 HD[0..63]
HREQ#[0..4]
BSEL0
BSEL1
GHI#
PLL1
PLL2
TESTLO1
TESTLO2
TESTP1
TESTP2
TESTP3
TESTP4
DBSY#
DRDY#
DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#
RSVD
EDGECTRLP
TESTHI
RTTIMPEDP
7 HREQ#[0..4]
HA[3..31]
7 HA[3..31]
+VCPU_IO
HA3 L3 Analog Data Phase Signals D10 HD0 R77
HA4 A3# CMOS Test Inputs D0# HD1 TESTHI
K3 A4# D1# D11 1 2
HA5 J2 Geyserville C7 HD2
A5# D2# 1.5K
HA6 L4 C8 HD3
HA7 A6# D3# HD4 R92 TESTLO1
L1 A7# D4# B9 1 2
HA8 K5 A9 HD5 +VCPU_IO
A8# D5# 1K
HA9 K1 C10 HD6
HA10 A9# D6# HD7 R89
J1 A10# D7# B11
HA11 HD8 CPURST# R95 TESTLO2
J3 A11# D8# C12 1 2 1 2
HA12 K4 B13 HD9
A12# D9# 1K
HA13 G1 A14 HD10 56.2_1%
HA14 A13# D10# HD11
H1 A14# D11# B12
HA15 E4 E12 HD12
HA16 A15# D12# HD13
F1 A16# D13# B16
HA17 F4 A13 HD14
HA18 A17# D14# HD15
F2 A18# D15# D13
HA19 E1 D15 HD16
HA20 A19# D16# HD17
C4 A20# D17# D12
HA21 D3 B14 HD18
HA22 A21# D18# HD19
D1 A22# D19# E14
HA23 E2 C13 HD20
HA24 A23# D20# HD21
D5 A24# D21# A19
HA25 Address Lines Data Phase Signals HD22 +3V R248
D4 A25# D22# B17
HA26 C3 A18 HD23 1 2
HA27 A26# D23# HD24
C1 A27# D24# C17
1
HA28 B3 D17 HD25 10K
HA29 A28# D25# HD26 C281
A3 A29# D26# C18
HA30 B2 B19 HD27 .1UF
HA31 A30# D27# HD28
2
C2 A31# D28# D18
HD29 U25
A4 B20
A5
A32#
A33#
Coppermine D29#
D30# A20 HD30 THERMDA 1 NC NC 16
2
B4 B21 HD31 2 15
A34# D31# C279 VCC STBY
C5 D19 HD32 3 14
A35# D32# 2200PF DXP SMBCLK SMC 5,20,25,26,32,33,38
C21 HD33 THERMDC 4 13
HREQ#0 D33# HD34 R256 DXN NC
1
T2 E18 5 12
HREQ#1
HREQ#2
V4
V2
REQ0#
REQ1#
REQ2#
H-PBGA D34#
D35#
D36#
C20
F19
HD35
HD36 +3V 1
1K
2 6
7
NC
ADD1
GND
SMBDATA
ALERT
ADD0
11
10
SMD 5,20,25,26,32,33,38
ATF# 26
HREQ#3 W3 D20 HD37 8 9
HREQ#4 W5
REQ3#
REQ4# 495 Ball D37#
D38# D21 HD38 Change GND NC
1
1
W2 H18 HD39 NE1617DS +VCPU_IO
RP# Request Phase Request D39# HD40
value. by R255 R262 R275
D40# F18
AB2 J18 HD41 Charles at Change 1K 10K 1 2 TDI
7 HADS# ADS# D41#
F21 HD42 6/22
RS#0 D42# value. by @150
U1 E20 HD43
RS#[0..2] RS#1 RS0# D43# HD44 Charles at 1 R80 TDO
2
2
7 RS#[0..2] AA2 RS1# D44# H19 2
RS#2 W1 E21 HD45 6/22
RS2# Response Phase Signals D45# @150
Y1 J20 HD46
HTRDY# RSP# D46# HD47 +3V R277 TCK
7 HTRDY# U2 TRDY# D47# H21 1 2
L18 HD48
D48# @1K
W19 G20 HD49
BPM1# D49# HD50 R82 TMS
W21 BPM0# D50# P18 1 2
Y21 Debug Break Point G21 HD51 +VCPU_IO
BP3# D51# @1K
AA21 K18 HD52
BP2# D52# HD53 R273 TRST#
D53# K21 1 2
HD54 RP25
D54# M18 1K
AB18 L21 HD55 1 8 PREQ#
6 GT_INTR LINT0/INTR D55#
AC19 R19 HD56 2 7 IERR#
6 GT_NMI LINT1/NMI Execution Control Signals Arbitration Phase Signals D56# RP2
K19 HD57 3 6 FLUSH#
D57# HD58 SLP#
6 GT_STPCLK# AC11 STPCLK# D58# T20 4 5 5 4
SLP# AB12 Snoop Phase Signals PC Compatibility Signals J21 HD59 6 3 TCK
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