Service Manuals, User Guides, Schematic Diagrams or docs for : HP HP_OmniBook_XE3 ad144_LA-1011
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A B C D E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BLOCK
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
Model Name :
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
N32N101
PCB No :
DIAGRAM
Mobile Tualatin
LA-1011
4 4
or
Coppermine-T Thermal Sensor CK TITAN CPU VID & All
Date : (uFCBGA/uFCPGA) MAX1617MEE ICS9250-38 reference voltage
2001/09/01 PAGE 4,5 PAGE 5 PAGE 8 PAGE 7
Revision : 1.0
PSB
CRT
Conn. PAGE 16
Almador-M SO-DIMM X2 Docking Connector
LVDS VCH DVOA Bus Interface GMCH-M BANK 0, 1, 2, 3
Conn. PAGE 15 PAGE 15 Memory Bus PAGE 14 LAN
USB X 2
3
625 BGA 3
PARALLEL PORT
TV-Out
TV-Out DVOC Bus Interface SERIAL PORT
Encoder
Conn. PAGE 16 PAGE 9,10,11 DC-IN JACK
PAGE 15
LINE OUT
Kinnereth
Interface
HUB
LAN EXT. MIC IN
82562ET
CRT CONN.
PAGE 25
PS/2 CONN. PAGE 37
HDD Connector ATA 66/100
PAGE 21
IEEE-1394 FAN on controller &
Controller TEMP. sensing circuit
PAGE 22
CD-ROM Connector Audio DJ PAGE 36
OZ163
ICH3-M
PAGE 21
Rev.C
2
PAGE 26 421 BGA Mini PCI 2
PCI BUS DC/DC Interface
USB & BlueTooth USB
Socket
PAGE 17,18 PAGE 38
RTC Battery
PAGE 20
PAGE 39
LPC
CardBus
OZ6933T Slot 0/1
PAGE 24 BATTERY
PAGE 23
Super I/O Embedded Charger
PAGE 42
NS PC87391 Controller
PAGE 32 NS PC87591 Audio
PAGE 30 Controller EQ Circuit
ES1988 POWER
PAGE 27 PAGE 29
Interface
1 PAGE 40,41,42,44 1
ROM Scan KB PS/2 Interface Mic Jack
Parallel FIR FDD BIOS Audio Amplifier
Title
Compal Electronics, inc.
PAGE 33 PAGE 33 PAGE 33 PAGE 31 PAGE 35 PAGE 35 PAGE 28 PAGE 28
SCHEMATIC, M/B LA-1011
Size Document Number Rev
Custom 401174 1A
Date: Friday, September 21, 2001 Sheet 2 of 46
A B C D E
A B C D E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Voltage Rails
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
1 B+ AC or battery power rail for power circuit. N/A N/A N/A 1
+VCC_H_CORE Core voltage for CPU ON OFF OFF
+VTT 1.2V switched power rail for CPU AGTL Bus ON OFF OFF
+1.5V_ALW 1.5V always on power rail ON ON ON*
+1.5V_SW AGP 4X ON OFF OFF
+1.8V_ALW 1.8V always on power rail ON ON ON*
+1.8V_SW 1.8V switched power rail ON OFF OFF
+2.5V 2.5V power rail ON ON OFF
+2-5V_MRIMM 2.5V switched power rail ON OFF OFF
+3V_ALW 3.3V always on power rail ON ON ON*
+3V 3.3V power rail ON ON OFF
+3V_SW 3.3V switched power rail ON OFF OFF
+5V_ALW 5V always on power rail ON ON ON*
+5V 5V power rail ON ON OFF
+5V_SW 5V switched power rail ON OFF OFF
2 2
+12V_ALW 12V always on power rail ON ON ON*
+12V_SW 12V switched power rail ON OFF OFF
RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
LAN (AD24 internal)
CardBus AD20 2 PIRQA/PIRQB
Audio Controller AD19 3 PIRQD
Mini-PCI AD18 1 PIRQC
Mini-PCI(LAN) AD22 4 PIRQD
3
IEEE-1394 Controller AD16 0 PIRQA 3
EC SM Bus1 address EC SM Bus2 address
Device Device
Smart Battery 0001 011X b MAX1617MEE 1001 110X b
EEPROM 1010 000X b OZ163 0011 0100 b
Docking 0011 011X b
DOT Board XXXX XXXXb
ICH3 SM Bus address
Device
SODIMM 1010 000X b
Clock Gen. 1101 001X b
4 4
P.S:Default Resistor & Capacitor's package are 0402. Title
Compal Electronics, inc.
Default 8P4R package is 0402. SCHEMATIC, M/B LA-1011
Size Document Number Rev
Custom 401174 1A
Date: Friday, September 21, 2001 Sheet 3 of 46
A B C D E
A B C D E
+VCC_H_CORE
1 1
AC21
AC19
AC17
AC15
AC13
AC11
AB22
AA21
AB20
AA19
AB18
AA17
AB16
AA15
AB14
AA13
AB12
AA11
AB10
W21
AC9
AC7
M22
AA9
AB8
AA7
G21
D22
H22
N21
R21
U21
D20
D18
D16
D14
D12
D10
E21
K22
P22
V22
Y22
E19
E17
E15
E13
E11
F22
T22
F20
F18
F16
F14
F12
F10
L21
J21
G5
D8
D6
H6
N5
E9
E7
E5
K6
V6
F8
F6
T6
J5
H_A#[3..31] U4A H_D#[0..63]
9 H_A#[3..31] H_D#[0..63] 9
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
H_A#3 K1 A16 H_D#0
H_A#4 A#3 D#0 H_D#1
J1 A#4 D#1 B17
H_A#5 G2 A17 H_D#2
H_A#6 A#5 D#2 H_D#3
K3 A#6 D#3 D23
H_A#7 J2 B19 H_D#4
H_A#8 A#7 D#4 H_D#5
H3 A#8 D#5 C20
H_A#9 G1 VCC C16 H_D#6
H_A#10 A#9 D#6 H_D#7
A3 A#10 D#7 A20
H_A#11 J3 A22 H_D#8
H_A#12 A#11 D#8 H_D#9
H1 A#12 D#9 A19
H_A#13 D3 A23 H_D#10
H_A#14 A#13 D#10 H_D#11
F3 A#14 D#11 A24
H_A#15 G3 C18 H_D#12
H_A#16 A#15 D#12 H_D#13
C2 A#16 D#13 D24
H_A#17 B5 B24 H_D#14
H_A#18 A#17 D#14 H_D#15
B11 A#18 D#15 A18
H_A#19 C6 E23 H_D#16
H_A#20 A#19 D#16 H_D#17
B9 A#20 D#17 B21
H_A#21 B7 B23 H_D#18
H_A#22 A#21 D#18 H_D#19
C8 A#22 D#19 E26
H_A#23 A8 C24 H_D#20
2 H_A#24 A#23 D#20 H_D#21 2
A10 A#24 Address D#21 F24
H_A#25 B3 Lines D25 H_D#22
H_A#26 A#25 D#22 H_D#23
A13 A#26 D#23 E24
H_A#27 A9 B25 H_D#24
H_A#28 A#27 D#24 H_D#25
C3 A#28 D#25 G24
H_A#29 C12 H24 H_D#26
H_A#30 A#29 D#26 H_D#27
C10 A#30 D#27 F26
H_A#31 A6 L24 H_D#28
A#31 D#28 H_D#29
A15 H25
A14
B13
A12
A#32
A#33
A#34
Mobile Data
Signals
D#29
D#30
D#31
C26
K24
G26
H_D#30
H_D#31
H_D#32
9 H_REQ#[0..4]
H_REQ#[0..4]
H_REQ#0 R1
A#35
REQ#0
Tualatin D#32
D#33
D#34
D#35
K25
J24
K26
H_D#33
H_D#34
H_D#35
H_REQ#1 L3 F25 H_D#36
H_REQ#2 REQ#1 D#36 H_D#37
T1 REQ#2 Request D#37 N26
H_REQ#3 U1 Signals J26 H_D#38
H_REQ#4 REQ#3 D#38 H_D#39
L1 REQ#4 D#39 M24
T4 U26 H_D#40
RP# D#40 H_D#41
9 H_ADS# AA3 ADS# D#41 P25
L26 H_D#42
D#42 H_D#43
D#43 R24
W2 R26 H_D#44
AERR# D#44 H_D#45
AB3 AP#0 D#45 M25
P3 Error V25 H_D#46
+1.5V_SW AP#1 D#46 H_D#47
C14 BERR# Interface D#47 T24
R19 1.5K AF23 M26 H_D#48
BINIT# D#48 H_D#49
1 2 AF4 IERR# D#49 P24
3 H_D#50 3
D#50 AA26
R28 10 T26 H_D#51
D#51 H_D#52
1 2 A7 BREQ0# D#52 U24
C4 Arbitration Y25 H_D#53
NC D#53 H_D#54
C22 NC Signals D#54 W26
AD23 V26 H_D#55
NC D#55 H_D#56
9 H_BPRI# R2 BPRI# D#56 AB25
L2 T25 H_D#57
9 H_BNR# BNR# D#57
V3 Snoop VSS VCC Y24 H_D#58
9 H_LOCK# LOCK# D#58
Signals W24 H_D#59
D#59 H_D#60
D#60 Y26
AA2 AB24 H_D#61
9 H_HIT# HIT# D#61
U2 AA24 H_D#62
9 H_HITM# HITM# D#62
T3 V24 H_D#63
9 H_DEFER# DEFER# D#63
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VCC_73
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
AC25
AC22
AC20
AA25
AE26
AB23
AE23
AB21
AA22
AE21
AB19
AA20
AE19
AB17
AF25
W25
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