Service Manuals, User Guides, Schematic Diagrams or docs for : HP hp_g42_g56_g62_compaq_cq56_cq62_quanta_ax2_ax7_rev_1a_sch
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1 2 3 4 5 6 7 8
AX2/7 SYSTEM DIAGRAM 01
DDR3-SODIMM1 DDR3 channel A
AMD Champlain CPU THERMAL
PAGE 6 SENSOR
35mm X 35mm
A A
S1G4 Processor PAGE 5
DDR3-SODIMM2 DDR3 channel B
638P (PGA)35W/25W
PAGE 7 PAGE 3,4,5
HT3
PCI-E
PAGE 25
NORTH BRIDGE
RS880M A12 PAGE 24
RTL8103E
B
(10/100) 23mm X 23mm B
PAGE 23
PAGE 30 PAGE 33 PAGE 17,18,19
PAGE 8,9,10,11 20,21
PAGE 22
ALINK X4 PAGE 8
PAGE 30
SYSTEM CHARGER(ISL6251)
PAGE 40 0,5,8 15 2 3 10
PAGE 29 SOUTH BRIDGE
SYSTEM POWER ISL6237 PAGE 29 PAGE 29 PAGE 23
PAGE 33
PAGE 34 SB820 A12 PAGE 26
DDR II SMDDR_VTERM PAGE 29
1.8V/1.8VSUS(RT8207) 4.5W(Ext)
C PAGE 37 4.3W(Int) C
PAGE 12,13,14,15,16
VCCP +1.1V AND +1.2V(RT8204)
PAGE 35
PAGE 28
VGACORE(1.1V~1.2V)Oz8118 PAGE 27
PAGE 38
CPU CORE ISL6265HRTZ-T
PAGE 36
PAGE 32 PAGE 27 PAGE 28
SMBUS TABLE
Clock gen/Robson/TV tuner
SB--SCL0/SD0 /DDR2/DDR2 thermal/Accelerometer +3V
D
PAGE 31 D
PAGE 31
epress card PAGE 28 PAGE 31
Wlan Card +3VS5
EC --SCL/SD Battery charge/discharge +3VPCU
EC--SCL2/SD2 VGA thermal/system thermal +3V Size Document Number Rev
Custom 1A
Block Diagram
1 2
http://laptop-motherboard-schematic.blogspot.com/
3 4 5 6
Date: Thursday, December 24, 2009
7
Sheet 1
8
of 42
5 4 3 2 1
02
D D
PV,delete all external clock GEN reserve material
C C
B B
A A
Size Document Number Rev
Custom 1A
Clock Generator
5
http://laptop-motherboard-schematic.blogspot.com/
4 3 2
Date: Wednesday, December 23, 2009 Sheet
1
2 of 42
5 4 3 2 1
BLM21PG221SN1D(220,100M,2A)_8 H_THRMDC
03
+CPUVDDA
W/S= 15 mil/20mil H_THRMDA
H_THRMDC 5
+2.5V H_THRMDA 5
VLDT use 1.5A Max current L34 CPU CLK CPU_PWRGD 300_4 R146
+1.1V +1.1V_VLDT C418 LS0805-100M-N C392 C302 C304 CPUCLKP CPU_LDT_RST# 300_4 R148
12 CPUCLKP
4.7U/6.3V_6 4.7U/6.3V_6 0.22U/25V_6 3300P/50V_4 CPUCLKN CPU_LDT_STOP# 300_4 R166
12 CPUCLKN
R164 *0_6/S CPU_LDT_REQ#_CPU *300/F_4 R144 +1.5V
Keep trace from resisor to CPU within 0.6"
+1.1V +1.1V_VLDT_R +CPUVDDA 250mA
keep trace from caps to CPU within 1.2" U21D
R83 *0_6/S U21A W/S= 15 mil/20mil
+CPUVDDA F8 M11
+1.1V_VLDT +1.1V_VLDT_R 10U/6.3V_8 C99 CPUCLKIN R149 169/F_4 CPUCLKIN# +CPUVDDA VDDA1 VSS
D1 VLDT_A0 HT LINK VLDT_B0 AE2 F9 VDDA2 RSVD11 W18
C396 10U/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT_R 0.22U/6.3V_4 C113
D C390 0.22U/6.3V_4 +1.1V_VLDT VLDT_A1 VLDT_B1 +1.1V_VLDT_R 180P/50V_4 C120 CPUCLKP C402 3900P/25V_4 CPUCLKIN CPU_SVC_R D
D3 VLDT_A2 VLDT_B2 AE4 A9 CLKIN_H SVC A6
C389 180P/50V_4 +1.1V_VLDT D4 AE5 +1.1V_VLDT_R 10U/6.3V_8 C594 CPUCLKN C401 3900P/25V_4 CPUCLKIN# A8 A4 CPU_SVD_R
VLDT_A3 VLDT_B3 CLKIN_L SVD
HT_NB_CPU_CAD_H0 E3 AD1 HT_CPU_NB_CAD_H0 CPU_LDT_RST# B7
L0_CADIN_H0 L0_CADOUT_H0 12 CPU_LDT_RST# RESET_L
HT_NB_CPU_CAD_L0 E2 AC1 HT_CPU_NB_CAD_L0 CPU_PWRGD A7
L0_CADIN_L0 L0_CADOUT_L0 12 CPU_PWRGD PWROK
HT_NB_CPU_CAD_H1 E1 AC2 HT_CPU_NB_CAD_H1 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP_L#
L0_CADIN_H1 L0_CADOUT_H1 10,12 CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L
HT_NB_CPU_CAD_L1 F1 AC3 HT_CPU_NB_CAD_L1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_NB_CPU_CAD_H2 L0_CADIN_L1 L0_CADOUT_L1 HT_CPU_NB_CAD_H2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 MEMHOT_L AA8 T15
HT_NB_CPU_CAD_L2 G2 AA1 HT_CPU_NB_CAD_L2 CPU_SIC AF4
L0_CADIN_L2 L0_CADOUT_L2 5 CPU_SIC SIC
HT_NB_CPU_CAD_H3 G1 AA2 HT_CPU_NB_CAD_H3 SideBand Temp sense I2C CPU_SID AF5
HT_NB_CPU_CAD_H[15..0] L0_CADIN_H3 L0_CADOUT_H3 5 CPU_SID SID
HT_NB_CPU_CAD_L3 H1 AA3 HT_CPU_NB_CAD_L3 CPU_ALERT AE6 W7 H_THRMDC
8 HT_NB_CPU_CAD_H[15..0] L0_CADIN_L3 L0_CADOUT_L3 5 CPU_ALERT ALERT_L THERMDC
HT_NB_CPU_CAD_H4 J1 W2 HT_CPU_NB_CAD_H4 W8 H_THRMDA
HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CAD_L4 L0_CADIN_H4 L0_CADOUT_H4 HT_CPU_NB_CAD_L4 R114 44.2/F_4 CPU_HTREF0 THERMDA
8 HT_NB_CPU_CAD_L[15..0] K1 L0_CADIN_L4 L0_CADOUT_L4 W3 R6 HT_REF0
HT_NB_CPU_CAD_H5 L3 V1 HT_CPU_NB_CAD_H5 +1.5VSUS R115 44.2/F_4 CPU_HTREF1 P6
L0_CADIN_H5 L0_CADOUT_H5 +1.1V_VLDT HT_REF1
HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CAD_L5 L2 U1 HT_CPU_NB_CAD_L5 place them to CPU within 1.5"
8 HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CAD_H6 L0_CADIN_L5 L0_CADOUT_L5 HT_CPU_NB_CAD_H6 VDDIO_FB_H
L1 L0_CADIN_H6 L0_CADOUT_H6 U2 36 CPU_VDD0_RUN_FB_H F6 VDD0_FB_H VDDIO_FB_H W9 VDDIO_FB_H 37
HT_NB_CPU_CLK_L[1..0] HT_NB_CPU_CAD_L6 M1 U3 HT_CPU_NB_CAD_L6 E6 Y9 VDDIO_FB_L
8 HT_NB_CPU_CLK_L[1..0] L0_CADIN_L6 L0_CADOUT_L6 36 CPU_VDD0_RUN_FB_L VDD0_FB_L VDDIO_FB_L VDDIO_FB_L 37
HT_NB_CPU_CAD_H7 N3 T1 HT_CPU_NB_CAD_H7 R163
HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CAD_L7 L0_CADIN_H7 L0_CADOUT_H7 HT_CPU_NB_CAD_L7
8 HT_NB_CPU_CTL_H[1..0] N2 L0_CADIN_L7 L0_CADOUT_L7 R1 36 CPU_VDD1_RUN_FB_H Y6 VDD1_FB_H VDDNB_FB_H H6 CPU_VDDNB_RUN_FB_H 36
HT_NB_CPU_CAD_H8 E5 AD4 HT_CPU_NB_CAD_H8 510/F_4 AB6 G6
HT_NB_CPU_CTL_L[1..0] L0_CADIN_H8 L0_CADOUT_H8 36 CPU_VDD1_RUN_FB_L VDD1_FB_L VDDNB_FB_L CPU_VDDNB_RUN_FB_L 36
HT_NB_CPU_CAD_L8 F5 AD3 HT_CPU_NB_CAD_L8
8 HT_NB_CPU_CTL_L[1..0] HT_NB_CPU_CAD_H9 L0_CADIN_L8 L0_CADOUT_L8 HT_CPU_NB_CAD_H9 CPU_DBRDY
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 G10 DBRDY
HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_L9 F4 AC5 HT_CPU_NB_CAD_L9 CPUTEST25H CPU_TMS AA9 E10 CPU_DBREQ#
8 HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_H10 L0_CADIN_L9 L0_CADOUT_L9 HT_CPU_NB_CAD_H10 CPU_TCK TMS DBREQ_L
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 AC9 TCK
HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_L10 H5 AB3 HT_CPU_NB_CAD_L10 CPUTEST25L CPU_TRST# AD9 AE9 CPU_TDO
8 HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_H11 L0_CADIN_L10 L0_CADOUT_L10 HT_CPU_NB_CAD_H11 CPU_TDI TRST_L TDO
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 AF9 TDI
HT_CPU_NB_CLK_H[1..0] HT_NB_CPU_CAD_L11 H4 AA5 HT_CPU_NB_CAD_L11 R162
8 HT_CPU_NB_CLK_H[1..0] HT_NB_CPU_CAD_H12 L0_CADIN_L11 L0_CADOUT_L11 HT_CPU_NB_CAD_H12 CPUTEST23
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5 T7 AD7 TEST23 TEST28_H J7
HT_CPU_NB_CLK_L[1..0] HT_NB_CPU_CAD_L12 K4 W5 HT_CPU_NB_CAD_L12 510/F_4 H8
8 HT_CPU_NB_CLK_L[1..0] HT_NB_CPU_CAD_H13 L0_CADIN_L12 L0_CADOUT_L12 HT_CPU_NB_CAD_H13 CPUTEST18 TEST28_L
L5 L0_CADIN_H13 L0_CADOUT_H13 V4 T26 H10 TEST18
C HT_CPU_NB_CTL_H[1..0] HT_NB_CPU_CAD_L13 M5 V3 HT_CPU_NB_CAD_L13 CPUTEST19 G9 D7 CPUTEST17 C
8 HT_CPU_NB_CTL_H[1..0] L0_CADIN_L13 L0_CADOUT_L13 T30 TEST19 TEST17 T37
HT_NB_CPU_CAD_H14 M3 V5 HT_CPU_NB_CAD_H14 E7 CPUTEST16
HT_CPU_NB_CTL_L[1..0] L0_CADIN_H14 L0_CADOUT_H14 TEST16 T38
HT_NB_CPU_CAD_L14 M4 U5 HT_CPU_NB_CAD_L14 CPUTEST25H E9 F7 CPUTEST15
8 HT_CPU_NB_CTL_L[1..0] L0_CADIN_L14 L0_CADOUT_L14 TEST25_H TEST15 T29
HT_NB_CPU_CAD_H15 N5 T4 HT_CPU_NB_CAD_H15 CPUTEST25L E8 C7 CPUTEST14
L0_CADIN_H15 L0_CADOUT_H15 TEST25_L TEST14 T49
HT_NB_CPU_CAD_L15 P5 T3 HT_CPU_NB_CAD_L15 place them to CPU within 1.5"
L0_CADIN_L15 L0_CADOUT_L15 CPUTEST21 AB8 TEST21 TEST7 C3
HT_NB_CPU_CLK_H0 J3 Y1 HT_CPU_NB_CLK_H0 CPUTEST20 AF7 K8 R156 *300/F_4 +1.1V_VLDT
L0_CLKIN_H0 L0_CLKOUT_H0 T127 TEST20 TEST10
HT_NB_CPU_CLK_L0 J2 W1 HT_CPU_NB_CLK_L0 CPUTEST24 AE7
HT_NB_CPU_CLK_H1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CPU_NB_CLK_H1 CPUTEST22 TEST24
J5 Y4 +1.5VSUS T8 AE8 C4
HT_NB_CPU_CLK_L1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CPU_NB_CLK_L1 R172 300/F_4 CPU_DBREQ# CPUTEST12 TEST22 TEST8 CPUTEST29H
K5 Y3 T6 AC8 T46
L0_CLKIN_L1 L0_CLKOUT_L1 CPUTEST27 TEST12
AF8
HT_NB_CPU_CTL_H0 HT_CPU_NB_CTL_H0 R338 1K/F_4 CPUTEST27 TEST27 R130
N1 R2 C9
HT_NB_CPU_CTL_L0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CPU_NB_CTL_L0 R157 *0_4/S TEST29_H
P1 R3 C2 C8
HT_NB_CPU_CTL_H1 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CPU_NB_CTL_H1 R339 *300/F_4 TEST9 TEST29_L 80.6/F_4
P3 T5 AA6
HT_NB_CPU_CTL_L1 L0_CTLIN_H1 L0_CTLOUT_H1 HT_CPU_NB_CTL_L1 TEST6 CPUTEST29L
P4 R5 T45
L0_CTLIN_L1 L0_CTLOUT_L1
A3 H18
RSVD1 RSVD10
FOX PZ63826-284R-41F A5
RSVD2 RSVD9
H19
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN B3 AA7 Route as 80ohm, diff
RSVD3 RSVD8
MLX 47296-4131 B5 D5
RSVD4 RSVD7
C1 C5
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2) RSVD5 RSVD6
TYC 4-1903401-2
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN
MV can remove reserve for debug Serial VID VFIX MODE VID Override table (VDD)
B +1.5VSUS B
SVC SVD Output Voltage
R207 10K/F_4 CNTR_VREF +3V
+1.5VSUS +1.5V 0 0 1.1V
R186 R189 1K/F_4 +1.5VSUS
0 1 1.0V
2
Q19 R170 R171 R190 1K/F_4
MMBT3904
1K/F_4
*1K/F_4 *1K/F_4
+1.5V 1 0 0.9V
CPU_LDT_RST# CPU_LDT_RST_HTPA#
1 3
CPU_SVC_R R176 0_4 CPU_SVC 1 1 0.8V
CPU_SVC 36
CPU_SVD_R R175 0_4 CPU_SVD
CPU_SVD 36
CPU_PWRGD R177 0_4 CPU_PWRGD_SVID_REG
CPU_PWRGD_SVID_REG 36
CPUTEST20 R340 1K/F_4
CPUTEST21 R81 1K/F_4
R184 *220_4 CPUTEST22 R80 1K/F_4
R183 *220_4 CPUTEST24 R69 1K/F_4
R185 *220_4
+1.5VSUS R224 10K/F_4
+1.5VSUS R181 10K/F_4 HDT Connector
R225 300_4 +1.5VSUS
+1.5VSUS
+1.5VSUS R180 1K/F_4 CPUTEST12 R70 1K/F_4
2
Q18 1 2 CPUTEST19 R124 1K/F_4
MMBT3904 3 4 CPUTEST18 R125 1K/F_4
A CPU_THERMTRIP_L# 1 3 5 6 A
5 CPU_THERMTRIP_L# CPU_THERMTRIP# 13
CPU_PROCHOT_L# R205 0_4 CPU_DBREQ# 7 8
2
Q22 CPU_DBRDY 9 10
CPU_TCK 11 12
R219 0_4 1 3 CPU_PROCHOT_R# CPU_TMS 13 14
32 CPU_PROCHOT# CPU_PROCHOT_R# 12
MMBT3904 CPU_TDI 15 16
CPU_TRST# 17 18
CPU_TDO 19 20
EC new option SI , add R205 for P-state implement 21 22
C74 *0.1U/10V_4 23 24 CPU_LDT_RST_HTPA#
KEY 25
Size Document Number Rev
Custom 1A
S1G4 HT,CTL I/F 1/3
5
http://laptop-motherboard-schematic.blogspot.com/
4 3
CN6 *HDT CONN
2
Date: Thursday, December 24, 2009
1
Sheet 3 of 42
A B C D E
+1.5VSUS
R337
*0_4/S
PLACE THEM CLOSE TO
CPU WITHIN 1"
+0.9V
D10
C10
B10
AD10
U21B
VDDR2
VDDR3
VDDR5
VDDR1 MEM:CMD/CTRL/CLK
VDDR6
VDDR7
W 10
AC10
AB10
AA10
+0.9V
VDDR = 0.9V for 25W & 35W CPU
VDDR = 1.05V for 35V & 45W CPU
7 MEM_MB_DATA[0..63]
DDR_VTTREF 6,7,37
Processor Memory Interface
MEM_MB_DATA0 C11
U21C
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