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HElJLErI PACKARD SUPIPIary of significant chanies between version 3 and version 5
COMPUTER SYSTEMS - 19447 Pruneridge Ave. CUpertino CA 95014 1. Virtual address space has been cut back frOR 74 to 64 bits.
2. The I'llJIber of privileee levels has been reduced froa 8 to 4.
3. Object Descriptors have been streulined to a 4-word foraat.
FrOR: Alan Hewer Date: August 19, 1982
JiPl Miller 4. Procedure linkage has been smplified: the STr-JlechaniSll is no
Dave SalOPlaki longer required in Vision Rode.
Bert Speelpenning Procedure stack Jlarkers have been reduced to three words instead
of four; EXIT can distinguish between Jlarkers laid down by CALL
To: ACD Distribution SUbject: VISION Architecture and CALLX, this aignificantly streaJllines exit frca CALL.
Control DocUPIent,
Version 5 5. SOlIle STATUS bits and other Jlachine state (such as the TCB) have
been rearranQ8d to allow faster updates to the addressing
enviroraent, such as EXIT or IEXIT.
We are proud to announce the release of Version 5 of the VISION ACD. 6. Synchronization of caches and TLBs when Rakilli charlies to the
Version 5 incorporates all changes and clarifications that have addressing tables has been .ade the explicit responsibility of
previously been transmitted only through PlePlos. This single docUPIent operatini systeR software.
provides a stable, self-consistent and cOPlplete description of the
VISION processor architecture including I/O instructions. A version 7. The encoding of instructions has changed. Instructions or pairs
of the cOlllpanion docuPlent "HP/3000 COlllpatibility Mode" incorporating of instructions now occupy a word or a Jlultiple of words.
the eKtended CST structure will be available in October. OrthoQonality of opcodes and operands has been retained.
Version 5 of the ACD replaces version 3, and the copy of version 3 in 8. 8 General reQisters have been added.
your possession Plust be shredded or returned to Bert Speelpenning at
CSY. If you wonder what happened to version 4: there is no version 4 9. Instructions dealing with base reQisters have been separated out.
nor will there be. The designation "version 5" for the neKt Plajor Base reQisters are no longer treated as Qeneral operands.
release of the ACD sOPlehow gained currency within CSY, and it didn't
seeR particularly fruitful to buck that trend. 10. Several instructions that were Jlarginal in terRS of speed-up over
their software equivalents were deleted.
The organization of the architecture description has been thoroughly All 16-bit arithJletic and all 12-byte packed deciJlal arithPletic
overhauled in order to iJllprove clarity of exposition. These changes has been deleted frOR the architecture.
were sufficiently extensive that it was decided not to retain page or
section nuJIIbers frOR version 3; change bars were also abandoned. 11. Opcode assigMents have been updated.
Rather, version 5 is a stand-alone description of the architecture that
should be read in full by iRpleaentors of VISION-specific products. 12. Several definitions of individual instructions have been streaJIlined.
Turning to content, the arChitecture described in version 5 differs frOR 13. Arguaents for trap handlers are pushed in the reverse order. The
that of version 3 in ways described in earlier PlePlOS published by us, trap identification nuJlber is now always on top of the stack.
as well as in other JIIinor ways. These changes are ~arized below.
Their net effect is to Plake the VISION architecture 1II0re streaPIlined 14. The interrupt structure for I/O and inter-processor cOJlAunication
and easier to iPlplePlent coSt-effectively in hardware while JliniPIizing has been defined and included.
the iRpact on software. I/O instructions for PICMB-based systeJIS and for MfB-based syst~s
have been defined and included.
It is a pleasure to acknowledge the help and cooperation we have received The interface to the Control and Support Processor (CSP) has been
in getting the architecture and its description to its current statej the defined and included.
iJlplePIentation teaPIs have been reJlarkably patient in helping us evaluate
the effect of proposed chanies as well as in accOJlodating those changes
we decided to adopt. Not yet included in the Architecture Control DocUJlent are:
Our Plain efforts will becOJle focussed on Ronitoring the progress of
VISION illlpleRentationsj we r~ain cORJIIitted to resolve probleRs in the
present definition of the VISION architecture that these iRpleJIentations 1. Instructions to support diaanostic capabilities.
Ray uncover.
2. Description of the data structures to support I/O.
VISION ARCHITECTURE CONTROL DOCUMENT 07/31
DO NOT COpy -- HP PRIVATE INFORMATION
1 INTRODUCTION
1.1 VISION Architecture Control Document
1.2 Architecture OVerview
1.3 Architecture Control
1.4 Intended Audience
1.5 Related Documents
1.6 Notations and Conventions
VISION 1.7 Implementation Guidelines
2 ADDRESS SPACES
ARCHITECTURE CONTROL DOCUMENT 2.1 Physical Address Space
2.1.1 Pages
2.2 Virtual Address Space
2.2.1 Virtual Address Space: virtual objects
VERSION 5 2.2.2 Virtual Address Space: Paging
2.2.3 The Physical Page Directory (PDIR)
2.3 Logical Address Space
2.3.1 Logical Objects
2.3.2 Object Descriptor Format
July 31, 1982 2.3.2.1 Object Types
2.3.2.2 Access Rights
2.3.2.3 Lower and Upper Bounds
2.3.3 Object Groups
2.3.4 Object Descriptor Table
2.3.5 Current Code Object
COPYRIGHT (C) 1982 HEYLEIT-PACKARD COMPANY 2.3.6 Current Stack Object
2.3.7 Nil Object
2.3.8 Group Descriptors
2.3.9 Task Control Block
3 ADDRESS TRANSLATION
3.1 An access -- its characteristics
3.2 Access Algorithm
+------------------------------------------+
Your copy of this document is registered
3.2.1 Schematic OVerview
Hardware Shortcuts in Address Translation
3.2.2
3.3 Logical to Virtual Address Translation
COPY 3.3.1 Locating the bDT in Virtual Space
NUMBER 3.3.1.1 Locating the DDT for Group Zero
3.3.1.2 Locating the DDT for a Group Other than Zero
+------------------------------------------+ 3.3.2 L9cpting the 00 for the Logical Object
3.3.3 Computing the Virtual Offset
-3.4 Virtual to Physical Address Translation
3.4.1 Physical Page Directory Search '
3.4.2 OVerview of Hash Table and Hash Chain
3.4.3 The Hash Table
3.4.4 PPD Format to Support Hashing and Related Functions
3.4.5 The Hash Algorithm
3.4.6 Page Faults
i
VISION ARCHITECTURE CONTROL DOCUMENT 07/31 VISION ARCHITECTURE CONTROL DOCUMENT 07/31
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4 PROCESSOR REGISTERS AND MACHINE STATE 5 MACHINE MODEL
4.1 General/Index Registers 5.1 The Vision Stack
4.2 Base Registers 5.1.1 Procedure Stack Marker
4.3 PrograIll Counter 5.1.1.1 External Procedure Stack Marker
4.4 Status Registers 5.1.1.2 Local Procedure Marker
4.4.1 STATUSA Register 5.1.2 Interrupt Marker
4.4.1.1 FOrI1lat 5.1.3 Dispatcher Marker
4.4.1.2 S\lrIu1lary 5.2 Procedure Linkage
4.4.1.3 XL - Execution Privilege Level 5.2.1 Entry Point Evaluation
4.4.1.4 SIT -- Single Instruction Trace 5.2.2 Multiple Entry Points in a Code Object
4.4.1. 5 lIP -- Instruction In Progress 5.3 Debug Support
4.4.1. 6 DBP -- Debug Breakpoint Pending 5.3.1 Code Breakpoints
4.4.2 STATUSB -- Task/Interrupt Status 5.3.2 Breakranges
4.4.2.1 Forlllat 5.3.3 Single Instruction Trace
4.4.2.2 Sullllllary 5.3.4 Procedure Trace
4.4.2.3 PTE -- Procedure Trace Enable 5.3.5 Object Trace
4.4.2.4 DISP -- Dispatcher Running Flag 5.3.6 Ring Crossing Trap
4.4.2.5 vector -- vector register status 5.4 List of Supported Data Types
4.4.2.6 TCE -- Task Clock Enable 5.4.1 Integers
4.4.2.7 &IL -- EXIT Threshold Level 5.4.2 Floa ting Point
4.4.2.8 FPC -- IEEE Floating Point Control 5.4.3 Decilllal
4.4.2.9 TE & EF -- Trap & Exception Flags 5.4.4 Logical
4.4.2.10 CBA & CBB -- Condition Break Enable Flags 5.4.5 Bit
4.4.2.11 CC -- Condition Code 5.4.6 Fields
4.4.3 STATUSC -- CPU Status 5.4.7 Byte strings
4.4.3.1 Forlllat
4.4.3.2 Su!Il!Ilary 6 VISION INSTRUCTION SET
4.4.3.3 DDC -- Dispatcher Disable Count 6.1 Prelilllinaries
4.4.3.4 XM -- Excecution Mode 6.1.1 Operands
4.4.3.5 ICS -- On the Interrupt Control Stack 6.1.1.1 Register Operands
4.4.3.6 DRF -- Dispatcher Request Flag 6.1.1.2 Literal Operands
4.4.3.7 IE & 1MB -- Interrupt Enable & Mask Register 6.1.1.3 Melllory Operands
4.4.4 STATUSD -- COlllputer Status 6.1.1.3.1 COlllputing the effective logical address
4.4.4.1 Forlllat 6.1.1.3.2 Base register operands
4.4.4.2 Su!Il!Ilary 6.1.2 Instruction Encoding
4.4.4.3 DRL -- Debug Ring Level 6.1.2.1 Basic instruction encoding sche!lle
4.4.4.4 REVCODE -- SPU Revision Code 6.1.2.2 Dense Instruction Encoding Sche!lle
4.5 Group Descriptors 6.1.2.3 Secondary Instruction Set Encoding
4.6 Virtual Address Translation Registers 6.1.2.4 Code bounds violations
4.7 Task Control Block 6.1.3 Operand descriptors
4.8 Breakranges (Systelll and Task) 6.1.3.1 Short literal
4.9 Interrupt Control Stack location 6.1.3.2 Long li teral
4.10 CST and DST descriptors 6.1.3.3 Register operand
4.11 Vector Processing 6.1.3.4 Melllory operand (base+short word displace!llent)
4.11.1 Vector Registers 6.1.3.5 Melllory operand (base-short word displace!llent)
4.11.2 Vector Mask Registers 6.1.3.6 Me!Ilory operand (base+ long displace!llent)
4.11.3 Vector Length Register 6.1.3.7 Melllory operand (base+index)
4.11.4 Vector Context Save Area 6.1.3.8 Melllory operand (base+index+displace!llent)
4.11.5 Vector Processing: Operation 6.1.4 Opcode Assignments
4.11.6 VP Manage!llent - Vector Context Save Area 6.1.5 Attributes
6.1.5.1 Operand Attributes
6.1. 5.2 Instruction Attributes
ii iii
VISION ARCHITECTURE CONTROL DOCUMENT 07/31 VISION ARCHITECTURE CONTROL DOCUMENT 07/31
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6.1.6 Sources 6.2.5 Base Register Instructions
6.1.7 Destinations 6.2.5.1 BGET8 source.b, destination.wB
6.1.B Traps 6.2.5.2 BSET8 source.rB, dest.b
6.2 Base Instruction Set 6.2.5.3 BMOVEADR source. rn , dest.b
6.2.1 Data Move~ent Instructions 6.2.5.4 BMOVE8 source.b, dest.b
6.2.1.1 MOVEt source.r, destination.w 6.2.5.5 BGET4 source.b, dest.w4
6.2.1.2 MOVEADR operand.~, destination.wB 6.2.5.6 BSET4 source.r4, dest.b
6.2.1.3 PUSHt source. r 6.2.5.7 BPUSHB source.b
6.2.1.4 PUSHADR operand.~ 6.2.5.B BPOP8 dest.b
6.2.1.5 POPt destination.w 6.2.5.9 BADD4 te~.r4, dest.b
6.2.1. 6 DPF value.r4, shiftcount.r1, ~ask.r4, target.rw4 6.2.5.10 BSUB4 te~.r4, dest.b
6.2.1.7 MOVEC length.r4, source.~r, destination.~w 6.2.5.11 BCMP4 sourcea.b, sourceb.r4
6.2.1.B MOVEBIT bitindex.r4, source.r1, bitarray.~rw 6.2.5.12 BCMP8 sourcea.b, sourceb.r8
6.2.1.9 MOVEBLR fillchar, srcl, src, destl, dest 6.2.5.13 BTEST8 source.b
6.2.1.10 MOVEBRL fillchar, srel, src, destl, dest 6.2.6 Transfer of Control
6.2.1.11 TRANSL table.~r, length.r4, source.~r, dest.~w 6.2.6.1 BR{GLEU} target.r4
6.2.1.12 DUP roordcount.r4, value.r4 6.2.6.2 CALL target.r4
6.2.1.13 REP roordeount.r4, value.r4, operand.~w 6.2.6.3 CALLX loi.r4
6.2.1.14 EXTEND wordcount.r4 6.2.6.4 BRX loi.r4
6.2.1.15 DELETE wordcount.r4 6.2.6.5 EXIT
6.2.2 AriUJIIletic Instructions 6.2.6.6 SEXIT
6.2.2.1 ADDt ter~.r, su~.rw 6.2.6.1 BREAK pararneter.r4
6.2.2.2 SUBt te~.r, difference.rro 6.2.6.8 ERROR
6.2.2.3 MPYt factor.r, product.rro 6.2.6.9 NOP
6.2.2.4 DIVt divisor.r, dividend.rro 6.2.6.10 CHECKA pararneter.r4
6.2.2.5 NEGt source.r, destination.w 6.2.6.11 CHECKB pararneter.r4
6.2.2.6 ABSt source.r, destination.w 6.2.6.12 CHECKLO source.r4, lobound.r4
6.2.2.7 REMt divisor.r, dividend.rro 6.2.6.13 CHECKHI source.r4, hibound.r4
6.2.2.8 MODt divisor.r, dividend.rro 6.2.7 Interaction roith Machine State
6.2.2.9 POLYt degree.r1, polyn.~r, operand.rw 6.2.7.1 MOVEfSP4 selector.r1, destination.w4
6.2.3 Logical Operations and Shifts 6.2.7.2 MOVEtSP4 selector.r1, source.r4
6.2.3.1 AND4 ~ask.r4, operand.rro4 6.2.7.3 MOVEfSP8 selector.r1, destination.wB
6.2.3.2 NOT4 source.r4, destination.w4 6.2.7.4 MOVEtSP8 selector.r1, source.r8
6.2.3.3 OR4 ~ask.r4, operand.rro4 6.2.7.5 TRY
6.2.3.4 XOR4 ~ask.r4, operand.rro4 6.2.7.6 UNTRY destination.ro4
6.2.3.5 LSLt shiftcount.r1, bitfield.rro 6.2.8 Instructions that Interact roith the Address Space
6.2.3.6 LSRt shiftcount.r1, bitfield.rw 6.2.B.1 PROBE ring.r1, access.r1, address.r8, length.r4
6.2.3.7 ASLt shifteount.r1, operand.rw 6.2.8.2 TESTREF va.r8
6.2.3.B QUAD4 source.r4, destination.w4 6.2.B.3 PDINS. ppn.r4
6.2.3.9 ASRt shifteount.r1, operand.r~ 6.2.8.4 PDDEL ppn.r4
6.2.4 Co~pares and Tests 6.2.B.5 CVLAtVA operand.~l, virtaddr.w8
6.2.4.1 CMPt source1.r, source2.r 6.2.8.6 HASH virtaddr.r8, hashindex.w4
6.2.4.2 TESTt source.r 6.2.B.7 CVVAtPP virtaddr.r8, ppn.ro4
6.2.4.3 CMPC length.r4, stringa.~, stringb.rn, index.w4 6.2.8.8 GrowGDO newlength.r4
6.2.4.4 TESTLSB source.r1
6.2.4.5 TESTOV
6.2.4.6 TESTA
6.2.4.7 TESTB
6.2.4.8 TESTBIT bitindex.r4, bi tarray. rnr
6.2.4.9 SCANUNTIL eharset.~r, string.~r, index.rw4
6.2.4.10 CMPB fillehar, Igtha, srea, 19thb, sreb, index
6.2.4.11 CMPT table, fillchar, 19tha, srca, 19thb, srcb, inK
iv v
VISION ARCHITECTURE CONTROL DOCUMENT VISION ARCHITECTURE CONTROL DOCUMENT
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6.2.9 Instructions for Tasking and Synchronization 6.4 Vector Instruction Set
6.2.9.1 DISABLE oldi.wl 6.4.1 Boundary conditions
6.2.9.2 ENABLE oldi.rl 6.4.2 Vector Arithmetic Operations
6.2.9.3 INTERRUPT pr.r4 6.4.2.1 VMOVEt vqual.r1, source.vr, dest.vw
6.2.9.4 PSDB 6.4.2.2 VADDt vqual.rl, ter~a.vr, te~b.vr, ~.vw
6.2.9.5 PSEB 6.4.2.3 VSUBt vqual.rl, ter~a.vr, ter~b.vr, diff.vw
6.2.9.6 DISP 6.4.2.4 VMPYt vqual.r1, facta.vr, factb.vr, prod.vw
6.2.9.7 LAUNCH tcbla.r8, tcbva.r8 6.4.2.5 VDIVt vqual.r1, divd.vr, divsr.vr, quot.vw
6.2.9.8 IEXIT 6.4.2.6 VNEGt vqual.rl, source.vr, neg.vw
6.2.9.9 SlJITCH 6.4.2.7 VABSt vqual.rl, source.vr, abs.vw
6.2.9.10 RSlJITCH 6.4.2.8 VREMt vqual.r1, divd.vr, divsr.vr, re~.vw
6.2.9.11 IDLE 6.4.2.9 VMODt vqual.rl, divd.vr, divsr.vr, ~od.vw
6.2.9.12 STOP 6.4.2.10 VLSLt vqual.rl, shiftcount.vr, target.vrw
6.2.9.13 SYNCOD loi. r4 6.4.2.11 VLSRt vqual.r1, shiftcount.vr, target.vrw
6.2.9.14 SYNCTCB tcb. r8 6.4.2.12 VASLt vqual.r1, shiftcount.vr, target.vw
6.2.9.15 SYNCrB operand.~c, length.r4 6.4.2.13 VASRt vqual.r1, shiftcount.vr, target.vw
6.2.9.16 TESTSEMA sel1la.~rw4, result.w4 6.4.3 Vector Logical Operations
6.2.9.17 MOVESEMA source.r4, se~a.~w4 6.4.3.1 VAND4 vqual.rl, facta.vr, factb.vr, and.vw
6.2.9.18 DOlJN se~a.~rw4 6.4.3.2 VOR4 vqual.r1, ter~a.vr, te~b.vr, or.vw
6.2.9.19 TESTDOlJN sel1la.l1lrw4 6.4.3.3 VKOR4 vqual.rl, ter~a.vr, te~b.vr, xor.vw
6.2.9.20 UP se~a.~rw4 6.4.4 Vector Co~pare and Vector/Scalar Hybrids
6.2.10 Arithmetic Conversion 6.4.4.1 VCMPt vqual.r1, field.r1, srca.vr, srcb.vr, mrsel.r1
6.2.10.1 ISC42 source.r4, destination.w2 6.4.4.2 VACCt vqual.rl, te~s.vr, sum.rw
6.2.10.2 CONVERT subopcode.r1, source.r, destination.w 6.4.4.3 VACCDt vqual.rl, ter~s.vr, ~rw
6.3 Decimal Instructions 6.4.4.4 VMAKELt vqual.r1, ter~s.vr, ~aKind.w4
6.3.1 Packed Decimal Numbers 6.4.4.5 VMINELt vqual.r1, ter~s.vr, ~inind.w4
6.3.2 External Decimal Numbers 6.4.4.6 VEKTt vqual.rl, terms.vr, index.r, value.w
6.3.3 Deci~al Instruction Set 6.4.4.7 VINSt vqual.r1, te~s.vw, index.r, newval.r
6.3.3.1 ADDtD term.r, ~.rw 6.4.4.8 VCOMPRSt vqual.rl, terms.vr, compressed.vw
6.3.3.2 SUBtD ter~.r, difference.rw 6.4.4.9 VEKPNDt vqual.rl, ter~s.vr, expanded.vw
6.3.3.3 MPYtD factor.r, product.rw 6.4.4.10 VGATHt vqual.rl, source.vr, index.vr, destination.vw
6.3.3.4 DIVtD divisor.r, quotient.rw 6.4.4.11 VSCATt vqual.r1, source.vr, index.vr, destination.vw
6.3.3.5 CMPtD sourcea.r, sourceb.r 6.4.5 Vector Housekeeping
6.3.3.6 TESTtD source.r 6.4.5.1 RVLR
6.3.3.7 SLD count.r1, length.r1, source.r, dest.m 6.4.5.2 LDVLR source.r4
6.3.3.8 SRD count.r1, lenght.rl, source.r, dest.w 6.4.5.3 STVLR dest.w4
6.3.3.9 MOVED length.r1, source.r, dest.w 6.4.5.4 VINVAL vr~ask.rl
6.3.3.10 VALD length.r1, operand.rw 6.4.5.5 UVCSA
6.3.3.11 CVDI length.r1, source.r, dest.w8 6.4.5.6 PUVCSA tcb.l1lr
6.3.3.12 CVID length.r1, source.r8, dest.w 6.4.5.7 IVB tcb.l1lr
6.3.3.13 TESTSTRIP operand.rw1 6.4.5.8 LVB tcb.~r
6.3.3.14 GETSIGN operand.r1, sign.w1 6.4.6 Operations on Mask Registers
6.3.3.15 OVPUNCH sign.rl, operand.rw1 6.4.6.1 CLRMR ~rselect.rl
6.3.3.16 VALN length.r1, operand.rw 6.4.6.2 STMR l1lrselect.r1, destination.w16
6.3.3.17 CVAD length.rl, source.r, dest.w 6.4.6.3 LDMB ~rselect.r1, source.r16
6.3.3.18 CVDA length.rl, source.r, dest.w 6.4.6.4 MRNOT l1lrselect.rl
6.4.6.5 MRAND ~rasleect.r1, l1lrbselect.rl
6.4.6.6 MBOR l1lraselect.r1, mrbselect.r1
6.4.6.7 MRKOR l1lraselect.rl, mrbselect.rl
6.4.7 Vector Conversion
6.4.7.1 VCONVERT vqual.r1, typer.r1, source.vr, dest.vw
vi vii
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6.5 I/O Instructions 7.5 Detail Description of Internal Interrupts
6.5.1 PICMB-based VISION systems 7.5.1 Architectural Interface
6.5.1.1 PICMB Primitives 7.5.2 EKecution Environment
6.5.1.1.1 !FC 7.5.3 Sequence of Events
6.5.1.1.2 WCMD command.r1 7.5.4 Multiple Internal Interrupts
6.5.1.1.3 WBYIE data.r1, end.r1 7.5.5 Internal Interrupts Descriptions
6.5.1.1.4 RBYTE data.w1 7.5.5.1 Memory Parity Error
6.5.1.2 Functional PICMB Instructions 7.4.5.2 Power Fail
6.5.1.2.1 CHNOP 7.5.5.3 Power Recovery
6.5.1.2.2 RCL response.w1 7.5.5.4 CPU Machine Check
6.5.1.2.3 PRD response. wi 7.5.5.5 CSP Reply is Complete
6.5.1.2.4 PDA response.wl 7.6 Detail Description of Traps
6.5.1.2.5 PAR response.w1 7.6.1 Architectural Interface
6.5.1.2.6 RDP channel.rl, dest,w16, length. TIll 7.6.2 EKecution Environment
6.5.1.2.7 WDP channel.rl, data.r16, length.rw1 7.6.3 Common Covent ions for Traps
6.5.1.2.8 RIS channel.r1, status.wl 7.6.3.1 ParaAeter Passing to Trap Handlers
6.5.1.2.9 CIS channel.r1, status.rl 7.6.3.2 Determining Privilege of the Handler
6.5.1.2.10 SIS channel.r1, status.r1 7.6.3.3 Determining the address of a Trap Handler
6.5.2 MPB-based systems 7.6.4 Sequence of Events
6.5.2.1 MPB-based Instructions 7.6.4.1 A Non-Recoverable Trap on the CUrrent Stack
6.5.2.1.1 lOW channel.r4, control.r4, data.r4 7.6.4.2 A Non-Recoverable Trap on the ICS
6.5.2.1.2 lOR channel.r4, control.r4, data.w4 7.6.4.3 One Restartable Trap on the CUrrent Stack
6.5.2.1.3 IOC channel.r4, control.r4 7.6.4.4 One restartable trap on the ICS
6.5.2.2 Interpretation of the control word on the lOP 7.6.4.5 Top-of-Stack Page Fault and Stack OVerflow
6.5.2.3 lOP Opcodes 7.6.4.6 Multiple Restartable Traps
6.5.2.3.1 Read commands 7.6.4.7 Continuable Traps
6.5.2.3.2 Write Commands 7.6.5 System Error
6.5.2.3.3 Control Commands 7.6.6 Enabling/Disabling Traps
6.5.2.3.4 lOP Command EKecution 7.6.7 Transfer of Control Traps
6.6 Diagnostic Interface 7.6.7.1 Code Object Bounds Violation
6.6.1 MOVEtCSP 7.6.7.2 Code ODT Length Violation
7.6.7.3 Code Object Type Violation
7 INTERRUPTS AND TRAPS 7.6.7.4 Code Privilege Level Violation
7.1 Introduction 7.6.8 Instruction Traps
7.1.1 EKternal Interrupts OvervieTll 7.6.8.1 Privileged Instruction Violation
7.1.2 Internal Interrupts Overview 7.6.8.2 Error Instruction
7.1.3 Traps OVerview 7.6.8.3 CHECKLO Violation
7.1.3.1 Special PrograAming Notes 7.6.8.4 CHECKHI Violation
7.2 Detail Description of EKternal Interrupts 7.6.8.5 Undefined Instruction
7.2.1 Processor Context for Interrupts 7.6.8.6 Exit Threshold Trap
7.2.2 General Operation 7.6.8.7 Misaligned PrograA Counter
7.2.3 Channel Interrupts 7.6.8.8 Probe Violation
7.2.4 Processor-caused Interrupts 7.6.8.9 Operand Specifier Violation
7.2.5 When is the Processor Interrupted? 7.6.8.10 Move Special Violation
7.2.6 Acknowledging Processor Interrupts 7.6.8.11 STiJitch ViOlation
7.2.7 Shared-Memory Multiprocessor Considerations 7.6.8.12 VP Permission Control
7.3 Clocks 7.6.8.13 Vector Operation on the ICS
7.3.1 Time of Day Clock
7.3.2 Task Clock
7.3.3 Interval Clock
7.4 Summary of Traps and Internal Interrupts
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7.6.9 Stack Traps 9 SYSTEM INITIALIZATION
7.6.9.1 Stack Consistency Violation 9.1 Virtual Object Initialization
7.6.9.2 Stack OVerflollJ 9.2 The System COJllJlluniation Area
7.6.9.3 Stack UnderflollJ 9.2.1 The Environment Section
7.6.9.4 Delete/Extend Negative hlordcount 9.2.2 The Identification Section
7.6.10 Data Object Traps 9.2.3 The HardllJare-Reserved Section
7.6.10.1 Data Object Bounds Violation 9.2.4 The Diagnostics Section
7.6.10.2 Data ODT Length Violation 9.2.5 The Load Section
7.6.10.3 Data Object Type Violation 9.2.6 The DUlIlp Section
7.6.10.4 Data Access Rights Violation 9.3 The Hash Table and Physical Page Directory
7.6.11 Floating Point Traps 9.4 The Pr ilIlary Macro Env ironment Buffer
7.6.11.1 Floating Point Invalid Operation 9.4.1 Loading the Primary Macro Environment Buffer
7.6.11.2 Floating Point Divide By Zero 9.5 The Macro Code Launch
7.6.11.3 Floating Point OVerflollJ 9.6 Initial State SUlIlJIlary
7.6.11.4 Floating Point UnderflollJ
7.6.11.5 Floating Point Inexact Result 10 HP/3000 MODE
7.6.12 Integer Traps 10.1 Introduction
7.6.12.1 Fixed Point Divide by Zero 10.2 Environmental OVerviellJ
7.6.12.2 Fixed Point OVerflollJ 10.3 System Control Structures
7.6.13 Dec ilIlal Traps 10.3.1 CST - Code Segment Table
7.6.13.1 Decilllal Divide By Zero 10.3.2 DST - Data Segment Table
7.6.13.2 Decilllal OVerflollJ 10.3.3 ABS - Absolute Memory Object
7.6.13.3 Decilllal Invalid Length 10.4 Task Control Structures
7.6.13.4 Invalid Decilllal Digit 10.4.1 CSTX - Code Segment Table Extension
7.6.14 Debug Trap Conditions 10.4.2 Interrupt Stack Marker
7.6.14.1 Break Instruction 10.4.3 TCB Contents KnollJn to HardllJare
7.6.14.2 Procedure Trace Trap 10.5 Mode SlIJitching
7.6.14.3 CHECKA Instruction 10.5.1 Compatibility Mode Instructions
7.6.14.4 CHECKB Instruction 10.5.1.1 DISP
7.6.14.5 Single Instruction Trace 10.5.1.2 SlIT
7.6.15 Semaphore Traps 10.5.1.3 RSlIT
7.6.15.1 Semaphore OVerflollJ 10.5.2 Native Mode Instructions
7.6.15.2 DOllJn Semaphore 10.5.2.1 DISP
7.6.15.3 Up Semaphore 10.5.2.2 IEXIT
7.6.16 Vision Mode SlIJitch 10.5.2.3 SlJITCH
7.6.17 TRY/UNTRY Traps 10.5.2.4 RShlITCH
7.6.17.1 Try or UNTRY Violation 10.6 Protection
7.6.18 Virtual Addressing Traps 10.7 Implementation Notes
7.6.18.1 PDINS Inconsistent Page Number
7.6.19 Page Absent Traps App SORTED LIST OF INSTRUCTIONS
7.6.19.1 Page Absent
7.6.19.2 Top of Stack Page Absent
7.7 Top of Stack Page Faults
7.8 I CS MechaniSJll
8 INPUT/OUTPUT DATA STRUCTURES
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+---------------------------------------------+----------------+ 1.3 Architecture Control
INTRODUCTION CHAPTER 1
The tern "architecture" as used in this document refers to the
+---------------------------------------------+----------------+ characteristics of the software/hardware interface of compatible
VISION machines. "Hardware" refers to any combination of
electronics, electro-mechanics and microcode.
1.1 VISION Architecture Control Document
The notion of Architecture Control has been created at HP to aid
in the preservation of the investments it and its customers make
in hardware and software with VISION based products. This
This document provides, for reference purposes, the detailed and architectural control document attempts to completely and
rigorous definition of the machine functions perfor~ed by VISION unambiguously describe the features of any model claiming VISION
compatible computer syste~s. VISION provides the basis for a compa tibili ty.
~ultitude of fully co~patible syste~s over time which cover a
broad spectrum of price and perfor~ance, benefiting fro~ the To be successful, the following attributes of the arChitectural
exploitation of new or evolving technologies and ~achine control process are stipulated:
organizations.
1. This document is the only authoritative specification of the
This is the only authoritative specification of the VISION VISION architecture.
arChitecture. It provides machine designers and programmers a 2. All models will be monitored for compliance with the
complete description of the machine model which will transcend architure specification.
all implementations. 3. Deviations from the architecture will be corrected. In the
rare case when the cost to change the design or to retrofit
installed machines is excessive in relation to the practical
value of compliance on that model, deviations are permitted
1.2 Architecture Overview when approval is obtained from all affected group managers,
and appropriate provision is made for the exception in the
Architectural Control Document.
The VISION architecture is a product of the experience gained 4. Implementers are instructed to question any doubtful point in
with the HP3000, HP300 and FOCUS syste~s. It provides two the architectural definition rather than make assumptions.
execution modes. One mode is highly co~patible with the HP3000 The specification occasionally leaves out some aspect of the
and allows execution of HP3000 user level object programs. The operation, or the wording may not be clear. In these cases
Vision mode provides advanced information processing capability. the document should be updated to resolve the point.
The Vision mode is designed to retain the general purpose nature 5. Continual maintenance and updating of the architecture
of its predecessors, but with enhanced ability to effectively specification are essential.
address both business and technical applications. Vision mode 6. At any point in time, the management will entrust maintenance
is characterized by a powerful and complete basic instruction of the architecture control document to a person or small
set, a wide range of data types, a stack for data allocation and group. They will be responsible for resolving conflicts,
procedure linkage information, data registers to support creating and reviewing document revisions, stopping debate on
expression evaluation and addressing registers to support an some issue, etc, through the use of technical and business
extremely large task and system address space, paged memory analysis or executive decision making.
management, a hierarchical protection system, and vector
processing facilities.
1-1 1-2
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1.4 Intended Audience
1.6 Notations and Conventions
This document is intended primarily as reference material for
implementors of VISION-compatible products; specifically, Algorithms in this document are described in a pidgin PASCAL.
implementors of hardware and microcode, implementors of core In these algorithms:
operating system modules and implementors of Vision compilers. NAMES in capital letters denote processor registers;
Names with only the first letter capitalized denote
The first five chapters can be used as a stand-alone intrOduction temporary or scratchpad values;
to the main VISION features; they cover the VISION addressing names in lower case denote parameters or operands.
structure, which is the most distinguishing characteristic with
respect to its predecessors and current competition in the market. The notation R[O ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo