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IB'4 1401 DATA PROCESSING SYSTEM
INSTRUCTION LOGIC
Thomas M. Mierswa
Eastern Region Systems Dept.
November 1960
TABLE OF CONTENTS
Introduction 3
Data Flow 5
Control 8
Instructions: I-Phase 10
Instructions: E-Phase 22
Common A- cycle 23
Set Word Mark 24
Clear Word Mark 24
Move 27
Move Zone 27
Move Digit 27
Load 30
Clear Storage 32
Compare 34
Move & Zero Suppress 36
Edit 39
Reset Add 46
Reset Subtract 47
Add 49
Subtract 49
True Add 54
Complement Add 58
Branch 68
T est and Branch 68
T est Character and Branch 72
Test Zone or WM and Branch 72
No Operation 74
Stop 74
Read 76
Punch 82
Print 88
Checking Features 95
INTRODUCTION
The purpose of these notes is to provide a simplified version of 1401 machine
logic for IBM Field Systems personnel. A knowledge of these principles will
aid in understanding more fully the functions that each instruction causes the
machine to perform. This knowledge, it is hoped, will also stimulate ideas
for better programming which will both reduce machine time and conserve
memory space.
These notes were compiled from the Customer Engineering Manual and from
the Logic Flow Diagrams used by Customer Engineers. No effort has been
made to present the exact sequence of events within a machine cycle because
a knowledge of partial cycle operation would be of no practical knowledge to
the Field Systems Representative.
Only the instructions in the basic 1401 card system are presented.
In the diagrams and figures included in these notes the following abbreviations
are used:
A-REG A-Register
A-STAR A-Storage Address Register
B-REG B-Register
B-STAR B-Storage Address Register
C.B. Circuit breaker
Character - All bits including check bit, zone bits, digit bits
and WM bit
C.L. Console light
Digit The l, 2, 4, 8 bits and C- bit as required
E-Phase The machine cycles required to execute an
instruction
I-OP Instruction Operation cycle during which the
instruction operation code is accessed.
I-Phase The machine cycles required to acces s the
entire instruction
I-STAR Instruction Storage Address' Register
pos. position
p. s. program skip latch set if the normal sequential
access of instructions is changed.
R.B. Read back into storage from B- register. The entire
character including the word mark bit is regenerated in
the storage location indicated in the storage address
register.
R.I. Read into some register from stor age
R.S. Reverse scan where storage positions are
accessed from a lower address (high order
position) to a higher address (low order position)
as opposed to a forward scan where storage is
accessed from a higher address (low order position)
to a lower address (high order position).
3
When reverse scan is begun, the high order
position is readdressed by not resetting the
Storage Address Register.
SAR Storage Address Register which controls the
current storage location to be accessed.
S.F. Standard form. This applies to sign indication.
A field is considered plus if it has any zone
combination other than a "B - bit" alone but a
plus sign in standard form is an "A B bit"
combination.
trig. trigger
WM Word mark
WO Without
Z.S. Zero Suppress latch
Positive logic only is shown in the diagrams. For example, if a STAR is to be
modified it is so shown but if it is not to be modified the step is omitted
rather than shown to "not happen". If a latch or trigger is turned on it will
remain on until it is shown to have been turned off or is reset on the I-OP
cycle of the next instruction. For example, if A-cycles eliminate is turned on,
all subsequent A-cycles will be eliminated until the next I-OP cycle or the
machine is told to start an A- cycle.
The following symbols are used in the diagrams and have meanings as
indicated.
machine operation
machine interrogation
o machine cycle indication
o 4
connector
DATA FLOW
Figure 1 is a schematic of the overall flow of information through the 1401.
A general description of each component follows.
Core Storage Unit
The core storage unit is the "center" of all data flow in the 1401 system.
The over -all objective of the system is to receive data from cards in the card
read-punch, process this data, and send the resultant data to the punch or
printer. The core storage unit is part of all these functions. Each character
of information enters or leaves the storage unit in BCD form.
Information is read out of storage during the early part of a cycle. Readout
is actually accomplished by setting all the cores to zero. A core set at "one"
will, when it flips from one to zero during readout, induce a voltage on one
of the wires running through the center of the core. This is recognized as a
bit.
Information is read into storage during the later half of a cycle. When
information, that is readout of a storage location, is to be retained in the
particular location, it is "transferred" from one of the registers back into
the same cores that it was read out of. This happens on the later half of the
same cycle.
Data Lines
Data flow paths shown as single lines are actually eight lines, one for each
BCD "bit value", plus one additional line for word marks. The lines leading
to the inhibit drive are called inhibit lines, and are so named because they
will prevent, or inhibit, the setting of cores unless "activated" by a bit of
information.
Information to storage is through the inhibit drive while information from
storage is through the B-register.
A- and B-Registers
The A- and B-registers are single-character storage devices used for storing
the specific characters being treated. To proces s any information from the
storage unit, it must first be brought to one or both of these registers. For
example, in certain operations involving two data fields, an A-field character
is stored in the A-register (through the B-register), and then a B-field
character is stored in the B-register. Characters thus stored may be added,
subtracted, compared, or other-wise treated. When necessary, each of
these registers can transfer its character "back" to storage, preventing the
loss of the information in the storage unit. This is neces sary because the
cores of a position are all set to zero when the particular location is read out.
5
+
...._ _ _...
I
HOL.E
COUNT
I_~
.....""""---...--t---
READER
HOL.E
COUNT
J I PUNCH I I PRINTER
CHECKS
I
VAL.IDITY J
INHIBIT
DRIVE
~ I
""""
PARITY CHECK
AL A~
A~
... CORE STORAGE
,
,.."" ,..""
~
A
liIo.
~
VAL.IDITY CHECK
LOGIC
~
B
A~ REG REG A~
PARITY PARITY
CHECK CHECK
,..-.
\
."
,..""
I"""
PARITy AND
VAL.IDITY
-
OP
REG
INSTRUCTION L.ENGTH MANUAL. ADDR.
SWITCHES
SAR P ARITY
AND
0000 VAL.IDITY
,~
+ ,,--~------
,
________________~________,,~,,________~~__- '
I
AUTO
SCAN
otl
+3
0
I ~ SET UP
,',
MODIFIER
I-STAR A-STAR B-STAR
+
FIGURE I - DATA FLOW AND CHECKING FEATURES
6
Input/Output
Holes in cards read at the card reader cause corresponding BCD characters
to be applied to the inhibit lines for storage in the storage unit. To print or
punch data, the storage unit supplies ea ch character of infor:mation through
the B-register. The circuits are controlled so that this data, in BCD for:m,
is translated to a for:m and ti:ming relationship co:mpatible with the appropriate
output device.
Operation Register
The operation register is used for storing an op code for the duration of that
operation. This register consists of seven latches (A, B, C, 1, 2,4, 8) which
are capable of storing the op code bit configurations. Any latches that are set
in the op register are decoded into a single line, na:med for the operation,
which controls the syste:m during the operation.
1-, A-, and B- Address Registers
The 1401 uses three, 3-position address registers. These address registers
are referred to as STARS (Storage Address Registers). Each STAR contains
the following latches:
1. Five in the units and tens position (8, 4, 2, 1, C)
2. Six in the hundreds position (8, 4, 2, 1, C, A). A B-latch is used in the
hundreds position if a 4k storage unit is used.
The I-STAR controls the syste:m during I-phase. On I-phase, the I-STAR
contains the address of the storage location to be read-out on the next I-cycle.
On E-phase, the A-STAR contains the address of the storage location to be
read-out on the next A-cycle. The B-ST AR contains the address of the storage
location to be read-out on the B-cycle. All three STARS operate on the
following sequence on any particular cycle:
1. Reset the units position and read in the units position.
2. Reset the tens position and read in the tens position.
3. Reset the hundreds position and read in the hundreds position.
4. Read out all positions, in parallel to the storage address register.
No checking is perfor:med in the 1-, A-, or B -STARS. Checking takes place
in other circuitry after the STAR is read-out.
7
Instruction Length
The 1401 cycle control keeps track of the I-phase cycles by triggers. The
instruction length determines the number of I-phase cycles. There can be as
few as one I-phase cycle or as many as nine. Except for the "set word mark"
instruction the word mark of the next instruction stops I-phase. The "set word mark"
instruction causes I-phase to cease on 1-6 cycle regardless of a following word mark.
A blank in storage can also stop I-phase for the unconditional branch instruction.
CONTROL
In a stored program computer, such as the 1401, the computer must distinguish
between instructions and data. The cycle-control circuits are the control
center of the 1401. All central processing is regulated by cycle control. It
controls the change from I-Phase to E-Phase and vice versa. During I-Phase
the cycle control circuitry must direct the succes sive 1- cycles and during
E-Phase it provides A and B cycle control.
Addres s Register Modification
Because each storage cycle requires scanning at a new storage address, the
address in either the 1-, A-, or B-Storage address register is modified
during the storage cycle in which it was used. During I-phase, instruction
words are scanned from high-order to low-order position under control of the
1- storage addres s r-egister. This register increases its value by one for each
I-cycle. During most E-phase operations, treatment of an A-and B- field
requires the A- and B-storage address registers to decrease in value by one
for each A- and B-cycle, respectively. Operations involving the printer require
an address to be increased by three for each storage cycle, while at other
times it is not necessary to modify an address at all.
The 1-, A-, or B- storage address register controlling storage addressing is
"updated" during the same cycle in which it is used by a modified address
received from the modifier. The modifier output is obtained by adding ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo