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File Number 8360-01
Form C20-1635-2
Systems Reference Library
IBM System/360 Model 40
Operating Techniques
This manual describes operator procedures for an IBM 2040
Processing Unit. It is intended to be a handy reference manual
for the user to take to an IBM Test Center for preparation of
testing materials.
For information pertaining- to operation of the units attachable to
8ystem/360 Model 40, refer to the appropriate 8RL publication.
8RL publications that pertain to IBM System/360 and attachable
units are abstracted and referenced by form number in IBM
8ystem/360 Bibliography (A22-6822).
CONTENTS
Page Page
System/360 Model 40 Configuration Example 1 Main Storage 4
System Configuration 1 fustruction COWlter 4
CPU Features 1 Storage Protection 4
I/O Units and Addresses 1 Altering - Storage Select Switch 4
I/O Address Assignment Example 1 Main Storage 4
Current PSW, FP, and GP Registers 4
fustruction COWlter 4
FWlctions of the mM 2040 System Control
Storage Protect Key 5
Panel 1
Continuous Looping 5
Keys 1
Address Stop 5
Switches 2
Analyzing an Unexpected Wait State
Lights 2
Condition 5
Data and Address--Lights and Switches 2
Analyzing fuput/Output Commands 5
System/360 Operating Techniques 3
hlitial Program Loading (IPL) 3 Appendix A:
Clear storage--Manually 3 Reference Tables for the System/360 7
Displaying--Storage Select Switch 3 Units
Floating Point Registers 3
General Purpose Registers 3 Appendix B:
Current Program Status Word 3 IBM 2040 System Control Panel 12
Major Revision
This edition, C20-1635-2, is a major revision and completely obsoletes
C20-1635-1. It removes a programming example no longer applicable,
and updates the reference tables in Appendix A.
Copies of this and other IBM publications can be obtained through IBM branch
offices. Address comments concerning the contents of this publication to
IBM, Technical Publications Department, 112 East Post Road, White Plains, N. Y. 10601
SYSTEM/360 MODEL 40 CONFIGURATION
EXAMPLE
SYSTEM CONFIGURATION' C 2540 Reader
D 2540 Punch
CPU Features E 1403 Printer
9 1052 Typewriter-Keyboard
128K Storage Capacity o to 9 = Tape or Disk Address
Storage Protection Feature
For example: I/O address OOA would be inter-
Mode Set Commands (TAU Modifier Bits)
preted as being on the multiplexor channel whose
Universal Instruction Set
subchannel is O. The particular device selected
One Multiplexor Channel
is A, the 1442; I/o address 189 would be the tape
Two Selector Channels
drive number 9 on selector channel 1.
Interval Timer
I/O Units and Addresses FUNCTIONS OF THE mM 2040 SYSTEM
CONTROL PANEL
DEVICK ADDRESS
Tapes (2400), Selector 180, 181 -- 7 track,
Channell The System Control Panel contains the switches,
182, 183 -- 9 track
keys, and lights necessary to operate and control
Tapes (2400), Selector 280, 281 -- 7 track, the system. The controls are divided into three
Channel 2 282, 283 -- 9 track sections: operator control, operator intervention,
Card Reader- Punch (1442) OOA and field engineering control. In the follOwing
discussion, the operator's console refers to the
Printer (1443) OOB former two sections, which constitute the lower
half of the System Control Panel. The engineering
Card Reader (2540) OOC
control is the upper half.
Card Punch (2540) ODD All the keys, lights, and switches necessary
for operator control and intervention are subse-
Printer (1403) DOE
quently discussed; refer to Appendix D for the
Typewriter- Keyboard (1052) 009 IBM 2040 Console diagram.
Disk Storage (2311) 190 KEYS
NOTE: LOAD/SYSTEM RESET forces Mode LOAD -- loads from the II 0 unit specified in the
Set on all channels to 800 bpi, odd parity, data three LOAD UNIT SWITCHES on the console. De-
converter on, translator off, unless otherwise pressing the LOAD key causes execution of the
requested. Mode set applies only to 7 -track tapes, system reset internal diagnostic sequence, then loads
with the exception of track-in-error sense infor- the first 24 bytes of information from the load unit
mation, which applies to 9-track tapes (1600 bpi). into the first 24 bytes of main storage. This pro-
cedure is called initial program load (IPL).
START -- starts instruction execution in the
I/O ADDRESS ASSIGNMENTS EXAMPLE
manner defined by the RATE switch. This key is
effective only when the CPU is in the stopped or
The three position device address XYZ indicates: manual state.
X -- Channel
STOP -- causes the CPU to enter the stopped
o multiplexor state as indicated by the MANUAL light on the
1 = selector channel 1 console.
2 = selector channel 2
SYSTEM RESET -- stops all instruction proc-
Y -- Control Unit essing; resets all indicators and lights on the
o peripheral or unit record console; resets channels, online nonshared control
8 = magnetic tapes units, and I/O devices. It also restores the tape
9 = disk files modes on all channels to their original setting
Z -- Device (usually 800 bpi odd parity, data converter on,
A 1442 Card Reader- Punch translator off). It does not reset any of the regis-
B = 1443 Printer ters, or alter main storage.
1
CHECK RESET -- resets the three main error Interval Timer is not updated when the switch
triggers. Specifically, it resets the EARLY, LATE is in this position.
and C' NTRL lights in the upper left portion of the SINGLE-CYCLE (ordinarily for customer engi-
System Control Panel. It does not reset any of the neering use only). In this position single-cycling
registers or channels. of each phase of an instruction is allowed.
PSW RESTART -- causes the IPL PSW to be STORAGE SELECT (a rotary switch) -- selects
fetched from core storage location zero (provided the the storage area to be addressed by the ADDRESS
CPU is in the manual state). The CPU then continues switches. It can be manipulated without disrupting
to process starting at the location indicated by the CPU operations, and has the following settings:
Instruction Address portion of the IPL PSW. FP -- Floating Point Registers
INTERRUPT -- requests an external interrupt, GP -- General Purpose Registers
provided the PSW is masked to allow external PSW -- Current Program Status Word
interrupts. MS -- Main storage
STORE -- causes the information specified by IC -- Instruction Counter
the INSTRUCTION COUNTER OR STORAGE SP -- Storage Protect
ADDRESS and STORAGE DATA keys to be entered
in the area specified by the STORAGE SELECT LIGHTS
switch. When the STORE key is being used,
storage protection is ignored. LOAD -- is turned on when the LOAD key is pressed
DISPLAY -- displays information in the loca- for initial program loading (IPL), and remains on
tion specified by the STORAGE SELECT and until the loading process has been terminated (that
STORAGE ADDRESS switches. is, until the CCWs have been successfully executed).
POWER ON, POWER OFF -- initiates the power WAIT -- is on when the CPU is in the wait state.
on or power off sequence for the entire system. MANUAL -- is on when the CPU is in the stopped
Before initiating the power off sequence each I/O state or manual mode (caused by pressing the STOP
device must be at its not ready or unloaded state. key or the SYSTEM RESET key). In this state, the
CPU is not actually stopped, but rather is cycling
SWITCHES through the microprogram. To exit from this state
(that is, to resume instruction processing), press
ADDRESS COMPARE (a rotary switch) -- provides the START key.
the means of stopping the CPU at a predetermined TEST -- is on when the ADDRESS COMPARE,
address (indicated by the INSTRUCTION COUNTER INTERFACE CONTROL, CPU, and RATE switches
OR STORAGE ADDRESS keys) when in the MS are in other than their normal pOSitions.
position. An equal address comparison causes the SYSTEM -- is on when the CPU is in the
CPU to enter the manual state. running state.
LOAD UNIT ( three rotary switches) -- provides
the "XYZ" (eleven-bit) address of the input device DATA AND ADDRESS -- LIGHTS AND SWITCHES
to be used for initial program loading. The left-
most switch, corresponding to the "X" position of Directly above the System Control Panel keys are
the device address, has eight positions labeled two individual sets of lights and switches. They
0-7. The other two switches, "Y" and "Z", have each have a length of two bytes (one halfword).
16 positions each, and are labeled with the hexa- STORAGE DATA -- specify the data to be stored
decimal characters 0 - F. (Refer to the II0 in the location indicated by the INSTRUCTION
address assignments example given earlier. ) COUNTER OR STORAGE ADDRESS keys, and the
RA TE (a rotary switch) -- indicates the manner STORAGE SELECT switch. The lights directly
in which instructions are to be performed. The above the STORAGE DATA keys indicate the infor-
position of the switch should be changed only while mation being displayed or stored.
the CPU is in the manual state. The RATE switch INSTRUCTION COUNTER OR STORAGE
has the following settings: ADDRESS -- specify the address of the halfword of
PROCESS. In this position, the system operates storage to be altered or displayed; these keys may
at normal speed. also be used to indicate the number of the register
INSTRUCTION STEP. When the START key is (general purpose or floating point) to be altered or
pressed with the RATE switch in this position, displayed. They can be manipulated without disrupt-
one complete instruction is performed, and the ing CPU operations only when the ADDRESS
CPU then returns to the manual state. T)1e COMPARE switch is in the PROCESS position.
2
SYSTEM/360 OPERATING TECHNIQUES
INITIAL PROGRAM LOADING (IPL) in the manual state. The STORAGE SELECT switch
and the STORAGE ADDRESS keys are used for the
Initial program loading is started manually by se- register select, etc. All the data is displayed in
lecting the desired input device with the three LOAD the STORAGE DATA registers, bytes 0 and 1, except
UNIT (XYZ) switches, and then pressing the LOAD as indicated.
key. The first 24 bytes (six words) of information
are loaded from the device selected into positions Floating Point Registers
0-23 of storage. These positions contain the initial
program load program status word (IPL PSW), and 1. Press the STOP or SYSTEM RESET key.
the two channel command words (CCW) after initial 2. Set the STORAGE SELECT switch to FP.
loading. The IPL PSW will be in positions 0-7, and 3. Set the following bits in byte 1 of the STOR-
the CCWs in 8-23. If loading was not successful, AGE ADDRESS keys:
the CPU idles (SYSTEM light is on) and the LOAD Bits 0-3 (REGISTER SELECT switches), for
light remains on. the desired register to be displayed.
If, at the beginning of a job, any individual unit Bits 4-5, ignore.
cannot be readied, press the SYSTEM RESET key Bits 6-7 (HALFWORD SELECT switches), to
on the console. This should reset all unusual con- indicate which halfword is to be displayed,
ditions. (Note, however, that if this key is de- as follows:
pressed while running a job, information already on First halfword -- 00
the channels or interface units will be lost. ) Second halfword -- 01
Since this IPL procedure executes the same in- Third halfword -- 10
ternal diagnostic sequence and reset functions that Last halfword 11
the SYSTEM RESET key performs, the SYSTEM 4. Press the DISPLAY button.
RESET key need not be pressed before IPL.
General Purpose Registers
CLEAR STORAGE -- MANUALLY
1. Press the STOP or SYSTEM RESET key.
The following procedure for clearing storage man- 2. Set the STORAGE SELECT switch to GP.
ually does not clear the general purpose or floating 3. Set the following bits of byte 1 of the STOR-
point registers: AGE ADDRESS bit switches:
1. Press the DSAB INTVL TIMER (disable Bits 0-3 (REGISTER SELECT switches), for
interval timer) switch down. the desired register to be displayed.
2. Press the SYSTEM RESET key Bits 4-5, ignore.
3. Set the RATE switch to SINGLE CYCLE Bits 6-7 (HALFWORD SELECT switches), to
4. Set the DIAGNOSTIC CONTROL switch to indicate which halfword is to be displayed,
MS ADDRESS as follows:
5. Set bit 3 of byte 0 of the STORAGE DATA First halfword -- 00
keys in the down position to address the clear stor- Second halfword -- 01
age microprogram. 4. Press the DISPLAY button.
6. Flip up the STORAGE STATS switch
7. RESET the RATE switch to PROCESS Current Program status Word
8. Press START. This causes the microprogram
that sets all of main storage to zeros to be executed. 1. Press the STOP or SYSTEM RESET key.
None of the STORAGE DATA lights should be on, 2. Set the STORAGE SELECT switch to PSW.
but the microprogram light ( J.l. P light in the upper 3. Set the follOwing bits in byte 1 of the STOR-
left-hand portion of the field engineering console) AGE ADDRESS keys:
should be on, to indicate successful completion. If Bits 0-3 (REGISTER SELECT switches), ignore
this light does not come on, or if any other lights Bits 4-5, ignore.
on the field engineering console are on, the clear Bits 6-7 (HALFWORD SELECT switches), to
storage procedure was not successful. indicate which halfword is to be displayed, as follows:
First halfword -- 00
DISPLAYING -- STORAGE SELECT SWITCH Second halfword -- 01
Third halfword -- 10
All console displaying on the System/360 Model 40 Last halfword 11
is done a halfword at a time only when the system is 4. Press the DISPLAY button.
3
Main storage state) always involves two bytes at a time, even
though only one of the bytes may be actually changed.
1. Press the STOP or SYSTEM RESET key. The procedure is as follows:
2. Set the STORAGE SELECT switch to MS. 1. Press the STOP or SYSTEM RESET key.
3. Set the STORAGE ADDRESS keys for the de- 2. Set the STORAGE SELECT switch to MS.
sired storage address. 3. Set the STORAGE ADDRESS keys to the ad-
4. Press the DISPLAY button. dress of the data to be changed.
(Note that two bytes are always displayed in the 4. Set the STORAGE DATA keys as follows:
STORAGE DATA lights at one time; byte 0 always If the content of an even numbered address is to be
displays the contents of an even numbered address, changed, set the new data in the byte 0 STORAGE
and byte 1 of the next higher odd numbered address. DATA keys. Also, since two bytes are always stor-
If an even numbered address is set into the STOR- ed at the same time, the data already stored in the
AGE ADDRESS keys, byte 0 of the STORAGE DATA odd numbered address (next above the even address
lights displays the contents of that address, and byte being changed) must be repeated in byte 1 of the
1 displays the contents of the next higher odd num- STORAGE DATA keys, so that it may be "restored"
bered address. If an odd numbered address is set at the same time the contents of the even numbered
into the STORAGE ADDRESS keys, byte 1 of the address are changed.
STORAGE DATA lights displays the contents of the If the content of an odd numbered address is to be
odd numbered address, and byte 0 displays the con- changed, set the new data in the byte 1 DATA STOR-
tents of the next lower even numbered address. ) AGE keys, and "repeat" the data already stored in
the next lower even numbered address in byte 0 of
Instruction Counter (Instruction Address Portion of the STORAGE DATA keys.
PSW) 5. Press the STORE key; the data stored will
be displayed in the STORAGE DATA lights.
1. Press the STOP or SYSTEM RESET key.
2. Set the STORAGE SELECT switch to IC. Current PSW, FP, and GP Registers
3. Press the DlSPLAY key. The entire 3 bytes
of the IC are displayed; the first byte is in byte 1 of The procedure for changing data in any of these reg-
the STORAGE DATA lights; the second byte is in isters (done only when the system is in the manual
byte 0 of the INSTRUCTION COUNTER lights; and state) which is similar to the procedure for displaying
the third byte is in byte 1 of the INSTRUCTION the respective registers is as follows:
COUNTER lights. 1. Press the STOP or SYSTEM RESET key.
2. Set the STORAGE SELECT switch to select
storage Protection the desired type of register.
3. Set bits 0-3 of byte 1 of the STORAGE AD-
1. Press the STOP or SYSTEM RESET key. DRESS keys to select the desired number of the
2. Set the STORAGE SELECT switch to SP. register.
3. Set in the STORAGE ADDRESS bit switches 4. Set bits 4-7 of byte 1 of the STORAGE AD-
the storage address for which the protection infor- DRESS keys to select the halfword to be changed.
mation is desired. 5. Set the STORAGE DATA keys for the half-
4. Press the DISPLAY button; the following in- word of data to be stored.
formation will be displayed in bytes 0 and 1 of the 6. Press the STORE key; the data stored will be
STORAGE DATA lights: displayed in the STORAGE DATA lights.
a. Byte 0 will be cleared. 7. Repeat steps 3 through 5 for all halfwords of
b. Bits 0-3 (SP DATA) of byte 1 contain the data to be changed.
protection key for the block of core in which
the desired storage address is located; Instruction Counter
this is called the "protection data"
c. Bits 4-7 (SP KEY) contain the protection To manually transfer to another location in main
key in the current PSW (bits 8-11 in the storage (that is, to set the IC to a new starting point)
(PSW); this is called the "protection tag". when the CPU is in any state other than the wait
state:
ALTERING -- STORAGE SELECT SWITCH 1. Press the STOP key to place the CPU in the
Main Storage manual state.
2. Set the STORAGE SELECT switch to IC.
The altering or changing of the contents of main stor- 3. Set the STORAGE ADDRESS keys to the trans-
age (done only when the system is in the manual fer location.
4
4. Press the STORE button. ADDRESS STOP
5. Press the START button to resume processing To stop the CPU at a specified address:
at the new location. 1. Press the STOP key.
NOTE: The transfer to another location can also 2. Set the ADDRESS COMPARE switch to MS
be accomplished by altering the Instruction Address STOP.
(last three bytes) of the current PSW. 3. Place the desired address in the STORAGE
To alter the IC in wait state, the wait state bit in ADDRESS keys.
the current PSW (bit 14) must first be cleared. This 4. Press the START button.
returns the system to the operating state as indicated The system will resume processing until an equal
by the SYSTEM light on the console. address comparison is made. The CPU then
1. Press the STOP or SYSTEM RESET key. switches itself to the manual state. This condition
2. Display the first halfword of the current PSW will occur when an equal comparison is made on
in the STORAGE DATA lights. an instruction or a data address.
3. Restore the contents of the first halfword with
the exception of the wait state bit (byte 1, bit 6 in the ANALYZING AN UNEXPECTED WAIT STATE CON-
Storage Data lights). This turns the wait state off. DITION
4. Follow the above steps for transferring to an-
other location of storage If the CPU unexpectedly switches to the wait state as
indicated by the WAIT light on the console, the con-
Storage Protect Key tents of the current PSW should be examined, and
then a core dump should be taken. Note that PSWis
To change the protection information associated with an internal register that will be destroyed by any
a given block of core (in blocks of 2048 bytes): core dump program.
1. Press the STOP button. If any of the System/360 BPS Utility programs are
2. Set the STORAGE SELECT switch to SP. being used, bits 40 to 63 of the current PSW, which
3. Set the STORAGE ADDRESS keys to the stor- normally contain the instruction address, will con-
age address that is to be changed. tain a three-byte BCD message indicating the type of
4-. In the SP DATA keys, bits 0-3 of byte 1, key error. For example, if the instruction address field
in the new "Protection Data"; in bits 4-7 (SP KEY) of the current PSW contains D3D7Cl, decoded LPA,
of byte 1, key in the new "Protection Tag" (byte 0 is this signifies that a program check has occurred; a
ignored for this operation). core dump helps to investigate further the cause.
5. Press the STORE button. In this example, the old program PSW should be ex-
6. Press the START button to resume processing. amined starting in location 28 hexadecimal. This
action helps to isolate the cause of the program
CONTINUOUS LOOPING check and where it occurred. The instruction ad-
dress (which caused the wait state) minus the instruc-
When a program is continuously looping in execution tion length code is found at location hexadecimal
(indicated by console lights steadily flashing, and no 2E.
indication of correct processing) and it is desired to Under the BPS packages, an I/ 0 interrupt will al-
trace the loop: so switch the CPU to the wait state. In this case,
1. Press the STOP button. the above procedure should be followed, except that
2. Record the current PSW. the old I/o PSW (starting in hexadecimal location
3. Record the CAW, if the loop involves some 38) should be examined instead of the old program
I/O function. PSW.
4. Set the STORAGE SELECT switch to IC. Refer to Operating Guide for Basic Assembler
5. Set the RATE switch to INSTRUCTION STEP. and Utilities (C28-6557) for the list of codes (and
6. Press the START key; one instruction is ex- corresponding descriptions) that replace the instruc-
ecuted, and the address of the next sequential instruc- tion address in the current program PSW following
tion is displayed in the STORAGE ADDRESS lights. an unexpected switch by the CPU to the wait state.
Record the displayed address, and keep pressing the Appendix C contains a reference list.
START key until this recorded address is again dis-
played in the STORAGE ADDRESS lights, that is, un- ANALYZING INPUT/OUTPUT COMMANDS
til one loop is completed.
For analyzing II 0 commands for any reason what-
7. Reset the RATE switch to PROCESS.
ever, the procedure for using either the console or
8. Take a core dump.
a core dump to determine the last I/o command
5
issued, the device associated with that command, and c. The residual byte count should be zero at
the status or result of the execution of that command, the completion of the I/o command. other-
is as follows: wise, one of three things is indicated:
1. Examine the Channel Address Word (CAW -- (a) a wrong-length record was encountered;
fullword at location 48 hexadecimal), which contains (b) a command reject was issued from the
the address of the Channel Command Word (CCW). channel for the last I/o command received
(Refer to Appendix C for formats.) - in either of these two cases, something
may be wrong with the user's channel pro-
( NOTE: If I/O command chaining was gram; (c) a data check occurs during a
employed, the CAW will contain the address read or write operation causing data trans-
of the first CCW.) fer to stop at the point where the error
occurred, and causing device motion to
2. Analyze the Channel status Word (CSW -- stop at the end of the affected record.
doubleword starting at location 40 hexadecimal). Channel end, device end, unit check and
The CSW has three significant parts: (a) the com- incorrect length indications are posted in
mand address of the CCW, (b) the status of the chan- the CSW, and the residual byte count may
nel, etc., and (c) the residual byte count (which indicate the amount of data not stored.
may be zero). When working with variable-length records, the
a. The command address portion of the CSW wrong-length record indication in the CCW bit 34
always contains the address of the last should be on; otherwise, every time a record with a
CCW executed plus eight bytes. count different from that specified in the CCW is en-
b. The status portion (bits 32 through 47) of countered, bit 41 in the CSW (incorrect length) will
the CSW halfword at location 44 hexadec- be turned on, causing an I/O interrupt (if the Basic
imal contains the status of the channel I/o subroutines are used, the CPU will enter the
control unit or subchannel, and the status wait state).
of the device to which the I/ 0 command 3. Check the Channel Command Word (CCW--
was issued. Each I/o device that can be doubleword location on any doubleword boundary in
attached to the system has its own char- storage). The CCW contains the data address, a byte
acteristics as far as status bits are con- count indicating the number of bytes involved in the
cerned. Refer to the individual SRL for operation, the command code defining the actual I/O
each I/o device status bit meaning, as operation, and the flag bits (if any) for command and
they vary. The address of the particular data chaining, etc. Note that, initially, there must
device to which the I/O command was di- be a byte count of one or more for any I/O operation,
rected can normally be found in the Interrup- except Transfer in Channel (TIC). (For the defini-
tion Code portion (bits 16 through 31) of tions of I/O device command codes, refer to the
the old I/o PSW at location 3A hexadeci- individual SRLs; Appendix B contains a reference
mal. list. )
6
APPENDIX A: REFERENCE TABLES FOR THE
SYSTEM/360 UNITS
OPERATION CODES FOR:
RR FORMAT INSTRUCTIONS RX FORMAT INSTRUCTIONS
11\ Deci-
Hexa- Graphic & Con- (2) Punched System/3ffi 11\ Hexa-
Oeci- deci-
Graphic &Con- (ZI
7-Track Tape
Punched System/3ffi
8-bit
deci- Mnemonic Irol S~mbols 7-Track Tape Card 8-bit (3) Mnemonic trol S~mbols Card 131 ($)
mal mal mal BCOIC
mal BCDIC EBCDIC BCDIC Code Code BCOIC EBCDIC Code Code
12-{)-9-8 1 (XXXI (XXXI ccw 64 4D STH SP (ZI no punches 0100 (XXXI ccw
0 00 IZ-{)-9-1
12-9-1 0001
(XXXI 65 41 LA 0100 0001
1 01 IZ-{)-9-Z
12-9-2 0010 66 42 STC 0100 0010
2 02 (XXXI
67 43 IZ-{)-9-3 0100 0011
12-9-3 0011
(XXXI
IC
3 03 68 44 EX 12-{)-9-4 0100 0100
4 04 SPM PF 12-9-4 (XXXI 0100
12-{)-9-5
~ 45 BAL 0100 0101
5 05 BALR HT 12-9-5 (XXXI 0101
IZ-{)-9-6
70 46 BCT 0100 0110
6 06 BCTR LC 12-9-6 (XXXI 0110 IZ-{)-9-7 0100 0)))
71 47 BC
7 07 BCR DEL 12-9-7 (XXXI Olll 12-{)-9-8
7Z 48 LH 0100 1000 ccw
8 08 SSK 12-9-8 (XXXI 1000 ccw
9 09 ISK 12-9-8-1 (XXXI 1001
73
74
49
4A
CH
AH , 12-8-1
12-8-Z
0100 1001
0100 1010
10 OA SVC 12-9-8-2 (XXXI 1010 :il 75 4B SH BA8 Z 1 12-8-3 0100 lOll
~ 11 OB 12-9-8-3 (XXXI 1011 76 4C MH III < B A 84 12-8-4 0100 1100
12-9-8-4 t (
.9 12 OC (EBCDIC +1 0000 1100 ;: 77 40 [ ( B A 84 1 12-8-5 0100 1101
~ 13 00 (EBCDIC -I 1~-9-8-5
12-9-8-6
0000 1101
~ 78 4E CVO < + B A 84 Z
BA8421
12-8-6
12-8-7
0100 1110
0100 1111
+
0000 1110 79 4F CVB
~ 14 OE I
~ I'"
15 OF CUI 12-9-8-7 0000 1111 -ll ~ 50 ST & t & BA lZ 01010000 ccw
] 16 10 LPR 12-11-9-8-1 0001 (XXXI ccw
~ 81 51 lZ-11-9-1
lZ-11-9-2
01010001
01010010
LNR 11-9-1 00010001 82 5Z
~ 17 11
18 12 LTR 11-9-2 00010010 83 53 12-11-9-3 01010011
19 13 LCR 11-9-3 00010011 84 54 N 12-11-9-4 01010100
20 14 NR RES 11-9-4 00010100 85 55 CL IZ-II-9-5 01010101
15 CLR NL 11-9-5 00010101 86 56 0 IZ-I1-9-6 01010110
21
11-9-6 00010110 87 57 X IZ-1I-9-7 0101 om
22 16 OR BS
11-9-7 88 58 L 12-11-9-8 0101 1000 ccw
23 17 XR IL ooo10111
89 59 C 11-8-1 0101 1001
24 18 LR 11-9-8 0001 1000 ccw
90 5A A ! 11-8-2 0101 1010
25 19 CR 11-9-8-1 00011001 11-8-3
91 5B S $ $ B 8 2I 0101 lOll
26 lA AR CC 11-9-8-2 0001 1010 5C M 84 11-8-4 0101 1100
92 B
27 IB SR 119-8-3 00011011 93 50 0 1 ) B 84 I 11-8-5 01011101 )
28 lC MR 11-9-8-4 00011100 94 5E AL B 842 11-8-6 01011110
: :
29 10 DR 11-9-8-5 00011101 j/ 95 5F SL , ""7 B 8421 11-8-7 01011111
3D IE ALR 11-9-8-6 0001 1110 Q6 ffi STD B II OliO 0000 ccw
II /1\
31 IF SLR CU2 11-9-8-7 0001 1111 97 61 I I A 1 0-1 OliO 0001
32 20 LPOR 11-{)-9-8-1 0010 (XXXI ccw 98 62 1I-{)-9-Z OliO 0010
I
33 21 LNOR 0-9-1 0010 0001 99 63 11-{)-9-3 OliO 0011
34 22 LTDR 0-9-2 0010 0010 100 64 11-{)-9-4 01100100
35 23 LCOR 0-9-3 0010 0011 101 65 11-{)-9-5 OliO 0101
36 24 HDR BYP 0-9-4 0010 0100 102 66 1I-{)-9-6 01100110
37 25 LF 0-9-5 0010 0101 103 67 1I-{)-9-7 0110 om
38 26 EOB 0-9-6 0010 0110 104 68 LO 11-{)-9-8 01101000 ccw
105 69 CD 0-8-1 01101001
! 39
40
27
28 LOR
PRE 0-9-7
0-9-8
0010 Olll
0010 1000 ccw
!
106
107
6A
6B
N AD
N SO A8 Z I
12-11
0-8-3
01101010
01101011
j 41
42
29
2A
CDR
N AOR SM
0-9-8-1
0-9-8-2
00101001
0010 1010 e lOS 6C NMO ~( ~ A 84 0-8-4 01101100
~ 43 2B N SOR 0-9-8-3 00101011 ~ 109 60 NOD v
\
A 84 I
A 84 Z
0-8-5
0-8-6
01101101
0110 mo
0-9-8-4 0010 1100 110 6E AW >
44 2C N MDR
~ 45 20 N DDR 0-9-8-5 00101101
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