Service Manuals, User Guides, Schematic Diagrams or docs for : IBM LENOVO_S100_OEM_BM5080
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5 4 3 2 1
Bitland Electronics Co.,LTD
D D
Board name: Mother Board Schematic 1. System Block Diagram & Schematic page description;
Project name: BM5XXX 2. Power Block Diagram & Discription;
Version: REV:1.X 3. Annotations & information;
initial Date: 201X-0X-XX 4. Schematic modify Item and history;
New update: 5. Power on & off Sequence;
6. ACPI Mode Switch Timings;
7. Power On Sequence Map;
8. CLOCK Distribution;
C C
9. Power Distribution;
Bitland Confidential
Hardware drawing by: Hardware check by: EMI Check by:
Power drawing by: Power check by:
B B
Manager Sign by:
A A
Bitland Information Technology Co.,Ltd
Page Name Title
Size Project Name Rev
A3 BM5080 1.2
Date: Sheet 1 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
5 4 3 2 1
5 4 3 2 1
CONTENT
Bitland Electronics Co.,LTD 1 Title
SYSTEM BLOCK Ver:C 2 System Block & Index
3 PWR Block & description
4 NOTE
5 Sch Modify and history
D 6 CK-505 D
10' TFT LVDS Pineview M
+V3.3S;+V5S DDR3
DDR3 SODIMM1 667
BGA559 667
VGA +V0.75S,+V1.5,+V3.3S
RGB +V3.3S,+V1.5S,
+V1.05S,+V1.8S
+V5S +0.89S
CK505M
Clocking Thermal Sensor
+V3.3S
ICS365 G780
+V3.3S
PCIE mini Card
WIFI DMI
x2
C C
PCIE 1X 10/100M
Tiger Point PCIE X1
RTL8105E RJ45
USB1.1/2.0 BGA360
+V1.05S,+V3.3S +V3.3AL,+V3.3S
SIM CARD +V3.3AL,+V5AL
PCIE mini Card +V1.5S,+V5S
+V3.3A_RTC
S-ATA
3G SPI SATA 2.5" HHD
+V5S,+V3.3S
BIOS
16Mbit
+V3.3AL
LPC INT MiC
USB PORT1 AZALIA
HDA
+V5AL ALC269 Audio Jack
+V5S,+V3.3S
HP/EX MIC Combo Jack
B
KB Controller/EC +V5S,+3.3S B
USB PORT2/3
+V5AL ITE8502
EC_RTC
Speaker
L
Card Reader
RTL5138 R
+V3.3S SPI
KB Matrix
SD/MMCCARD TouchPAD EC ROM
512Kbit
EC_V3.3AL
Bitland Information Technology Co.,Ltd
A A
Page Name SYS BLOCK & SCH PAGE
Size Project Name Rev
B BM5080 1.2
Date: Sheet 2 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
5 4 3 2 1
5 4 3 2 1
POWER Distribution 4A CPU
3A 0V-1.4625V VCC
S18 POWER BLOCK Ver:A 1.05V FSB VCCP
CPU Core Regulator 0.25A 1.5V VCCA
IMVP-6 Compliant
4A DDR2 SO-DIMM
Charger 2A Battery Battery
0.75A 0.75V SM VTT
VCCP,GMCH_CORE,
ISL6251 ICH_CORE 1.8V VDD/VDDQ
D 1.05V D
1.5A 4.5A AC
1.7A
CPU
1.5V DDR I/O
0.5A
Adapter VCC_CORE 6A/6.5W DDR VCC Regulator 3.3V TVDAC
Power +VDC ISL6261 V1.5
+VCC_CORE 1.05V FSB VTT
20V
3A Switch 4.5A 1.5A 4A
1.05V Core(Int)
System
VREG 1.05V VCC_PEG
7A 1.8V LVDS
9-20V
DDR VTT Regulator 2.5A 1.05V DMI
1.5A 1.5A 1.5A
V0.75S
1.05V HSIO
Always_On GFX CORE
+V1.8S/+V1.05S PWR +0.89S
Power +0.89S
TPS51117
TPS51125 TPS51117
5A 4A PCH
1.05V VCC_CPU
6A 4A +V5AL +V3.3AL 1.5A 1.05V Core
1.05V DMI
1.5V PCI Express
+V1.5 +V1.05S
1.5V Interface Regulator 1.5V SATA
TPS51117 TPS51117
4A 3A V1.5S 1.5V LAN
1A 1.5V USB
+V5S
0.4A 4A
V5S 0.1A 1.5V AZALIA
1A 1A +V3.3S +V1.8S
uP7710 5.0V Interface Regulator
1.5V AL
V5A V5AL
0.1A 5VRef
C C
5VrefSus
+V1.5S +V0.75S LDO EC_RTC 3.3VBG
APL5331
RTC
3.3V Interface Regulator
V3.3S 0.1A 3.3V IDE/PCI
V3.3A 3A 0.5A 3.3V VccSus
1.5VSUS(IntVR)
4A V3.3AL
0.5A 1.05VSUS(Int/ExtVR)
0.5A USB(Each port)
V5A
1.5A
SATA
1A V3.3S&V5S
Platform
Logic
BLUETOOTH
0.5A V3.3S
VR_ON
VR_TT#
VIN 0.5A Camera
Vcc_core V5AL
V_5 IMVP-6 VID[6...0]
PSI#
V_3
DPRSTP#
B B
CLK_ENABLE#
IMVP6_PWRGD
DPRSLPVR
Vcc_sense
Vss_sense
0.5A 0.5A
LVDS VDC
0.5A V3.3S,VDC or V5S
DPRSTP# PSI# PROCHOT# 0.3A CK505-M
Tiger point CPU_PWRGD CPU V3.3S
0.5A EC&SPI
EC_RTC
CLK 0.25A Azalia
CHIP 0.25A V5,V3.3S
1A Mini-PCI Express
1A Each slot
0.5A +1.5V&+V3.3AL&+V3.3S
0.25A CRT
0.5A V5S,V3.3S
A A
0.4A LAN
V3.3AL
0.25A FAN Bitland Information Technology Co.,Ltd
V5S
Page Name PWR Block & description
Size Project Name Rev
0.8A CardReader
D BM5080 1.2
Date: Sheet 3 of 42
V3.3AL PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
5 4 3 2 1
5 4 3 2 1
Voltage Rails
I2C SMB Address
+VDC Primary DC system power supply (9V-20V)
Device Address Hex Master
+VBATTERY Battery Power supply (9-20V) Clock Generator 1101 001x D2 ICH7-M
D D
+VCC_CORE Core Voltage for CPU
SO-DIMM0 1010 000x A0 ICH7-M
CPU Thermal Sensor 1001 100x 98 KBC
+V1.05S 1.05V for Pineview & Tiger point core / FSB VTT Smart Battery 0001 011x 16 KBC
+V1.5 1.5V power rail for DDR3
PCIE Slot TBD TBD ICH7-M
+V0.75S 0.75V DDR3 Termination voltage
+V3.3AL 3.3V always on power rail
Power States
+V5AL 5V for ICH7-M's VCC5 Refsus
Signal SLP_S3# SLP_S4# SLP_S5# +V*ALW +V* +V*S Clock
+V3.3S 3.3V main power rail
S0(Full On) HIGH HIGH HIGH ON ON ON ON
+V5S 5V main power rail
S3(STM) LOW HIGH HIGH ON ON OFF OFF
+V0.89S 0.89V for GFX
S4(STD) LOW LOW HIGH ON OFF OFF OFF
C C
Board stack up description S5(SoftOff) LOW LOW LOW ON OFF OFF OFF
PCB Layers
Top(Signal1)
Trace Impedence:55ohm +/-15%
Power
Wake up Events
Ground
LID switch from EC
Bottom(Signal4)
Power switch from EC
B B
PCB Footprints
3 5 4
USB Table
SOT23 SOT23_5
USB Port# Function Description
1 2 1 2 3
0
1
2
3 ns: Component marked "ns" is not stuff
4
5
A 6 Bitland Information Technology Co.,Ltd A
7 Page Name Notes & Anotation
Size Project Name Rev
A3 BM5080 1.2
Date: Sheet 4 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
5 4 3 2 1
Schematic modify Item and history:
D D
C C
B B
A A
Bitland Information Technology Co.,Ltd
Page Name Sch Modify and history
Size Project Name Rev
A3 BM5080 1.2
Date: Sheet 5 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
5 4 3 2 1
5 4 3 2 1
7,8,9,10,11,12,13,14,15,17,18,19,20,21,22,25,28,29,30,36 +V3.3S +V3.3S
+V3.3S FB38
fb0603
120ohm/100MHZ
1 2 +V3.3S_CK_VDD +V3.3S 7,8,9,10,11,12,13,14,15,17,18,19,20,21,22,25,28,29,30,36
+V1.05S 8,9,10,11,12,34
1
C3091 C3092
4.7uF/6.3V,X5R 0.1UF/10V,X5R
1
c0603 C3093 C3094 c0402
2
4.7uF/6.3V,X5R 0.1UF/10V,X5R
D
+V3.3S +V1.05S C3095 C3096 c0603 c0402 +V3.3S_CK_VDD D
2
0.1UF/10V,X5R 0.1UF/10V,X5R U509
c0402 c0402 +V3.3S_CK_VDD ICS9LPRS365 Remove serial resistor
tssop64_0d5_8d0 SMBUS ADD:1101 001X swap pins for layout
1
1
FB39 FB40 2
NC_100ohm@100MHz,3A 120ohm/100MHZ 9 VDD_PCI 48
FB0603 FB0603 C3097 16 VDD_48 IO_VOUT
0.1UF/10V,X5R +V3.3S_CK_VDD 61 VDD_PLL3 63
VDD_REF SMB_DATA SMB_DATA_S 11,13
2
2
c0402 64
SMB_CLK SMB_CLK_S 11,13
39
+VDDIO_CLK +V3.3S_CK_VDD 55 VDD_SRC
C3098 C3099 VDD_CPU 38
SRC5/PCI_STOP# PM_STPPCI# 11
C3101 10uF/6.3V,X5R 0.1UF/10V,X5R +VDDIO_CLK 12 37
VDD_IO SRC5#/CPU_STOP# PM_STPCPU# 11
10uF/6.3V,X5R c0805 c0402 C3100 +VDDIO_CLK 20
c0805 0.1UF/10V,X5R +VDDIO_CLK 26 VDD_PLL3_IO 54
VDD_SRC_IO_1 CPU0 CLK_CPU_BCLK 8
c0402 36 53
VDD_SRC_IO_2 CPU0# CLK_CPU_BCLK# 8
+VDDIO_CLK 45
C3102 C3103 +VDDIO_CLK 49 VDD_SRC_IO_3 51
VDD_CPU_IO CPU1 CLK_MCH_BCLK 7
V1.0 DEL NC_10uF/6.3V,X5R 0.1UF/10V,X5R 50
CPU1# CLK_MCH_BCLK# 7
c0805 c0402 1 1
ICTP T87 PCI0/OE#_0/2_A 47
SRC8/CPU2_ITP CLK_MCH_3GPLL 7
V1.0:ADD R3771@RTM875T-606 ICTP 1 3 46
T88 PCI1/OE#_1/4_ASRC8#/CPU2#_ITP CLK_MCH_3GPLL# 7
+VDDIO_CLK R3771 NC_10K_J r0402TME 4 34
PCI2/TME SRC10 CLK_PCIE_LAN 19
C3104 C3105 C3106 C3107 35
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