Service Manuals, User Guides, Schematic Diagrams or docs for : Intel Legacy Package_databook_1999 ch_01

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Introduction                                                                                                   1

1.1           Overview Of Intel Packaging Technology
              As semiconductor devices become significantly more complex, electronics designers are
              challenged to fully harness their computing power. Transistor count in products is expected to
              exceed 100 million. With a greater number of functions integrated on a die or chip of silicon,
              manufacturers and users face new and increasingly challenging electrical interconnect issues. To
              tap the power of the die efficiently, each level of electrical interconnect from the die to the
              functional hardware or equipment must also keep pace with these revolutionary devices. Package
              design has a major impact on device performance and functionality.

              Today, submicron feature size at the die level is driving package feature size down to the design-
              rule level of the early silicon transistors. At the same time, electronic equipment designers are
              shrinking their products, increasing complexity, setting higher expectations for performance, and
              focusing strongly on reducing cost. To meet these demands, package technology must deliver
              higher lead counts, reduced pitch, reduced footprint area, provide overall volume reduction, aid in
              system partitioning, and be cost effective.

              Circuit performance is only as good as the weakest link. Therefore, a significant challenge for
              packaging is to insure it does not gate device performance. While packaging cannot add to the
              theoretical performance of the device design, it can have adverse effects if not optimized. Package
              performance, therefore, is the best compromise of electrical, thermal, and mechanical attributes, as
              well as the form factor or physical outline, to meet product specific applications, reliability and
              cost objectives.

              The continuing demand for higher performance products is requiring levels of package
              performance unattainable by the molded plastic and ceramic packages of the past decade. These
              factors have driven a variety of major innovations in Intel packaging. Intel had in past years
              introduced organic packaging with copper interconnect for improved electrical characteristics.
              Intel has recently introduced flip chip between die and package as an interconnect approach to
              further improve performance and offer very compact packaging. This has resulted in new classes
              of technology using organic substrates for both surface mount (Organic Land Grid Array - OLGA)
              and thru-hole (Flip Chip Pin Grid Array - FCPGA). The microPGA (

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