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Leaded Surface Mount Technology
(SMT) 7
7.1 Introduction
Traditional through-hole Dual In-Line Package assemblies reached their limits in terms of
improvements in cost, weight, volume, and reliability at approximately 68L. SMT allows
production of more reliable assemblies with higher I/O, increased board density, and reduced
weight, volume, and cost. The weight of printed board assemblies (PBAs) using SMT is reduced
because surface mount components (SMCs) can weigh up to 10 times less than their conventional
counterparts and occupy about one-half to one-third the space on the printed board (PB) surface.
SMT also provides improved shock and vibration resistance due to the lower mass of components.
The smaller lead lengths of surface mount components reduce parasitic losses and provide more
effective decoupling
The smaller size of SMCs and the option of mounting them on either or both sides of the PB can
reduce board real estate by four times. A cost savings of 30% or better can also be realized through
a reduction in material and labor costs associated with automated assembly.
7.2 Types Of Surface Mount Technology
SMT replaces DIPs with surface mount components. The assembly is soldered by reflow and/or
wave soldering processes depending on the mix of surface mount and through-hole mount
components. When attached to PBs, both active and passive SMCs form three major types of SMT
assemblies, commonly referred to as Type 1, Type II, and Type III (see Figure 7-1).
Type I is a full SMT board with parts on one or both sides of the board.
Type II is probably the most common type of SMT board. It has a combination of through-hole
components and SMT components. Often, surface mount chip components are located on the
secondary side of the Printed Board (PB). Active SMCs and DIPs are then found on the primary
side. Multiple soldering processes are required.
Type III assemblies are similar to Type II. They also use passive chip SMCs on the secondary side,
but on the primary side only DIPs are used.
2000 Packaging Databook 7-1
Leaded Surface Mount Technology (SMT)
Figure 7-1. Surface Mount Technology Board Types
PLCC Passive
Components SO
Solder Paste
Type I
SO Passive
Components PLCC
PLCC Passive
Component SO
Solder Paste
DIP
Type II
Passive
Components Only*
DIPs
Type III
Passive
Components Only*
NOTE: Intel does not recommend active devices be immersed in solder wave.
A5664-02
The process sequence for Type III SMT is shown in Figure 7-2. Leaded components are inserted,
usually by automatic equipment. The assembly is turned over, and adhesive is applied. Next,
passive SMCs are placed by a "pick-and-place" robot, the adhesive is cured, the assembly is turned
over, and the wave-soldering process is used to solder both leaded and passive SMCs in a single
operation. Finally, the assembly is cleaned (if needed), inspected, repaired if necessary, and tested.
For this type of board, the surface mount components used are chip components and small pin
count gull wing components.
7-2 2000 Packaging Databook
Leaded Surface Mount Technology (SMT)
The process sequence for Type I SMT is shown in Figure 7-3. For a single sided type I, solder
paste is printed onto the board and components are placed The assembly is reflow soldered and
cleaned (if needed). For double-sided Type I, the board is turned over, and the process sequence
just described is repeated.
Type II assemblies go through the process sequence of Type I SMT followed by the sequence for
Type III. In general practice, only passive chip components and low pin count gull wing
components are exposed to solder wave immersion.
Figure 7-2. Typical Process Flow for Underside Attachment (Type III SMT)
Insert Place Surface
Apply
Leaded Invert Board Mount Cure Adhesive
Adhesive
Components Components
Invert Board Wave Solder Clean Test
(if needed)
A5665-02
Figure 7-3. Typical Process Flow for Total Surface Mount (Type I SMT)
Screen Print Place Reflow
Solder Paste Components Dry Paste Solder
Side 1 Single
Side
Only
Screen Print Place Reflow
Invert Board Solder Paste Dry Paste
Components Solder
Side 2
Clean Test
(if needed)
A5666-02
7.3 Fine Pitch Devices
The need for high lead-count packages in semiconductor technology has increased with the advent
of application-specific integrated circuit (ASIC) devices and increased functionality of
microprocessors. As package lead count increases, devices will become larger and larger. To
ensure that the area occupied by packages remains within the limits of manufacturing equipment,
lead pitches have been reduced. This, coupled with the drive toward higher functional density at
the board level for enhanced performance and miniaturization, has fostered the introduction of
many devices in fine-pitch surface mount packages.
2000 Packaging Databook 7-3
Leaded Surface Mount Technology (SMT)
A fine-pitch package can be broadly defined as any package with a lead pitch finer than the
1.27mm pitch of standard surface mount packages like PLCCs and SOPs. Most common lead
pitches are .65mm and .5mm. There are even some now available in 0.4mm pitch. Devices with
these fine pitches and leads on all four sides are called Quad Flat Packs, (QFPs).
The assembly processes most dramatically affected by the fine-pitch package are paste printing and
component placement. Fine pitch printing requires high quality solder paste and unique stencil
aperture designs. Placement of any surface mount package with 25 mils or less of lead pitch must
be made with the assistance of a vision system for accurate alignment.
Placement vision systems typically consist of two cameras. The top camera system scans the
surface of the board and locates fiducial targets that are designed into the artwork of the board. The
placement system then offsets the coordinates in the computer for any variation in true board
location. The bottom camera system, located under the placement head, views the component
leads. Since the leads of fine-pitch components are too fragile to support mechanical centering of
the device, the vision system automatically offsets for variations in the X, Y, and theta dimensions.
This system also inspects for lead integrity problems, such as bent or missing leads.
Other manufacturing issues for assembling fine-pitch components on PC boards include:
1. Printing various amounts of solder paste on the 25-mil and 50-mil lands. One stencil thickness
will usually suffice. But stencils may be stepped down to a thinner amount for fine pitch
aperture areas to keep volumes lower to prevent bridging.
2. Cleaning adequately under and around package leads,
3. Baking of the packages to remove moisture,. Thin QFPs are susceptible to a problem known
as popcorning where moisture in the plastic can literally explode when heating in reflow or
rework and crack the plastic package.
4. Handling of the packages without damaging fragile leads.
These challenges are by no means insurmountable. Many equipment choices have already found
solutions to these issues.
7.4 Surface Mount Design
7.4.1 Design for Manufacturability
Design for manufacturability is gaining more recognition as it becomes clear that cost reduction of
printed wiring assemblies cannot be controlled by manufacturing engineers alone. Design for
manufacturability-which includes considerations of land pattern, placement, soldering, cleaning,
repair, and test-is essentially a yield issue. Thus, companies planning surface mount products face a
challenge in creating manufacturable designs.
Of all the issues in design for manufacturability, land pattern design and interpackage spacing are
the most important. Interpackage spacing controls cost-effectiveness of placement, soldering,
testing, inspection, and repair. A minimum interpackage spacing is required to satisfy all these
manufacturing requirements, and the more spacing that is provided, the better.
With the vast variety of components available today, it would be difficult to list or draw the space
requirements for every component combination. In general, most component spacing ranges from
0.040 in. to 0.060 in. The space is typically measured from pad to pad, lead to lead, or body to
body, whichever is closest. Smaller spacing (0.040 in) is generally used for low or thin profile
parts and small chip components. Taller parts such as PLCCs are usually spaced at 0.060 in. The
placement capability of each individual piece of equipment will partially dictate minimum
7-4 2000 Packaging Databook
Leaded Surface Mount Technology (SMT)
requirements. However, often the ability to rework or repair individual leads, or entire parts, will
have a stronger influence on the minimum spacing. Allowing enough space for rework nozzles or
soldering irons can save considerable cost by allowing repair of a few bad solder joints versus
scrapping the entire board. Thus, each user must set spacing requirements based on the equipment
set used.
The spacing between the pads of conventional and surface mount components may be as large as
0.100 in. so that auto-insertion equipment may used for conventional components. Clear spaces of
at least 0.050 in. should be allowed around all edges of the PC boards if the boards are tested off
the connector, or 0.100 in. if vacuum seal is used for testing, such as bed-of-nails.
Another manufacturing consideration is the alignment of components on the PC board. Similar
types of components should be aligned in the same orientation for ease of component placement,
inspection, and soldering.
Via holes are used to connect SMC lands to conductor layers. They may also be used as test targets
for bed-of-nails probes and/or rework ports. Via holes may be covered with solder mask material if
they are not required for node testing or rework. Such vias are called tented or capped vias.
Via holes may be placed under surface mount components. However, in Type II and Type III SMT
(mix-and-match surface mount), via holes under SMCs should be minimized or tented with solder
mask to prevent trapping of flux under the packages during wave soldering. For effective cleaning,
via holes should only be located beneath SMCs in Type I SMT assemblies (full surface mount) that
are not wave soldered.
7.4.2 Land Pattern Design
The surface mount land patterns, also called footprints or pads, define the sites where components
are to be soldered to the PC board. The design of land patterns is very critical, because it
determines solder joint strength and thus the reliability of solder joints, and also impacts solder
defects, cleanability, testability, and repair or rework. In other words, the very producibility or
success of SMT is dependent upon the land pattern design.
The lack of standardization of surface mount packages has compounded the problem of
standardizing the land pattern. There are a variety of package types offered by the industry, and the
variations in a given package type can be numerous. For example, for the small outline package
(SOP), there are not only two lead types (gull-wing and J-lead), but there are multiple body types
such as narrow wide and thin. In addition, the tolerance on components varies significantly, adding
to the manufacturing problems for SMC users.
In this section, general guidelines are presented for land pattern designs that accommodate
reasonable tolerances in component packages, process, and equipment used in manufacturing.
These guidelines are based on manufacturability and environmental testing of different land pattern
designs for reliability.
To simplify the land pattern design guidelines, surface mount components are divided into four
different categories:
1. 0.050" Pitch J-leaded Devices
2. 0.050" Pitch Gullwing Leaded Devices
3. Sub 0.050" Pitch Gullwing Leaded Devices
4. Chip Components
2000 Packaging Databook 7-5
Leaded Surface Mount Technology (SMT)
Again, with the large variety of SMT part available today, listing every pad size would create a
very long list. So, instead of providing specific pad sizes, the general formulas for the land pattern
designs are given for each of these four categories. There are several different approaches to
dimensioning pads. In addition to the guidelines below, IPC also publishes its own set of
guidelines. Each customer should study several options and decide which is best for their
application.
7.4.2.1 0.050" Pitch J-Leaded Devices
The following dimensions will be needed:
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