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A GREAT ER M EA SU R E O F C O N F I D E N C E This situation calls for increased collabo-
ration between test instrument vendors and
their leading edge reliability customers.
Reliability Test Trends
Today we are seeing the introduction of
new gate dielectrics to address the increas-
ing leakages associated with ultra thin gates.
With the introduction of unconventional di-
electric materials, such as Hafnium oxides,
the degradation mechanism known as Bias
Temperature Instability (BTI) has become
every more problematic. The new materials
generally reduce gate leakage, which leads to
lower quiescent operating currents, however
it also results in threshold and baseband volt-
age instability.
In addition to BTI, the new generation of
New Challenges
gate stacks (high-k-metal gates specifically)
display time dependent dielectric breakdown
(TDDB) characteristics that are distinctly
In WLR Testing
different from conventional SiO2. Earlier
models for hard and soft breakdown were
well understood, but the new materials dis-
play "progressive breakdown". There is cur-
rently a major effort underway to understand
Joey Tun the fine details of the physics behind this
Keithley Instruments, Inc. failure mechanism, and a growing sense of
urgency as the materials move into the en-
gineering phase where process compatibility
Industry Cycles in ability testing is being taxed beyond current is being optimized. These subtleties require
Reliability Testing measurement hardware capabilities. Engi- a new class of instrumentation that not only
Activities to solve semiconductor reliabil- neers and researchers involved with reliabil- possesses better measurement capabilities,
ity problems follow a somewhat predictable ity and quality assurance are encountering a but also substantial processing power to ac-
cycle, just as Moore's law drives the geomet- widening capability gap between the exist- commodate innovative test sequences.
ric shrink. As an example, with the adapta- ing instruments and unmet testing needs. Many degradation mechanisms are the
tion of the VLSI generation of technology,
aluminum interconnects were introduced to
keep the speed of the circuit on track. Re-
liability problems such as electromigration
were quickly identified. Once the problems New Reliability
were identified, the degradation mechanism Materials Problems
had to be modeled through experimental
efforts. With the models in place, process
engineering efforts took place to optimize Reliability
the reliability of the new technology. As the
technology matured, the focus shifted to de- Defect Cycle Reliability
fect reduction. With the introduction of ULSI Reduction Physics
technology, the cycle was again repeated
with new materials, such as strained silicon;
Reliability
copper, and low-k interconnect dielectrics.
Engineering
As the number of material compounds
being introduced continues to increase, reli-
ability related challenges continue to accel-
erate. These new challenges mean that reli- Figure 1. Semiconductor defect-reduction / reliability-improvement cycle.
New Challenges In WLR Testing May 2007 1
result of trapped charge. Consequently, the
magnitude of parameter degradation needs
to be measured relative to trapping and
de-trapping rates of the device. Measure- I-V Sweep
ments must be made very quickly after the
electrical stress condition is removed, AND
Stress Switch Matrix Switch Matrix Stress
the stress condition needs to be restored as Connection, Connection,
quickly as possible after the measurement. SMU Assignment SMU Assignment
Much of the older test equipment falls short
of these needs. Device Relaxation
Additionally, it is clear that various
transistor performance enhancement tech- Figure 2. Multiplexed SMUs may not properly control device relaxation time.
nologies result in complex interaction with
respect to device and circuit reliability. For tures generally is not fast enough. To achieve
Central Controller
instance, strain silicon processes that en- statistically meaningful sample sizes, and
Traditional SMU
hance channel mobility have been shown to meet critical timing requirements, it is often Control Libraries
exacerbate BTI. Furthermore, instability in necessary to dedicate source and measure-
Auxiliary Routines
threshold voltage results in elevated off-cur- ment hardware to each structure. Determine SMU
count, type, etc.
rents and subsequent higher junction temper- Using typical traditional measurement
atures. High junction temperatures acceler- systems for reliability testing raises the fol-
ate dielectric leakage and breakdown. These lowing issues: Choose Test
to Perform
high order interactions are difficult to model Low-cost per channel systems generally Bus Latency
Issues
and make failures more random. Developing rely on switching to reduce the number of
WLR Test Routines Traditional
reliable models requires test instruments that SMUs needed; this means stress-measure (EM_Isothermal,
TDDB, etc.) SMU
can capture a statistically significant number transitions are slow. Multiplexing also makes
of samples with fast test sequences. it impossible to continuously monitor each
Large data sets are particularly important test structure. This also means that truly par- Data Management
and Display
in modeling the interaction between tran- allel testing is impossible.
sistors within a circuit, which is even more Poor timing and latencies often make it
Decision Making
complex than the mechanisms that operate impossible to capture important transient Based on Results
within individual transistors. For example, P- events, and also results in poorly controlled
MOS and N-MOS transistors do not degrade relaxation times.
the same way. N-MOS devices are more The instruments' on-board processors
Figure 3. Software Architecture of a Tradi-
prone to BTI. As a consequence, a circuit have limited programmability or decision tional Test System
with complementary transistors transporting making capacity. This also means that po-
a clock signal may cause a change in duty tentially valuable processes, such as data reports the resistance value over the GPIB
cycle or signal skewing. Additionally, com- thinning, are impossible. bus to the central controller. The controller
plex interactions can occur between differ- Many traditional systems have a buffer calculates the temperature, and then decides
ent degradation mechanisms. For example, size of about 5000; this is too small for most which current to source next. The next in-
soft dielectric breakdown usually results in reliability testing needs, such as capturing an struction with a new current source value is
increased leakage. Although this does not entire high-K-metal gate failure. sent to the SMU, again over the GPIB bus.
render the transistor useless, it can possibly The software architecture of a traditional This process is repeated ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo