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Number 2896
Application Note CV Characterization of MOS
Series Capacitors Using the Model 4200SCS
Semiconductor Characterization System
Introduction C
Q
V
Maintaining the quality and reliability of gate oxides of MOS
structures is a critical task in a semiconductor fab. Capacitance- One general practical way to implement this is to apply a
voltage (C-V) measurements are commonly used in studying small AC voltage signal (millivolt range) to the device under test,
gate-oxide quality in detail. These measurements are made on a and then measure the resulting current. Integrate the current
two-terminal device called a MOS capacitor (MOS cap), which is over time to derive Q and then calculate C from Q and V.
basically a MOSFET without a source and drain. C-V test results
offer a wealth of device and process information, including bulk C-V measurements in a semiconductor device are made using
and interface charges. Many MOSdevice parameters, such as two simultaneous voltage sources: an applied AC voltage signal
oxide thickness, flatband voltage, threshold voltage, etc., can also (dVac) and a DC voltage (Vdc) that is swept in time, as illustrated
be extracted from the C-V data. in Figure 1.
Using a tool such as the Keithley Model 4200-SCS equipped
Vdc
with the 4200-CVU Integrated C-V Option for making C-V meas-
urements on MOS capacitors can simplify testing and analysis.
The Model 4200-SCS is an integrated measurement system that
can include instruments for both I-V and C-V measurements, as
well as software, graphics, and mathematical analysis capabilities.
Voltage
The software incorporates C-V tests, which include a variety of
dVac
complex formulas for extracting common C-V parameters.
This application note discusses how to use a Keithley Model
4200-SCS Semiconductor Characterization System equipped
with the Model 4200-CVU Integrated C-V Option to make C-V
measurements on MOS capacitors. It also addresses the basic Time
principles of MOS caps, performing C-V measurements on MOS
capacitors, extracting common C-V parameters, and measure- Figure 1. AC and DC voltage of CV Sweep Measurement
ment techniques. The Keithley Test Environment Interactive
(KTEI) software that controls the Model 4200-SCS incorporates The magnitude and frequency of the AC voltage are fixed; the
a list of a dozen test projects specific to C-V testing. Each project magnitude of the DC voltage is swept in time. The purpose of
is paired with the formulae necessary to extract common C-V the DC voltage bias is to allow sampling of the material at differ-
parameters, such as oxide capacitance, oxide thickness, doping
ent depths in the device. The AC voltage bias provides the small-
density, depletion depth, Debye length, flatband capacitance, flat-
signal bias so the capacitance measurement can be performed at
band voltage, bulk potential, threshold voltage, metal-
a given depth in the device.
semiconductor work function difference, and effective oxide
charge. This completeness is in sharp contrast to other commer-
cially available C-V solutions, which typically require the user to Basic Principles of MOS Capacitors
research and enter the correct formula for each parameter manu-
ally. Figure 2 illustrates the construction of a MOS capacitor.
Essentially, the MOS capacitor is just an oxide placed between
a semiconductor and a metal gate. The semiconductor and the
Overview Of C-V Measurement Technique
metal gate are the two plates of the capacitor. The oxide func-
By definition, capacitance is the change in charge (Q) in a device tions as the dielectric. The area of the metal gate defines the area
that occurs when it also has a change in voltage (V): of the capacitor.
Metal Gate For a p-type MOS capacitor, the oxide capacitance is mea-
sured in the strong accumulation region. This is where the volt-
age is negative enough that the capacitance is essentially constant
Metal
and the C-V curve is almost flat. This is where the oxide thick-
Oxide ness can also be extracted from the oxide capacitance. However,
Semiconductor for a very thin oxide, the slope of the C-V curve doesn't flatten in
accumulation and the measured oxide capacitance differs from
the actual oxide capacitance.
Back Contact Depletion Region
Figure 2. MOS capacitor When a positive voltage is applied between the gate and the
semiconductor, the majority carriers are replaced from the
The most important property of the MOS capacitor is that its semiconductor-oxide interface. This state of the semiconductor
capacitance changes with an applied DC voltage. As a result, the is called depletion because the surface of the semiconductor is
modes of operation of the MOS capacitor change as a function depleted of majority carriers. This area of the semiconductor
of the applied voltage. Figure 3 illustrates a high frequency C-V acts as a dielectric because it can no longer contain or conduct
curve for a p-type semiconductor substrate. As a DC sweep volt- charge. In effect, it becomes an insulator.
age is applied to the gate, it causes the device to pass through
The total measured capacitance now becomes the oxide
accumulation, depletion, and inversion regions.
capacitance and the depletion layer capacitance in series, and as
a result, the measured capacitance decreases. This decrease in
capacitance is illustrated in Figure 3 in the depletion region. As a
gate voltage increases, the depletion region moves away from the
gate, increasing the effective thickness of the dielectric between
the gate and the substrate, thereby reducing the capacitance.
Inversion Region
As the gate voltage of a p-type MOS-C increases beyond the
threshold voltage, dynamic carrier generation and recombination
move toward net carrier generation. The positive gate voltage
generates electron-hole pairs and attracts electrons (the minor-
ity carriers) toward the gate. Again, because the oxide is a good
insulator, these minority carriers accumulate at the substrate-to-
oxide/well-to-oxide interface. The accumulated minority-carrier
layer is called the inversion layer because the carrier polarity is
inverted. Above a certain positive gate voltage, most available
minority carriers are in the inversion layer, and further gate-
voltage increases do not further deplete the semiconductor. That
is, the depletion region reaches a maximum depth.
Figure 3. CV curve of a ptype MOS capacitor measured with the 4200CVU Once the depletion region reaches a maximum depth, the
capacitance that is measured by the high frequency capacitance
The three modes of operation, accumulation, depletion and meter is the oxide capacitance in series with the maximum deple-
inversion, will now be discussed for the case of a p-type semicon- tion capacitance. This capacitance is often referred to as mini-
ductor, then briefly discussed for an n-type semiconductor at the mum capacitance. The C-V curve slope is almost flat.
end of this section.
NOTE: The measured inversion-region capacitance at the
Accumulation Region maximum depletion depth depends on the measurement
frequency. Therefore, C-V curves measured at different
With no voltage applied, a p-type semiconductor has holes, or frequencies may have different appearances. Generally, such
majority carriers, in the valence band. When a negative voltage differences are more significant at lower frequencies and less
is applied between the metal gate and the semiconductor, more significant at higher frequencies.
holes will appear in the valence band at the oxide-semiconduc-
tor interface. This is because the negative charge of the metal n-type Substrate
causes an equal net positive charge to accumulate at the inter- The C-V curve for an n-type MOS capacitor is analogous to a
face between the semiconductor and the oxide. This state of the p-type curve, except that (1) the majority carriers are electrons
p-type semiconductor is called accumulation. instead of holes; (2) the n-type C-V curve is essentially a mirror
image of the p-type curve; (3) accumulation occurs by applying
a positive voltage to the gate; and (4) the inversion region occurs
at negative voltage.
Performing C-V Measurements
with the 4200-CVU
To simplify testing, a project has been created for the 4200-SCS
that makes C-V measurements on a MOS capacitor and extracts
common measurement parameters such as oxide thickness, flat-
band voltage, threshold voltage, etc. The project (CVU_MOScap)
is included with all 4200-SCS systems running KTEI Version
7.0 or later. Figure 4 is a screen shot of the project, which has Figure 5. Formulator window with parameters derived
three tests, called ITMs (Interactive Test Modules), which gen-
erate a C-V sweep (CVSweep_MOScap), a 1/C2 vs. Gate Voltage C-2vsV_MOScap Test Module
curve (C-2vsV_MOScap), and a doping profile (DopingProfile_ This test performs a C-V sweep and displays the capacitance
MosC). Figure 4 also illustrates a C-V sweep generated with the (1/C2) as a function of the gate voltage (VG). This sweep can
(CVSweep_MOScap) test module. All of the extracted C-V param- yield important information about doping profile because the
substrate doping concentration (NSUB) is inversely related to the
eters in these test modules are defined in the next section of this
reciprocal of the slope of the 1/C2 vs. VG curve. A positive slope
application note. indicates acceptors and a negative slope indicates donors. The
substrate doping concentration is extracted from the slope of
the 1/C2 curve and is displayed on the graph. Figure 6 shows the
results of executing this test module.
Figure 4. CV Sweep created with MOScap project for the 4200
CVSweep_MOScap Test Module
Figure 6. 1/C 2 vs. gate voltage plot generated with 4200CVU
This test performs a capacitance measurement at each step of a
user-configured linear voltage sweep. A C-V graph is generated DopingProfile Test Module
from the acquired data, and several device parameters are cal- This test performs a doping profile, which is a plot of the doping
culated using the Formulator, which is a tool in the 4200-SCS's concentration vs. depletion depth. The difference in capacitance
software that provides a variety of computational functions, com- at each step of the gate voltage is proportional to the doping
concentration. The depletion depth is computed from the high
mon mathematical operators, and common constants. Figure 5
frequency capacitance and oxide capacitance at each measured
shows the window of the Formulator. These derived parameters value of the gate voltage. The results are plotted on the graph as
are listed in the Sheet Tab of the Test Module. shown in Figure 7.
Figure 7. Doping profile extracted from CV data taken with 4200CVU
Connections to the 4200-CVU
Figure 9. CVU compensation window
To make a C-V measurement, a MOS cap is connected to the
4200-CVU as shown in Figure 8. In the ITM, both the 4200-CVU
To perform the corrections, Open the Tools Menu and select
ammeter and the DC voltage appear at the HCUR/HPOT ter-
CVU Connection Compensation. For an Open correction, click
minals. See the next section, "Measurement Optimization," for
on Measure Open. Probes must be up during the correction.
further information on connecting the CVU to the device on
Open is typically used for high impedance measurements (<10pF
a wafer.
or >1MW).
HICUR For a Short correction, click on Measure Short. Short the
HIPOT probe to the chuck. A short correction is generally performed for
low impedance measurements (>10nF or <10W).
Gate Wafer
After the corrections are performed, they must be enabled
4200-CVU in the project. To enable corrections, click the Compensation
button at the bottom of the Forcing Functions/Measure Options
Bulk Window. In the CVU Compensation dialog box (Figure 9), click
LPOT only the corrections to be applied.
LCUR Measuring at Equilibrium Conditions
Figure 8. Basic configuration to test MOS capacitor with 4200CVU A MOS capacitor takes time to become fully charged after a
voltage step is applied. C-V measurement data should only be
recorded after the device is fully charged. This condition is called
Measurement Optimization
the equilibrium condition. Therefore, to allow the MOS capaci-
Successful measurements require compensating for stray capaci- tor to reach equilibrium: (1) allow a sufficient Hold Time in the
tance, measuring at equilibrium conditions, and compensating Timing Menu to enable the MOS capacitor to charge up while
for series resistance. applying a "PreSoak" voltage, and (2) allow a sufficient Sweep
Delay Time in the Timing Menu before recording the capacitance
Offset Correction for Stray Capacitance
after each voltage step of a voltage sweep. The appropriate Hold
C-V measurements on a MOS capacitor are typically performed and Delay Times are determined experimentally by generating
on a wafer using a prober. The 4200-CVU is designed to be con- capacitance vs. time plots and observing the time for the capaci-
nected to the prober via interconnect cables and adaptors and tance to settle.
may possibly be routed through a switch matrix. This cabling and
Although C-V curves swept from different directions may look
switch matrix will add stray capacitance to the measurements.
different, allowing adequate Hold and Delay Times minimizes
To correct for stray capacitance, the KTEI software environ- such differences. One way to determine sufficient Hold and
ment has a built-in tool for offset correction, which is a two-part Delay Times is to generate a series of C-V curves in both direc-
process: the corrections for OPEN and/or SHORT are performed tions. Change the Hold and Delay Times for each pair of inver-
first, and then they can be enabled within an ITM.
sion accumulation and accumulation inversion curves until Bias
the curves look essentially the same for both sweep directions. Bias Hold Time
Start Voltage
Voltage
Hold and Delay Times When Sweeping from Inversion
Accumulation. When the C-V sweep starts in the inversion Delay
region and the starting voltage is initially applied, a MOS capaci- Time
tor is driven into deep depletion. Thereafter, if the starting volt- Light
0V
age is maintained, the initial high frequency C-V curve climbs Pulse
toward and ultimately stabilizes to the minimum capacitance at
Figure 11. Preferred CV measurement Sequence
equilibrium. However, if the initial Hold Time is too short, the
MOS capacitor cannot adequately recover from deep depletion, The device is first biased at the "PreSoak" voltage for the
and the measured capacitance will be smaller than the minimum Hold Time that is adjusted in the Timing Menu. The bias or
capacitance at equilibrium. Set the "PreSoak" voltage to the first "PreSoak" voltage should be the same as the sweep start voltage
voltage in the voltage sweep and allow a sufficient Hold Time for to avoid a sudden voltage change when the sweep starts. During
the MOS capacitor to reach equilibrium. biasing, if necessary, a short light pulse can be applied to the
sample to help generate minority carriers. However, before the
However, once the MOS capacitor has reached equilibrium sweep starts, all lights should be turned off. All measurements
after applying the "PreSoak" voltage, an inversion accumula- should be performed in total darkness because the semiconduc-
tion C-V sweep may be performed with small delay times. This is tor material may be light sensitive. During the sweep, the Delay
possible because minority carriers recombine relatively quickly as Time should be chosen to create the optimal balance between
the gate voltage is reduced. Nonetheless, if the Delay Time is too measurement speed and measurement integrity, which requires
short, non-equilibrium occurs, and the capacitance in the inver- adequate equilibration time.
sion region is slightly higher than the equilibrium value. This is Compensating for series resistance
illustrated by the upper dotted line in Figure 10.
After generating a C-V curve, it may be necessary to compen-
sate for series resistance in measurements. The series resistance
(RSERIES) can be attributed to either the substrate (well) or the
backside of the wafer. For wafers typically produced in fabs, the
substrate bulk resistance is fairly small (<10W) and has negligible
C impact on C-V measurements. However, if the backside of the
Swept too fast wafer is used as an electrical contact, the series resistance due
to oxides can significantly distort a measured C-V curve. Without
series compensation, the measured capacitance can be lower
Equilibrium than the expected capacitance, and C-V curves can be distorted.
sweep
Tests for this project compensate for series resistance using the
VGS
simplified three-element model shown in Figure 12. In this
Figure 10. Effects of performing a CV sweep too quickly model, COX is the oxide capacitance and C A is the capacitance
of the accumulation layer. The series resistance is represented
Hold and Delay Times When Sweeping from Accumulation by RSERIES.
Inversion. When the C-V sweep starts in the accumulation
region, the effects of Hold and Delay Times in the accumulation CA
and depletion regions are fairly subtle. However, in the inversion COX
region, if the Delay Time is too small (i.e., the sweep time is too COX Simplifies to
fast), there's not enough time for the MOS capacitor to generate
minority carriers to form an inversion layer. On the high frequen- RSERIES RSERIES
cy C-V curve, the MOS capacitor never achieves equilibrium and
eventually becomes deeply depleted. The measured capacitance
values fall well below the equilibrium minimum value. The lower Equivalent 3-element Simplified model used
dotted line in Figure 10 illustrates this phenomenon. model of MOS capacitor to determine RSERIES
in strong accumulation
Using the preferred sequence. Generating a C-V curve by
Figure 12. Simplified Model to determine series resistance
sweeping from inversion to accumulation is faster and more con-
trollable than sweeping from accumulation to inversion. Figure The corrected capacitance (C ADJ) and corrected conductance
11 illustrates a preferred measurement sequence. (GADJ) are calculated from the following formulas [1]:
(G2 + (2fC)2)C
CADJ = ____________________
aR2 + (2fC)2
(G2 + (2fC)2)aR
GADJ = ____________________
aR2 + (2fC)2
where:
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