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A GREAT ER M EA SU R E O F C O N F I D E N C E structures. Improvements from 40% to 50%
are possible with structure layouts designed
to increase the potential for parallel test.
In traditional (i.e., sequential) parametric
test programs, each DUT is connected to
the measurement instruments one after the
other. During the period in which the DUT
is connected, forcing signals are applied to
it, and then electrical measurements record
its response. Once a single test or group of
Getting Started
tests for a DUT is complete, the connec-
tions are cleared to allow connection to the
next DUT. These connect and disconnect
in Parallel Test--
times represent some proportion of the
overall throughput budget because the relay
switching and settling times for high isola-
Modification tion mechanical devices are fixed.
In addition to the relay connect (Conpin)
of Existing
and disconnect (Reinitialize) overheads just
described, there is a delay (Delay) over-
head, the length of which can vary widely,
Scribe Line TEGs
depending on the DUT type and the meas-
urement conditions. When addressed sequen-
tially, these connect, disconnect, and delay
overheads can reduce the overall throughput
gains that faster instruments could otherwise
Randall G. Lee deliver. Fortunately, by connecting multiple
Keithley Instruments, Inc. DUTs to different measurement resources
simultaneously (for different types of tests),
Statistical Process Control (SPC). In order to it's possible to reduce significantly the impact
Initial Strategy minimize pad usage, test structure designers of relay connect and disconnect times on
Wafer-level parallel parametric testing frequently connect device terminals together overall throughput (Figure 1).
involves concurrent execution of multiple or use other techniques to minimize that Connecting various measurement instru-
tests on multiple scribe line test structures. amount of space these structures require. ments to multiple DUTs simultaneously and
This has the potential for huge improvements From the perspective of parallel testing, this obtaining reliable data from them is vastly
in throughput with existing test hardware. lack of device isolation can create problems. simplified if instruments of the same type
For many fabs or test cells with mature Despite such limitations, experienced test (e.g., source-measure units) have identical
processes, the most attractive approach sequence developers have been able to pro- capabilities. In the case of the DC instrument
to parallel test is to change only the test duce parametric test throughput improve- example shown in Figure 2, each path has
sequencing on existing TEGs. This approach ments (including prober overhead) ranging uniform signal amplification (via preamp)
is usually the best way to achieve significant from 5% to 40% with existing scribe line test at the pin. There also are uniform switching
throughput improvements with a relatively
limited investment in analysis, new software,
Conpin ForceV Delay MeasI Devint
and test sequence modifications. Typically, Conpin ForceV Delay MeasI Devint
the process starts with analysis of the TEG Conpin ForceV Delay MeasI Devint
and test sequence to find a way to minimize Conpin ForceV Delay MeasI Devint
Conpin ForceV Delay MeasI
switching time between test pads. Generally,
Conpin ForceV Delay MeasI
this involves the reordering or regrouping of Devint
existing tests on heterogeneous structures. Conpin ForceV Delay MeasI
Conpin ForceV Delay MeasI
Analysis of Existing Structures tp
4 DUT Parallel is approximately
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