Service Manuals, User Guides, Schematic Diagrams or docs for : Keithley KPCI KPCI-3140
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>> Download KPCI-3140 documenatation <<Text preview - extract from the document KPCI-3140 8-Channel, 40MHz Counter/Timer
with Digital I/O Board
Functional Description
The KPCI-3140's integration of sophisticated timing, frequency and event
counting, and digital I/O makes it a highly versatile, cost-effective alterna-
tive to using separate counter, timer, and digital I/O cards. This board con-
tains eight 16-bit counter/timers, four 24-bit interval timers, and 32 digital
I/O lines that can be programmed for input or output. Keithley's extensive
software suite of 32-bit DriverLINX drivers is included. DriverLINX pro-
vides both an ActiveX and DLL interface for programming languages and
Great mix of counters, timers, and digital I/O
Great mix of counters, timers, and digital I/O
test panels for easy performance verification.
Each of the eight counter/timers accepts both a clock input and a gate input
signal, and outputs a clock output signal. Each counter can use a time base
generated from an internal clock or from an external clock. Each counter
can interrupt the CPU when it reaches a count of 0. The internal clock uses
a 25ns time base with output frequencies ranging from 610Hz to 40MHz. An
external clock is useful for pacing counter/timer operations at rates not avail-
able with the internal clock or for pacing at uneven intervals.
The clock output signal of one counter/timer can be routed internally to the
clock input signal of the next counter/timer to cascade the two counter/timers.
This creates a 32-bit counter/timer. To cascade more than two counter/timers,
connect the counter/timers externally using the screw terminal panel accessory.
There are two methods for controlling the gate of each counter: by soft-
ware or by an external gate signal. Use the external gate signal to trigger a
one-shot output or to enable event counting, frequency measurement, or
rate generation when the gate signal is active.
The KPCI-3140 allows the internal clock's output signal to be a pulsed out-
put with either high-to-low transition or low-to-high transitions. The duty cycle (width) of the pulse
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