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appl icat i ons gui de
C-V Testing for Components and
Semiconductor Devices
a g r e a t e r m e a s u r e o f c o n f i d e n c e
C-V Testing for Components and Semiconductor Devices
Capacitance-Voltage (C-V) testing is widely used to determine a variety of semiconductor parameters,
such as doping concentration and profiles, carrier lifetime, oxide thickness, interface trap density, and
more. This C-V testing applications e-guide features a concentration of application notes on C-V testing
methods and techniques using Keithley's Model 4200-SCS Parameter Analyzer. The Model 4200-SCS
provides three C-V methods: Multi-frequency C-V (1kHz - 10MHz,), Very Low Frequency C-V (10mHz -
10Hz,) and Quasi-static C-V measurements.
Contents
CV Characterization of MOS Capacitors Using
the Model 4200SCS Parameter Analyzer . . . . . . . . . 3
Performing Very Low Frequency Capacitance
Voltage Measurements on High Impedance
Devices Using the Model 4200SCS Parameter
Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Using the Ramp Rate Method for Making
Quasistatic CV Measurements with the Model
4200SCS Parameter Analyzer . . . . . . . . . . . . . . . . . 23
Using the Model 4200CVUPWR CV Power
Package to Make High Voltage and High Current
CV Measurements with the Model 4200SCS
Parameter Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Measuring Inductance Using the 4200CVU
CapacitanceVoltage Unit . . . . . . . . . . . . . . . . . . . . . . 35
Electrical Characterization of Photovoltaic
Materials and Solar Cells with the Model 4200
SCS Parameter Analyzer . . . . . . . . . . . . . . . . . . . . . . . 37
Making Proper Electrical Connections to Ensure
Semiconductor Device Measurement Integrity . . . . 53
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C-V Characterization of MOS
Capacitors Using the Model 4200-SCS
Parameter Analyzer
Introduction C
Q
V
Maintaining the quality and reliability of gate oxides of MOS
structures is a critical task in a semiconductor fab. Capacitance- One general practical way to implement this is to apply a
small AC voltage signal (millivolt range) to the device under test,
voltage (C-V) measurements are commonly used in studying
and then measure the resulting current. Integrate the current
gate-oxide quality in detail. These measurements are made on a
over time to derive Q and then calculate C from Q and V.
two-terminal device called a MOS capacitor (MOS cap), which is
basically a MOSFET without a source and drain. C-V test results C-V measurements in a semiconductor device are made using
offer a wealth of device and process information, including bulk two simultaneous voltage sources: an applied AC voltage signal
and interface charges. Many MOSdevice parameters, such as (dVac) and a DC voltage (Vdc) that is swept in time, as illustrated
in Figure 1.
oxide thickness, flatband voltage, threshold voltage, etc., can also
be extracted from the C-V data. Vdc
Using a tool such as the Keithley Model 4200-SCS equipped
with the 4200-CVU Integrated C-V Option for making C-V
measurements on MOS capacitors can simplify testing and
analysis. The Model 4200-SCS is an integrated measurement
Voltage
system that can include instruments for both I-V and C-V
dVac
measurements, as well as software, graphics, and mathematical
analysis capabilities. The software incorporates C-V tests, which
include a variety of complex formulas for extracting common C-V
parameters.
This application note discusses how to use a Keithley Model
Time
4200-SCS Parameter Analyzer equipped with the Model 4200-
Figure 1. AC and DC voltage of C-V Sweep Measurement
CVU Integrated C-V Option to make C-V measurements on MOS
capacitors. It also addresses the basic principles of MOS caps, The magnitude and frequency of the AC voltage are fixed;
performing C-V measurements on MOS capacitors, extracting the magnitude of the DC voltage is swept in time. The purpose
common C-V parameters, and measurement techniques. The of the DC voltage bias is to allow sampling of the material at
Keithley Test Environment Interactive (KTEI) software that different depths in the device. The AC voltage bias provides
controls the Model 4200-SCS incorporates a list of a dozen test the small-signal bias so the capacitance measurement can be
projects specific to C-V testing. Each project is paired with the performed at a given depth in the device.
formulae necessary to extract common C-V parameters, such as
oxide capacitance, oxide thickness, doping density, depletion Basic Principles of MOS Capacitors
depth, Debye length, flatband capacitance, flatband voltage, bulk Figure 2 illustrates the construction of a MOS capacitor.
potential, threshold voltage, metal-semiconductor work function Essentially, the MOS capacitor is just an oxide placed between
difference, and effective oxide charge. This completeness is in a semiconductor and a metal gate. The semiconductor and
sharp contrast to other commercially available C-V solutions, the metal gate are the two plates of the capacitor. The oxide
which typically require the user to research and enter the correct functions as the dielectric. The area of the metal gate defines the
formula for each parameter manually. area of the capacitor.
The most important property of the MOS capacitor is that its
Overview of CV Measurement Technique capacitance changes with an applied DC voltage. As a result, the
modes of operation of the MOS capacitor change as a function
By definition, capacitance is the change in charge (Q) in a device of the applied voltage. Figure 3 illustrates a high frequency
that occurs when it also has a change in voltage (V): C-V curve for a p-type semiconductor substrate. As a DC sweep
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However, for a very thin oxide, the slope of the C-V curve doesn't
Metal Gate
flatten in accumulation and the measured oxide capacitance
differs from the actual oxide capacitance.
Metal
Oxide Depletion Region
When a positive voltage is applied between the gate and the
Semiconductor
semiconductor, the majority carriers are replaced from the
semiconductor-oxide interface. This state of the semiconductor
is called depletion because the surface of the semiconductor is
Back Contact
depleted of majority carriers. This area of the semiconductor
Figure 2. MOS capacitor
acts as a dielectric because it can no longer contain or conduct
charge. In effect, it becomes an insulator.
The total measured capacitance now becomes the oxide
capacitance and the depletion layer capacitance in series, and as
a result, the measured capacitance decreases. This decrease in
capacitance is illustrated in Figure 3 in the depletion region. As a
gate voltage increases, the depletion region moves away from the
gate, increasing the effective thickness of the dielectric between
the gate and the substrate, thereby reducing the capacitance.
Inversion Region
As the gate voltage of a p-type MOS-C increases beyond the
threshold voltage, dynamic carrier generation and recombination
move toward net carrier generation. The positive gate voltage
generates electron-hole pairs and attracts electrons (the minority
carriers) toward the gate. Again, because the oxide is a good
insulator, these minority carriers accumulate at the substrate-to-
oxide/well-to-oxide interface. The accumulated minority-carrier
layer is called the inversion layer because the carrier polarity is
inverted. Above a certain positive gate voltage, most available
Figure 3. C-V curve of a p-type MOS capacitor measured with the 4200-CVU minority carriers are in the inversion layer, and further gate-
voltage increases do not further deplete the semiconductor. That
voltage is applied to the gate, it causes the device to pass through
is, the depletion region reaches a maximum depth.
accumulation, depletion, and inversion regions.
Once the depletion region reaches a maximum depth, the
The three modes of operation, accumulation, depletion
capacitance that is measured by the high frequency capacitance
and inversion, will now be discussed for the case of a
meter is the oxide capacitance in series with the maximum
p-type semiconductor, then briefly discussed for an n-type
semiconductor at the end of this section. depletion capacitance. This capacitance is often referred to as
minimum capacitance. The C-V curve slope is almost flat.
Accumulation Region
NOTE: The measured inversion-region capacitance at the
With no voltage applied, a p-type semiconductor has holes, or maximum depletion depth depends on the measurement
majority carriers, in the valence band. When a negative voltage frequency. Therefore, C-V curves measured at different
is applied between the metal gate and the semiconductor, more frequencies may have different appearances. Generally, such
holes will appear in the valence band at the oxide-semiconductor differences are more significant at lower frequencies and less
interface. This is because the negative charge of the metal causes significant at higher frequencies.
an equal net positive charge to accumulate at the interface
between the semiconductor and the oxide. This state of the ntype Substrate
p-type semiconductor is called accumulation.
The C-V curve for an n-type MOS capacitor is analogous to a
For a p-type MOS capacitor, the oxide capacitance is p-type curve, except that (1) the majority carriers are electrons
measured in the strong accumulation region. This is where the instead of holes; (2) the n-type C-V curve is essentially a mirror
voltage is negative enough that the capacitance is essentially image of the p-type curve; (3) accumulation occurs by applying
constant and the C-V curve is almost flat. This is where the oxide a positive voltage to the gate; and (4) the inversion region occurs
thickness can also be extracted from the oxide capacitance. at negative voltage.
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Performing CV Measurements software that provides a variety of computational functions,
with the 4200CVU common mathematical operators, and common constants.
Figure 5 shows the window of the Formulator. These derived
To simplify testing, a project has been created for the 4200-
parameters are listed in the Sheet Tab of the Test Module.
SCS that makes C-V measurements on a MOS capacitor and
extracts common measurement parameters such as oxide C-2vsV_MOScap Test Module
thickness, flatband voltage, threshold voltage, etc. The project This test performs a C-V sweep and displays the capacitance
(CVU_MOScap) is included with all 4200-SCS systems running (1/C2) as a function of the gate voltage (VG). This sweep can
KTEI Version 7.0 or later. Figure 4 is a screen shot of the project, yield important information about doping profile because the
which has three tests, called ITMs (Interactive Test Modules), substrate doping concentration (NSUB) is inversely related to the
which generate a C-V sweep (CVSweep_MOScap), a 1/C2 vs. reciprocal of the slope of the 1/C2 vs. VG curve. A positive slope
Gate Voltage curve (C-2vsV_MOScap), and a doping profile indicates acceptors and a negative slope indicates donors. The
(DopingProfile_MosC). Figure 4 also illustrates a C-V sweep substrate doping concentration is extracted from the slope of
generated with the (CVSweep_MOScap) test module. All of the the 1/C2 curve and is displayed on the graph. Figure 6 shows the
extracted C-V parameters in these test modules are defined in results of executing this test module.
the next section of this application note.
DopingProfile Test Module
CVSweep_MOScap Test Module This test performs a doping profile, which is a plot of the doping
This test performs a capacitance measurement at each step of a concentration vs. depletion depth. The difference in capacitance
user-configured linear voltage sweep. A C-V graph is generated
from the acquired data, and several device parameters are
calculated using the Formulator, which is a tool in the 4200-SCS's
Figure 6. 1/C 2 vs. gate voltage plot generated with 4200-CVU
Figure 4. C-V Sweep created with MOScap project for the 4200
Figure 5. Formulator window with parameters derived Figure 7. Doping profile extracted from C-V data taken with 4200-CVU
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at each step of the gate voltage is proportional to the doping
concentration. The depletion depth is computed from the high
frequency capacitance and oxide capacitance at each measured
value of the gate voltage. The results are plotted on the graph as
shown in Figure 7.
Connections to the 4200CVU
To make a C-V measurement, a MOS cap is connected to the
4200-CVU as shown in Figure 8. In the ITM, both the 4200-
CVU ammeter and the DC voltage appear at the HCUR/HPOT
terminals. See the next section, "Measurement Optimization,"
for further information on connecting the CVU to the device
on a wafer.
HICUR
HIPOT
Gate Wafer
4200-CVU Figure 9. CVU compensation window
Bulk button at the bottom of the Forcing Functions/Measure Options
Window. In the CVU Compensation dialog box (Figure 9), click
LPOT
only the corrections to be applied.
LCUR
Measuring at Equilibrium Conditions
Figure 8. Basic configuration to test MOS capacitor with 4200-CVU A MOS capacitor takes time to become fully charged after a
voltage step is applied. C-V measurement data should only be
Measurement Optimization recorded after the device is fully charged. This condition is called
the equilibrium condition. Therefore, to allow the MOS capacitor
Successful measurements require compensating for stray to reach equilibrium: (1) allow a sufficient Hold Time in the
capacitance, measuring at equilibrium conditions, and Timing Menu to enable the MOS capacitor to charge up while
compensating for series resistance. applying a "PreSoak" voltage, and (2) allow a sufficient Sweep
Offset Correction for Stray Capacitance Delay Time in the Timing Menu before recording the capacitance
C-V measurements on a MOS capacitor are typically performed after each voltage step of a voltage sweep. The appropriate Hold
on a wafer using a prober. The 4200-CVU is designed to be and Delay Times are determined experimentally by generating
connected to the prober via interconnect cables and adaptors capacitance vs. time plots and observing the time for the
and may possibly be routed through a switch matrix. This capacitance to settle.
cabling and switch matrix will add stray capacitance to the Although C-V curves swept from different directions may look
measurements. different, allowing adequate Hold and Delay Times minimizes
To correct for stray capacitance, the KTEI software such differences. One way to determine sufficient Hold and Delay
environment has a built-in tool for offset correction, which is a Times is to generate a series of C-V curves in both directions.
two-part process: the corrections for OPEN and/or SHORT are Change the Hold and Delay Times for each pair of inversion
performed first, and then they can be enabled within an ITM. accumulation and accumulation inversion curves until the
curves look essentially the same for both sweep directions.
To perform the corrections, Open the Tools Menu and select
CVU Connection Compensation. For an Open correction, click Hold and Delay Times When Sweeping from Inversion
on Measure Open. Probes must be up during the correction. Accumulation. When the C-V sweep starts in the inversion
Open is typically used for high impedance measurements region and the starting voltage is initially applied, a MOS
(<10pF or >1MW). capacitor is driven into deep depletion. Thereafter, if the starting
voltage is maintained, the initial high frequency C-V curve climbs
For a Short correction, click on Measure Short. Short the toward and ultimately stabilizes to the minimum capacitance at
probe to the chuck. A short correction is generally performed for equilibrium. However, if the initial Hold Time is too short, the
low impedance measurements (>10nF or <10W). MOS capacitor cannot adequately recover from deep depletion,
After the corrections are performed, they must be enabled and the measured capacitance will be smaller than the minimum
in the project. To enable corrections, click the Compensation capacitance at equilibrium. Set the "PreSoak" voltage to the first
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voltage in the voltage sweep and allow a sufficient Hold Time for The device is first biased at the "PreSoak" voltage for the Hold
the MOS capacitor to reach equilibrium. Time that is adjusted in the Timing Menu. The bias or "PreSoak"
voltage should be the same as the sweep start voltage to avoid a
However, once the MOS capacitor has reached equilibrium
sudden voltage change when the sweep starts. During biasing,
after applying the "PreSoak" voltage, an inversion if necessary, a short light pulse can be applied to the sample
accumulation C-V sweep may be performed with small delay to help generate minority carriers. However, before the sweep
times. This is possible because minority carriers recombine starts, all lights should be turned off. All measurements should
relatively quickly as the gate voltage is reduced. Nonetheless, if be performed in total darkness because the semiconductor
the Delay Time is too short, non-equilibrium occurs, and the material may be light sensitive. During the sweep, the Delay
capacitance in the inversion region is slightly higher than the Time should be chosen to create the optimal balance between
equilibrium value. This is illustrated by the upper dotted line in measurement speed and measurement integrity, which requires
Figure 10. adequate equilibration time.
Compensating for series resistance
After generating a C-V curve, it may be necessary to compensate
for series resistance in measurements. The series resistance
(RSERIES) can be attributed to either the substrate (well) or the
backside of the wafer. For wafers typically produced in fabs, the
C substrate bulk resistance is fairly small (<10W) and has negligible
Swept too fast impact on C-V measurements. However, if the backside of the
wafer is used as an electrical contact, the series resistance due
Equilibrium to oxides can significantly distort a measured C-V curve. Without
sweep series compensation, the measured capacitance can be lower
VGS than the expected capacitance, and C-V curves can be distorted.
Tests for this project compensate for series resistance using the
Figure 10. Effects of performing a C-V sweep too quickly
simplified three-element model shown in Figure 12. In this
model, COX is the oxide capacitance and C A is the capacitance
Hold and Delay Times When Sweeping from Accumulation of the accumulation layer. The series resistance is represented
Inversion. When the C-V sweep starts in the accumulation by RSERIES.
region, the effects of Hold and Delay Times in the accumulation
and depletion regions are fairly subtle. However, in the inversion
region, if the Delay Time is too small (i.e., the sweep time is CA
too fast), there's not enough time for the MOS capacitor to COX
COX Simplifies to
generate minority carriers to form an inversion layer. On the
high frequency C-V curve, the MOS capacitor never achieves
equilibrium and eventually becomes deeply depleted. The RSERIES RSERIES
measured capacitance values fall well below the equilibrium
minimum value. The lower dotted line in Figure 10 illustrates
this phenomenon. Equivalent 3-element Simplified model used
model of MOS capacitor to determine RSERIES
Using the preferred sequence. Generating a C-V curve by in strong accumulation
sweeping from inversion to accumulation is faster and more
controllable than sweeping from accumulation to inversion. Figure 12. Simplified Model to determine series resistance
Figure 11 illustrates a preferred measurement sequence.
The corrected capacitance (C ADJ) and corrected conductance
(GADJ) are calculated from the following formulas [1]:
Bias
Hold Time (G2 + (2fC)2)C
Bias Start Voltage CADJ = ____________________
Voltage aR2 + (2fC)2
(G2 + (2fC)2)aR
Delay
Time
GADJ = ____________________
aR2 + (2fC)2
0V Light where:
Pulse
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