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Freescale Semiconductor, Inc.
MC68302
Freescale Semiconductor, Inc...
Integrated Multiprotocol Processor
User's Manual
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ii MC68302 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
PREFACE
The complete documentation package for the MC68302 consists of the M68000PM/AD,
MC68000 Family Programmer's Reference Manual, MC68302UM/AD, MC68302 Integrated
Multiprotocol Processor User's Manual, and the MC68302/D, MC68302 Integrated Multipro-
tocol Processor Product Brief.
The MC68302 Integrated Multiprotocol Processor User's Manual describes the program-
ming, capabilities, registers, and operation of the MC68302; the MC68000 Family Program-
mer's Reference Manual provides instruction details for the MC68302; and the MC68302
Low Power Integrated Multiprotocol Processor Product Brief provides a brief description of
the MC68302 capabilities.
This user's manual is organized as follows:
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Section 1 General Description
Section 2 MC68000/MC68008 Core
Section 3 System Integration Block (SIB)
Section 4 Communications Processor (CP)
Section 5 Signal Description
Section 6 Electrical Characteristics
Section 7 Mechanical Data And Ordering Information
Appendix B Development Tools and Support
Appendix C RISC Microcode from RAM
Appendix D MC68302 Applications
Appendix E SCC Programming Reference
Appendix F Design Checklist
ELECTRONIC SUPPORT:
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at 14,400 bps or slower. Set your software to N/8/1/F emulating a vt100.
Internet: This access is provided by telneting to pirs.aus.sps.mot.com [129.38.233.1] or
through the World Wide Web at http://pirs.aus.sps.mot.com.
-- Sales Offices --
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MC68302 USER'S MANUAL iii
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iv MC68302 USER'S MANUAL
For More Information On This Product,
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Freescale Semiconductor, Inc.
TABLE OF CONTENTS
Paragraph Title Page
Number Number
Section 1
General Description
1.1 Block Diagram......................................................................................... 1-1
1.2 Features .................................................................................................. 1-3
1.3 MC68302 System Architecture ............................................................... 1-4
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1.4 NMSI Communications-Oriented Environment ....................................... 1-5
1.5 Basic Rate ISDN or Digital Voice/Data Terminal .................................... 1-6
Section 2
MC68000/MC68008 Core
2.1 Programming Model................................................................................ 2-1
2.2 Instruction Set Summary......................................................................... 2-3
2.3 Address Spaces ...................................................................................... 2-6
2.4 Exception Processing.............................................................................. 2-8
2.4.1 Exception Vectors ................................................................................... 2-8
2.4.2 Exception Stacking Order ....................................................................... 2-9
2.5 Interrupt Processing .............................................................................. 2-11
2.6 M68000 Signal Differences ................................................................... 2-11
2.7 MC68302 IMP Configuration Control .................................................... 2-12
2.8 MC68302 Memory Map......................................................................... 2-14
2.9 Event Registers..................................................................................... 2-19
Section 3
System Integration Block (SIB)
3.1 DMA Control............................................................................................ 3-2
3.1.1 Key Features........................................................................................... 3-2
3.1.2 IDMA Registers (Independent DMA Controller) ...................................... 3-3
3.1.2.1 Channel Mode Register (CMR)............................................................... 3-4
3.1.2.2 Source Address Pointer Register (SAPR)............................................... 3-6
3.1.2.3 Destination Address Pointer Register (DAPR)........................................ 3-6
3.1.2.4 Function Code Register (FCR)................................................................ 3-7
3.1.2.5 Byte Count Register (BCR) ..................................................................... 3-7
3.1.2.6 Channel Status Register (CSR) .............................................................. 3-7
3.1.3 Interface Signals ..................................................................................... 3-8
3.1.3.1 DREQ and DACK.................................................................................... 3-8
3.1.3.2 DONE...................................................................................................... 3-8
3.1.4 IDMA Operational Description................................................................. 3-9
3.1.4.1 Channel Initialization ............................................................................... 3-9
3.1.4.2 Data Transfer .......................................................................................... 3-9
MC68302 USER'S MANUAL v
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Table of Contents Freescale Semiconductor, Inc.
Paragraph Title Page
Number Number
3.1.4.3 Address Sequencing..............................................................................3-10
3.1.4.4 Transfer Request Generation ................................................................3-11
3.1.4.5 Block Transfer Termination....................................................................3-12
3.1.5 IDMA Programming ...............................................................................3-13
3.1.6 DMA Bus Arbitration ..............................................................................3-14
3.1.7 Bus Exceptions ......................................................................................3-14
3.1.7.1 Reset......................................................................................................3-15
3.1.7.2 Bus Error................................................................................................3-15
3.1.7.3 Halt.........................................................................................................3-15
3.1.7.4 Relinquish and Retry..............................................................................3-15
3.2 Interrupt Controller .................................................................................3-15
3.2.1 Overview ................................................................................................3-16
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3.2.1.1 IMP Interrupt Processing Overview .......................................................3-16
3.2.1.2 Interrupt Controller Overview .................................................................3-17
3.2.2 Interrupt Priorities...................................................................................3-18
3.2.2.1 INRQ and EXRQ Priority Levels ............................................................3-18
3.2.2.2 INRQ Interrupt Source Priorities ............................................................3-19
3.2.2.3 Nested Interrupts ...................................................................................3-19
3.2.3 Masking Interrupt Sources and Events ..................................................3-20
3.2.4 Interrupt Vector ......................................................................................3-21
3.2.5 Interrupt Controller Programming Model................................................3-24
3.2.5.1 Global Interrupt Mode Register (GIMR) .................................................3-24
3.2.5.2 Interrupt Pending Register (IPR)............................................................3-26
3.2.5.3 Interrupt Mask Register (IMR)................................................................3-27
3.2.5.4 Interrupt In-Service Register (ISR).........................................................3-28
3.2.6 Interrupt Handler Examples ...................................................................3-28
3.3 Parallel I/O Ports....................................................................................3-29
3.3.1 Port A .....................................................................................................3-29
3.3.2 Port B .....................................................................................................3-31
3.3.2.1 PB7◦ Jabse Service Manual Search 2026 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo