Service Manuals, User Guides, Schematic Diagrams or docs for : Keithley 501 501_911_01B
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IBIN=PS/2
Interface for IBM W/2 and Compatibles
with Microchannel Architecture
The IBIN-PS/2 interface plugs into any of the expansion To install the IBlN-E'S/2 interface card you will need a
slots in IBM PS/2 Models 50, 55SX, 60, 70 and 80 or backup copy of the Reference diskette that was provided
compatibles, and serves as an interface between the com- with your computer. The Reference diskette contains
puter and the Models 5OOA, 5OOP,and 575. The interface various programs and files that are essential to installing
card contains POS circuitry, address buffering and decod- new peripherals in your computer. If you do not have a
ing, data buffering, configuration and status information, back-up copy of the Reference diskette, you must make one
a programmable interval timer, and interrupt generation according to the instructions provided with your com-
circuitry. puter.
Software Support The installation procedure for the lBIlGl?S/2 interface card
consists of several steps. First, the interface card itself must
The IBIN-I'S/2 interface card requires the use of Soft500 be physically installed in the computer. Then the computer
Version 5.2 or later, Quick500 Version 1.2 or later, or must be reconfigured to recognize the interface card. Once
KDAC500. If third-party data acquisition software is used, the computer is properly configured, theSoft500, Quick500,
it must support the features and operation of the IBIN-PS/ or KDAC500 installation should be run in order to check
2. Note: Even if you plan to use third-party software for correct operation (even if you are planning to run other
exclusively, you will need the "@6571.ADF" file included software exclusively).
with your Keithley software to install the IBIN-PS/2 in
your computer.
The following directions and illustrations show the IBM
PersonalSystem/2Model50. For other models, consult the
documentation which accompanies the computer.
Reading TIME/DATE with Keithley 500~Series
Software
IBIN-PS/2 Hardware Installation
The CLQCKREAD command of Soft500 V5.2 and Quick500
Vl.2, and the KDCLOCKcommand inKDAC500 default to
Install the IBIN-PS/2 into a vacant expansion slot as fol-
reading the battery-backed clock and calendar located on
lows: Make sure the PS/2 is turned off, and unplug the
the computer's mother board. This operation supplies time
power cord. Check that the cover is unlocked, and then
and date information within a test program even though
loosen the thumbscrews at the rear of the system unit.
the IBIN-PS/2 does not have a battery-backed clock and
Remove the cover by sliding it forward approximately two
calendar of its own. To set time and date, use the standard
inches, and then lifting it (see Figures 1 and 2).
computer set-up program, or other utility suggested by the
computer manufacturer. Do not use the SETCLOCKutility
which may be included with the Keithley software.
A rear panel opening is provided at the end of each
expansion slot for mounting I/O connectors. If a slot is
unused, then this opening will be covered by a metal plate
Installing the IBIN-PSI2 Interface Card held in place by a thumbscrew (Figure 3). Loosen the
thumbscrew (use a coin if it is too tight) and remove the
CAUTION cover plate from the desired expansion slot.
Turn power off before installing or removing
the interface card.
Document Number: 501-911-OlB IBIN-F'S/1
l%liV-PSI2
Interface for IBM PSJ2Models and Compafibles
with Microchannel Architecture
Carefully install the IBIN-E/2 card by fitting the DB25 Finally, attach the interface cable to the connector (J2) on
connector through the rear panel and firmly pressing it the interface card at the rear of the computer. Never strain
into the expansion slot until the card clicks into place the connection between cable and connector. The other end
(Figure 4). With the board firmly in place, tighten the of the cable should be plugged into the mating connector
thumbscrew. on the rear panel of the Series 500. Avoid entangling the
interface cable in 60 cycle AC power lines or other noisy
Slide the cover back on and tighten the thumbscrews, lock lines.
the cover lock, and reconnect the cables and power cords to
the rear of the computer. Plug the power cord into an The system is now ready for hardware configuration and
electrical outlet. software installation.
1Figure I. Removing PSI2 Cover Screrws
3gure 2. Removing PSI2 Cover
IBIN-E/2
Interface for IBM PSf2 Models and Compatibk
with Microchannel Architecture
Figure 3. Removing Expansion Slot Cover
Figure 4. Installing lBIN-PSI2
IBIN-I?s/3
IB'BIN-PSI2
Interface for IBM PS/2 Models and Compatibles
with Microchannel Architecture
IBIN-PSM Hardware Configuration You should then see a menu. Use the /cDown>
arrow keys to choose item 5, "Copy an option diskette"
from the menu. Then press to perform the indi-
There are no hardware switches to set when installing the
cated operation. "Copy an option diskette" is used to copy
interface card into your computer. The PS/2 family of
the configuration files from the Keithley 500-Series software
computers uses a different method for selecting a particu-
diskette ("the New Option Diskette") to the back-up copy
lar hardware configuration called "software switches". The
of the Reference diskette ("the Product 2 diskette"). Follow
following discussion details the procedure for setting these
the displayed instructions to copy the files.
switches using the configure program supplied by IBM.
Now the system is ready for configuration. Select item 3,
Insert the back-up copy of the Reference diskette into drive
"Set Configuration", and press cEnter>. From the con-
A: and turn the computer and display on. The system
figuration menu choose item 2, "Change Configuration",
should boot from the Reference diskette and display the
and press .
start-up screen with IBM logo. You may notice "165" on the
display screen during the power-on self-test. This number
indicates that the computer has noticed (correctly) that
Now, check that the address shown for IBIN-I'S/2 is OCFF80.
there has been a change in hardware configuration.
If necessary, use the cursor keys to move to the address
entry for the I'S/2 interface. Press the cF5> or cF6> keys to
toggle to the address OCFF80. When you are done, press
NOTE
cFlO> to save the information, and then press .
You will not be able to use the computer until it
Press to restart the system.
Reference diskette.
Conclude with software installation program.
If the computer does not boot-up, first check that you are
using a back-up copy of the Reference diskette and that it
is correctly inserted in drive A:. If you do not have a back-
up copy, turn the power off, remove the IBIN-l?S/2 inter- Installing More Than One IBIN-PS/2 in a
face, and follow the instructions that came with the Refer- Personal System/2
ence diskette to make a back-up copy. Then re-install the
IBIN-F'S/2 interface and re-boot the computer with the Install the IBIN-PS/2 interfaces in the PS/2 expansion
new back-up Reference diskette. slots. Consult the IBM and IBIN-l?S/2 documentation for
instructions on opening the computer and installing the
IBIN-PS/2 cards. When you are done installing the inter-
If the computer still does not boot, check to see that all faces, replace the cover.
cables and circuit boards'are installed correctly. If every-
thing appears to be correct, but the computer still does not
boot from the back-up copy of the Reference diskette, then Consult the previous section which describes running the
contact Keithley Data Acquisition and Control for assis- IBM-supplied hardware configuration program. As nec-
tance. essary, follow the instructions for copying the reference
diskette and option diskette.
Once the Reference diskette has booted, you should press
the key to continue. At this point you should see Now the system is ready for configuration. Select item 3,
the first two screens indicating that the computer has "Set Configuration", and press . Use the cursor keys to move to the
NJ". As we are not yet ready for automatic configuration, address entry for each I'S/2 interface. Select a different
you should answer "No" by pressing the "N" key. address for each IBIN-ES/2 card by pressing the 6;5> or
IEm-PS/4
lBliWW2
Interface@ IBM PS/2 Models and CompatrHe
with Microchannel Architecture
keys to toggle up or down through the available
addresses. Suggested addresses are OCFF80 for the inter- MSB LSB
face in the lowest-numbered slot, OCFB80 for the second llxx xxxx xx11 1000 0000
interface, OCF780 for the third interface, and so on. There C 0 3 8 0
are many possible addressed which should be compatible C 0 7 8 0
with any other hardware you may have in the PS/2. C 0 B 8 0
Confirm that no other hardware is using the addresses you C 0 F 8 0
have assigned for the IBIN-PS/2 cards. C 1 3 8 0
Use the cursor keys to move the interrupt entries for each
PS/2 interface. The IBM Configuration program should
already have set the interrupt level for the IBIN-l?S/2
interfaces to "10". Let the address for the IBIN-l?S/2 in the
lowest-numbered slot at "10". Use the cursor keys to move
to the interrupt level for each of the other interfaces, and
thendisable theinterrupt by pressing the key to select
"Not Used'. "x" = user-confimrable address bit.
When you are done, press &lo> to save the information. Note that many of the possible address for the Keithley
interface will conflict with other hardware already in the
system, such as fixed disks, video adapters, and expansion
Press twice. Eject the diskette, and then press to restart the computer. the hardware provides for. The configure program limits
your choices to areas where the IBIN-I'S/2 has been used
successfully.
Conclude with software installation.
Memory conflicts occur when the computer attempts to
Parameters (OPTIONAL) read an address occupied by more than one piece of
hardware. These probIems can be manifest as error mes-
Hardware configuration is normally automatic, but it is sages at boot-up, or failure of the hardware or Keithley
possible to modify the configuration by using the Change system to operate properly. If this occurs, examine the
Configuration option on the Reference diskette. Change memory usage of all the hardware in your computer, and
Configuration allows you to set the IBIN-l?S/2 interface make changes where necessary. Usually, changing the
hardware parameters: Memory Mapped Base Address address of the Keithley interface is all that is required.
and Interrupt Level. The parameters should be set accord- Normally, the configuration program will prevent you
ing to the following guidelines: from getting into trouble when changing these parameters.
The Memory Mapped Base Address selects the address You should have ,no technical difficulty finding usable
range of the interface in the PS/2 system memory map. addresses, although you may have to do some research to
This is normally set for a starting location of hex CFF80 (the find out what addresses are free in your computer.
factory default), but can be configured over the addressing
range of Hex CO380 through FFF80. This setting deter-
mines only 8 bits of the Series 500's address region, the The Interrupt Level for the IBIN-PS/2 interface board
other 12 bits are hard-wired as follows. should normally be set to 10 which is the highest priority
interrupt available on the PS/2 bus. This interrupt is used
IBIN-E/5
IBIN-PSI2
Interface for IBM PS/2 Models and Compatibles
with Microchannel Architecture
to provide timing for data acquisition. The higher the The address decoding circuitry, U14, U17, U18 and U22,
priority of the interrupt, the less jitter will occur on the uses the microchannel address lines, the read/write lines
timing of the data acquisition. If your timing must be fast, (SO and Sl>, the M/-IO line, the -CMD line, and POS
such as 1 to 100 milliseconds, you should use the higher register 3 (the base memory address). The POS register,
priority interrupt. If your timing requirements are slower, U17, is initialized at power-up with memory address bits
such as 0.1 to 1 second, you may consider using a lower 10-17, the interface address. U18, an 8 bit comparator,
priority interrupt. The "Not Used" option may be selected compares the stored address with incoming microchannel
for programs that do not use the interface card to generate addresses. Address bits A7-A9, Al8 and Al9 are checked
interrupts. for logic "1" by U22, A21-A23 are checked for logic "0" by
U14, and A20 is checked for logic "0" by U18. The read/
write lines -SO, -Sl are also used in U14 as part of the
Interrupt level 10 has the highest priority followed by decoding. The result is a signal, -CD SFDBK, that repre-
levels 11,15,3,4,5, and 6 with the lowest priority. sents "IBIN is addressed" on pin 19 of U14. U14 is also used
to create several other decoding and timing signals as
follows:
Software Installation
pin 18 CD CHRDY - Data ready signal to the
The system is now ready for software installation. Refer to microchannel bus (wait state generator)
the Keithley or third-party software manual for details on pin 17 /CDSEL - Latched version of "IBIN" is
installing your software. If you are using a third-party addressed"
software package, make sure that it is compatible with the pin 15-16 /BSO and /BSl -Latched versions of SOand Sl,
IBIN-%/ before you start. Consult the manufacturer's read and write
documentation. pin 14 MBSEL - Select pulse for use by external
chassis, gated by MBEN
pin 13 CMDRC - from -CMD -Used as time delay for
CD CHRDY and MBSEL
Theory of Operation
pin 12 SETLRC - from -CMD -Used as time delay for
MBSEL
The interface to the Series 500 is provided through connec-
tor J2. The connector contains five address lines (MBAO-
MBA4), a read/write (MBR/W), and a select line (MBSEL)
Address Decoding Circuitry-Local
which control the Series 500. The connector also contains
an eight bit data bus (MBDO-MBD7), a mother board
interrupt request line (MBIRQ), and 5 lines for power (+5V) U9a and U6 provide the local decoding of the following
and ground. Figure 5 shows the component layout of the regions of the local address map:
IBIN-PS/2 interface. Refer to Component Layout.
U9a pin12 /READ -General purpose read/-write line -
POS or memory map
pin 13 /IOR - I/O space read for POS
Address Decoding Circuitry-Global
pin 14 /IOW - I/O space write for POS
pin 15 /CONTEN - Control registers for TIMER
The interface is memory-mapped to the host computer and GLOBAL (offsets Hex 60-63)
responds to READ and WRITE commands. It does not U6 pin6 /8254CS - Selects the 8254 (Ul) registers
respond to the INT and OUT peripheral commands used (offsets Hex 40-43)
by most peripheral devices. pin4 /MBEN -Selects the external chassis address
space (offset Hex 00-lD>
pin 10 /CLRINT - Clear interrupt latch
The interface maps into a 128-byte region of memory pin11 /RSTAT - Read the status register TIMER
which may be positioned by the user in one of the 256 STATUS
region defined by the address bits MAlO-MA17 which are pin 12 / WCONFIG - Write to configure register
stored in programmable option select @OS) register 3. See TIMER GLOBAL
Section 3 of Installing The interface Card, hardware Pa-
rameters, for more information.
IBIN-l's/6
Interface fir IBM E'S/2Models and Compatible
with Microchannel Architecture
Programmable Option Select (POS) Table 1. Memory Map locations and Functions
Registers and Logic
(Presumes prior execution of a DEF SEG=CFF8 command)
U5 decodes the particular address of a POS location using
Function/Use Location (hex)
the SETUP signal from U21 and the three buffered address
signals from U21, BAO-BA.2. U3 provides the interface ID
Slot 1 CMDA xxx00
value. Ull stores the interrupt level value. U17 stores the
CMDB xxx01
base memory address as discussed earlier. U7b holds the
CMDC xxxlA
card enable flag and is reset from a buffered version of the
CMDD xxxlB
microchannel reset signal on power up (UlOc).
Slot 2 CMDA xxx02
CMDB xxx03
CMDC xxx18
Configuration and Status Registers Slot 3 CMDA xxx04
CMDB xxx05
U4 is a set of latches that hold the three configuration bits CMDC xxx19
for TIMER GLOBAL. Pin 7 is the Interrupt Enable flag, pin Slot 4 CMDA xxx06
15 and pm 10 are the configure bits that control the clock CMDB xxx07
signals to the 8254 (Ul) timer chip. U2 buffers the status Slot 5 CMDA xxx08
signals onto the data bus using the RSTAT signal discussed CMDB xxx09
earlier. The five status bits reflect the output of the three Slot 6 CMDA xxxOA
counters of the 8254 (pins 2,4 and 6), the external chassis CMDB xxxOB
interrupt signal (pin 12) and the interrupt latch value (pin Slot 7 CMDA xxxoc
14). CMDB xxxOD
Slot 8 CMDA xxxOE
CMDB xxxOF
Interrupt Latch and Drivers Slot 9 CMDA xxx10
CMDB xxx11
UI3 and U12 drive the interrupt lines on the microchannel Slot 10 CMDA xxx12
bus. U7A uses the output of counter 0 of the 8254 (Ul) to CMDB xxx13
clock the interrupt enable signal, INTEN, stored in U4. R/W COUNTER 0 xxx40
Provisions for external chassis interrupts are also provided R/W COUNTER 1 xxx41
through UlOd. R/W COUNTER 2 xxx42
COUNTER CONTROL xxx43
Address and Data Latching/Buffering TIMER GLOBAL xxx60
TIMER STATUS xxx61
CLEAR INTERRUI'T xxx62
U21 is used to latch the required bus signals on -CMD. SET INT LEVEL xxx63
These include address bits AO-A6 and the SETUP signal
indicating a POS access. U15 and U19 buffer the data bus
between the microchannel, and IBIN circuitry, and the The programmable interval timer can be used to time
external chassis. U20 buffers the address and the control events, create software delays, and generate periodic in-
signals to the external chassis. terrupts to the PS/2. The timer consists of three indepen-
dent 16 bit counters, which can be cascaded together to
create longer timing intervals. The timer uses a 1.02MHz
Programmer Model for the Memory Map input which is generated by dividing the 14.31818MI-I~
OSC pin on the microchannel bus by 14 using U16. This
A summary of memory locations used with the interface allows the timer to have a resolution of 977ns. The least
card is given in Table 1. These addresses correspond to the significant counter allows timing up to 64.lms. Two cas-
"Command A" and "Command B" functions associated caded counters allow up to almost 70 minutes, and three
with each module in the Series 500 module library. Note cascaded counters allow timing up to 8.7 years.
that some modules also use "Command c" and "Command
D" for special functions. Collectively, these addresses are
labeled "CMDA", "CMDB", "CMDC", and `CMDD".
IBIN-IS/7
IBIN-PSI2
interface for IBM PS/2 Models and Compatibles
with MicrochanneI Architecture
INTERRUPT
(WRITE)
I yI __ TIMER
JTR 0
L I
INT3
16 INT4
I 1
7'1
INT5
,6 (R/W)
INT6
CNTR-2
16 (R/W)
CNTR-CTL
SET INTERRUPT
(W%)
"ww
TIMER STATUS
(READ)
Figure5. Funcfional BlockDiagram of IBIN-PSI2 Timer Circuit
R/W COUNTER 0 R/W COUNTER 2
Location: xxx40 Location: xxx42
This location is used to load counter 0 with the interval This location is used in the same way as R/W COUNTER
count, as well as to read the interval from that counter. Data 0, except it applies to counter 2.
to this location is always sent as two bytes in succession.
The first WRITE (or READ) is the low byte of the count, and
the second WRlTB (or READ) the high byte. The read or COUNTER CONTROL
write must be issued twice for the counter to function. The
counter automatically makes the low byte register avail- Location: xxx43
able first followed by the high byte register.
An access to the COUNTER CONTROL location always
precedes the R/ W COUNTERcommands discussed above,
A write to COUNTER CONTROL (see discussion below) indicating to the timer which of the three counters is to be
must always precede any R/W COUNTER commands. addressed, and in what mode that counter will be used.
COUNTER CONTROL should always be followed by two
successive R/W COUNTER commands for the specified
R/W COUNTER 1 counter.
Location: xxx41
The counters can be used in three modes: interrupt gen-
This location is used in the same way as R/W COUIVIER erator, carry generator, and latch mode. Counter 0 cannot
0, except it applies to counter 1. be used as a carry generator, and counters 1 and 2 cannot
IBIN-PS/8
lBlWPSI2
Inferfacefor IBM PS/2 Models and Compafible
with Microchannel Architecture
generate interrupts. This functionality is due to the TIMER TIMER GLOBAL
GLOBAL circuitry discussed below.
Location: xxx60
The interrupt mode allows counter 0 to produce periodic This location is used to set mode of the timer circuitry. In
interrupts. When two or three counters are linked, the any routine involving the timer, this command should be
carry generator mode causes the terminal count of one issued prior to the COUNTER CONTROL and R/W
counter to trigger the count in another counter (see Table COUNTER commands. If it is not issued, all interrupt and
2). The counters can be used for timing events and creating carry functions will be off.
software delays by masking off the interrupts using the
TIMER GLOBAL location.
The lower three bits of this location determine whether the
Table 2. Values Written to COUNTER CONTROL interrupt circuitry of the timer is enabled, and whether any
of the counters will be Iinked with the carry generator.
Mode Counter 0 Counter 1 Counter 2
Interrupt 00110100 Not used Not used When the computer is first turned on or when the system
Generator Hex 34 is rebooted, all functions associated with this command are
52 (Decimal) initialized to off.
Not used 01110100 10110100
Generator Hex 74 Hex B4
116 180 Table 4 provides a summary of values written to the
Latch 00000000 01000000 10000000 TIMER GLOBAL location. Table 5 describes the bit con-
Hex 00 Hex 40 Hex 80 figuration of these values.
0 64 128
Table 4. Values Written to TIMER GLOBAL
In general, the count is always carried from counter 2 to No Cany Carry Carry
counter 1 to counter 0. When linked, counter 0 is always the Mode carry 1-o 2-l 2-1-o
carrier of counts generated by higher numbered counters,
and should be set to interrupt mode. The higher numbered Counter 0 0000 0001 0010 0011
counters should be set to carry generator mode. When only interrupt HO0 HO1 HO2 HO3
counters 2 and 1 are linked, counter 1 should be set to off. 0 1 2 3
interrupt mode, and counter 2 to carry generator mode.
Counter 0 0100 0101 0110 0111
interrupt HO4 HO5 HO6 HO7
The latch mode is used to read the counters. The latch on. 4 5 6 7
transfers the count into an intermediate register, allowing
a stable reading without disturbing the count in progress.
Table 3 describes the bit configuration of values written to Table 5. Bit Configuration of Values Written to TIMER
the counter control location. GLOBAL
D7 D6 D5 D4 D3 D2 Dl DO
Table 3.Bit Configuration of Values Written to COUNTER x x x x x INT 2-1 l-o
CONTROL
Explanation:
D7 D6 D5 D4 D3 D2 Dl DO X Not used
(--SC----) (---W/L--) 0 1 0 0 Interrupt ON/OFF (OFF=O, ON=l)
2-1 carry Counter 2 - Counter 1 (OFF=O, ON=l)
Explanation: 1-O carry Counter 1 - Counter 0 (OFF=O, ON=l)
SC (Select Counter) Counter 0 = 00
Counter 1 - 01
Counter 2 - 10
W/L (Write/Latch) Latch = 00
Write = 11
IBIN-!%/
IBIWPSI2
Interface@ IBM PS]2 Models and Compatibles
with Microchannel Architecture
TIMER STATUS timer status location to 0, and is used in interrupt service
routines to allow the generation of subsequent interrupts.
It should be issued after saving the registers and assessing
Location: xxx61
the source of the interrupt (see TIMERSTATUS) but before
other actions in the interrupt service routine. If this com-
The TIMER STATUS location can be read to view the
mand is not issued, no further interrupts will be generated.
output status of the interrupt circuitry and the three counters
of the 8254 (~1) counter/timer. The status of the interrupt
latch is assigned to bit 7 of this location, and the status of
Writing any number to this location will clear the interrupt
counters 0,l and 2 are assigned to bits 0,l and 2, respec-
circuitry (0 is often used for convenience, but is not re-
tively (See table 6).
quired).
Table 6.Bit Configuration of Values Read from TIMER
STATUS
USING QEMM WITH THE IBIN-PS/2
D7 D6 D5 D4 D3 D2 Dl DO
INT x x x x c2 Cl co When using the IBIN-PS/2 in a computer running the
"QEMM" memory manager, note the following:
Explanation:
X Not used 1. The line in CONFIG.SYS which invokes QEMM should
INT Interrupt status 1 = Active interrupt "exclude" the address range of the IBIN-PS/2. For in-
0 = No interrupt stance, if the IBIN-ES/2 is located at OCFF80(hex), a
C2 Counter 2 status 1 = Output line high typical line might take the form:
0 = Ouptut line low
Cl Counter 1 status 1 = Output line high DEVICE = C:QEMM386.SYS EXCLUDE CJTFO-CFFF
0 = Output line low
CO Counter 0 status 1 = Output line high 2. An error message advising "Unknown Microchannel ID
0 = Output line low 6571" may occur during boot-up. This error message is
caused by the QEMM software being unable to recognize
the IBIN-PS/2 card. QEMM contains a file which lists
If there is more than one device generating interrupts in the compatible microchannel cards. This file is called
system, the interrupt processing routine must determine "MCA.ADL", and does not include the IBIN-PS/2. There
whether the interrupt received was generated by the Series are three solutions:
500 unit. Each time the Series 500 generates an interrupt, bit
7 of the TIMER STATUS location is set to 1. This bit is l You may simply ignore the error message and press
cleared to 0 when the CLEAR INT command is issued. to continue.
l You may suppress the error message by adding No
Pause On Error ("NOPE") to the "DEVICE = ...`I line
The other bits in this location are used in software delay shown above:
routines. Each of these bits is set independently, and can be
read separately. When a counter is first loaded, the bit is set DEVICE = CzQEMM386SYS EXCLUDE CFFU-CFFF NOPE
to 1. Halfway through the count, the bit is set to 0, and at the
terminal count, the bit is reset to 1. A delay routine waiting 0 Youmay add thelBIN-PS/2information to theMCA.ADL
for the terminal count should first check for 0, and when 0 file. The QEMM manual contains instructions for this
has been read, check for 1. operation.
See your memory manager software documentation for
CLEAR INTERRUPT specific details.
Location: xxx62
This location is used to clear the interrupt status bit of the
IBlN-l?S/lO
OLI-10s .UNI LTR
E
ECU NO.
7
14.5 5
REVISIUN
BOARD COMPLETELY RE-DESIGNED
~~~~~;,R~~~:";~C22C2O~U23
ENG,
SAS
DATE
4-a-91
BR-32 (3 PIECES>
#4-40 X 3/8 PPH \ -RR-??
AND #4 KEPNUT
3 PCS EACH
cs-492
MC-285, CLIMPUNENT SIDE AFS #4-40 X l/4 PPH ' '
AND #4 KEPNUT
NOTE1 (1 EACH>
FOR COMPONENT INFORMATION, REFER TCI
BILL OF MATERIALS 501-973
xx=+/-.015 ANG.=+/-lo ' DRN. SAS j INll. <5'&
,&& 1SERIES 500 PS/2 INTERFACE
kfwkay
Ins-t5 Inc. xxx=+/-.005 N/A
arti ohlo
4,139 FRAC.=+/-l/64 MATERIAL
SURFACE MAX. \6Y FINISH N/A lB/"". 501-170
II- II
I
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