Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop COMPAL_LA-3781P_-_EVEREST_-_REV_0.1
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A B C D E
ZZZ ZZZ1 ZZZ2 ZZZ3 ZZZ4
PCB PCB PCB PCB PCB
DAZ@ DAZ@ DAZ@ DAZ@
1 1
Compal Confidential
2 2
Everest Schematics Document
Intel Merom Processor with Calistoga + DDRII + ICH7M
3
2007-05-15 3
REV: 1.0
4 4
om
l.c
ai
Security Classification Compal Secret Data Compal Electronics, Inc.
tm
Issued Date 2006/08/18 2007/8/18 Title
ho
Deciphered Date
Cover Page
f@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
in
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
LA-3781P
xa
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
he
Date: Friday, May 18, 2007 Sheet 1 of 46
A B C D E
A B C D E
Compal Confidential
Model Name : Everest Intel Merom Processor
File Name : LA-3781P uPGA-478 Package
1
page 4,5,6 1
FSB
H_A#(3..35) 667/800MHz H_D#(0..63)
CRT CRT CRT
NB8M page 19
128M Intel Calistoga GMCH Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
VGA/B LVDS Dual Channel BANK 0, 1, 2, 3 page 14,15
LCD Conn. LVDS
page 18 1.8V DDRII 533/667
PCBGA 1466
PCI-Express
page 7,8,9,10,11,12,13
DMI USB conn x2 USB conn x2 3 in 1
Bluetooth Card Reader socket
X4 mode TO M/B TO I/O/B RTS 5158
page 33 page 37
Conn page 33 page 28
page 29
2 2
PCI-Express USB
Intel ICH7-M 3.3V 48MHz
3.3V 24.576MHz/48Mhz HD Audio
3.3V ATA-100 IDE
mBGA-652
S-ATA port 0
page 20,21,22,23
New Card MINI Card LAN(10/100M) MDC 1.5 HDA Codec
Socket WLAN,
BCM5906 Conn 42
page
ALC861VD
page 38
page 33 3G/TV-Tuner
Robson page 32 page 30
S-ATA HDD CDROM
LPC BUS Conn.page 24 Conn. 24
page
Audio AMP
RJ45 page 39
3
page 31 3
ENE KB926 SPI ROM BIOS Int SPK Mic/Int
page 34 page 36
USB BD Audio BD
Fan Control Touch Pad Int.KBD
page 4 K_SW page 36 Line-out Mic/Ext
page 35
Clock Generator Sub BD
SLG8LP465VTR
page 16 USBx2
Thermal Sensor
4
G781F 4
page 4
SW Board
HDD/ODD NUM CAP Scroll NOVO Mute User Power
Power circuit
page X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Power Battery W/L
MB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3781P
Date: Friday, May 18, 2007 Sheet 2 of 46
A B C D E
A B C D E
1 1
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Voltage Rails
External PCI Devices
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
DEVICE IDSEL # REQ/GNT # PIRQ
B+ AC or battery power rail for power circuit. N/A N/A N/A
No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
2 2
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
EC SM Bus1 address EC SM Bus2 address
+RTCVCC RTC power ON ON ON
Device Address Device Address
Smart Battery 0001 011X b GMT-781 1001 100X b
EEPROM(24C16/02) 1010 000X b NVIDIA NB8X
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
3 ICH7M SM Bus address 3
Device Address
BOARD ID Table
Clock Generator 1101 001Xb
ID BRD ID R54/42(Rb) Vab (SLG8LP465VTR)
I I 0 R01 (EVT) 0 0V DDR DIMM0 1010 000Xb
H H
L L 1 R02 (DVT) 8.2K 0.25V DDR DIMM1 1010 010Xb
0 V
0 2 2 R03 (PVT) 18K 0.50V
/ Wireless
3 3 R10A (MP) 33K 0.82V NewCard
I 4 R01 (EVT) 56K 1.19V
G LAN
T 5 R02 (DVT) 100K 1.65V
3
0 6 R03 (PVT) 200K 2.20V
7 R10A (MP) NC 3.30V
PANEL ID Table
ID UMA_DES Vab
4
0 IHL00/IGT30 UMA 3.30V 4
1 IHLV3 UMA 2.20V
2
om
3
l.c
ai
4 Security Classification Compal Secret Data Compal Electronics, Inc.
tm
5 Issued Date 2006/08/18 2007/8/18 Title
ho
Deciphered Date
Notes List
f@
6 IHLV2 VGA 0.25V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
in
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
7 IHL00/IGT30 VGA 0V B 0.1
LA-3781P
xa
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
he
Date: Friday, May 18, 2007 Sheet 3 of 46
A B C D E
5 4 3 2 1
+VCCP
<7> H_A#[3..31] H_D#[0..63] <7>
JP15A This shall place near CPU
ITP_TDI R509 1 2 56_0402_5%
H_A#3 J4 E22 H_D#0
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2
ITP_TMS R510 1 2 56_0402_1%
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3 ITP_TDO R512 1 2 56_0402_5%
H_A#7 A6# D3# H_D#4
M1 A7# D4# F23
H_A#8 N2 G25 H_D#5 R515 1 2 56_0402_5%
H_A#9 A8# D5# H_D#6 @
J1 A9# D6# E25
H_A#10 N3 E23 H_D#7 ITP_TRST# R513 1 2 56_0402_5%
H_A#11 A10# D7# H_D#8
P5 A11# D8# K24
H_A#12 P2 G24 H_D#9 ITP_TCK R514 1 2 56_0402_5%
D H_A#13 A12# D9# H_D#10 D
L1 A13# D10# J24
H_A#14 P4 J23 H_D#11
H_A#15 A14# D11# H_D#12
P1 A15# D12# H26
H_A#16 R1 F26 H_D#13
H_A#17 A16# D13# H_D#14
Y2 A17# D14# K22
H_A#18 U5 H25 H_D#15 ITP_DBRESET# R511 1 2 @ 200_0402_5% PAD T35
H_A#19 A18# D15# H_D#16
R3 A19# D16# N22
H_A#20 W6 K25 H_D#17
H_A#21 A20# D17# H_D#18
U4 A21# D18# P26
H_A#22 Y5 R23 H_D#19
H_A#23 A22# D19# H_D#20
U2 A23# D20# L25
H_A#24 R4 L22 H_D#21
H_A#25 A24# D21# H_D#22
T5 A25# ADDR GROUP DATA GROUP D22# L23
H_A#26 T3 M23 H_D#23
H_A#27 A26# D23# H_D#24
W3 A27# D24# P25
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28 +3VS
<7> H_REQ#[0..4] Y1 A31# D28# R24
L26 H_D#29
D29# C327
H_REQ#0 K3 T25 H_D#30
H_REQ#1 REQ0# D30# H_D#31
H2 REQ1# D31# N24 1 2
2
H_REQ#2 K2 AA23 H_D#32
H_REQ#3 REQ2# D32# H_D#33 0.1U_0402_16V4Z @ R268
J3 REQ3# D33# AB24
H_REQ#4 L5 V24 H_D#34 U19 10K_0402_5%
REQ4# D34# H_D#35 H_THERMDA
D35# V26 2 D+ VDD1 1
H_ADSTB#0 L2 W25 H_D#36 C328
<7> H_ADSTB#0
1
H_ADSTB#1 ADSTB0# D36# H_D#37 H_THERMDC THERM_SCI#
<7> H_ADSTB#1 V4 ADSTB1# D37# U23 1 2 3 D- ALERT# 6 2 1 EC_THERM# <21,31>
U25 H_D#38 2200P_0402_50V7K R267 @ 0_0402_5%
D38# H_D#39 EC_SMB_CK2 THERM#
D39# U22 <31> EC_SMB_CK2 8 SCLK THERM# 4 2 1 +3VS
AB25 H_D#40 10K_0402_5% @R269 Check : to sb
D40# H_D#41 EC_SMB_DA2
D41# W22 <31> EC_SMB_DA2 7 SDATA GND 5
C H_D#42 C
D42# Y23
CLK_CPU_BCLK A22 AA26 H_D#43
<15> CLK_CPU_BCLK BCLK0 D43# G781F_SOP8
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45
D45# Y22 Address:100_1100
AC26 H_D#46
D46# H_D#47
D47# AA24
H_ADS# H1 AC22 H_D#48
<7> H_ADS# ADS# D48#
H_BNR# E2 AC23 H_D#49
<7> H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52
<7> H_DEFER# DEFER# D52#
H_DRD Y# F21 AC25 H_D#53
R73
56_0402_5%
<7>
<7>
H_DRDY#
H_HIT#
H_HIT#
H_HITM#
G6
DRDY#
HIT#
D53#
D54# AD20 H_D#54
H_D#55
FAN1 Conn
<7> H_HITM# E4 HITM# CONTROL D55# AE22
1 2 H_IERR# D20 AF23 H_D#56
+VCCP H_LOCK# IERR# D56# H_D#57
<7> H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
<7> H_RESET# RESET# D58#
AD21 H_D#59
D59# H_D#60
<7> H_RS#[0..2] D60# AE25
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62 +5VS
F4 RS1# D62# AF22
H_RS#2 H_D#63 C100 2.2U_0603_16V6K +5VS
H_TRDY#
G3
G2
RS2# D63# AF26
1 2
DIODE
<7> H_TRDY# TRDY#
Closed to
1
J26 H_DINV#0
DINV0# H_DINV#0 <7> Connector
M26 H_DINV#1 U6 D8
DINV1# H_DINV#1 <7>
AD4 V23 H_DINV#2 1 8
BPM0# DINV2# H_DINV#2 <7> VEN GND
AD3 AC20 H_DINV#3 2 7 1SS355_SOD323
BPM1# DINV3# H_DINV#3 <7> VIN GND
AD1 +VCC_FAN1 3 6 @ D7
2
BPM2# EN_FAN1 VO GND @ 1N4148_SOT23
AC4 BPM3# H_DSTBN#[0..3] <7> <31> EN_FAN1 4 VSET GND 5
H23 H_DSTBN#0 1 2
ITP_DBRESET# C20 DSTBN0# H_DSTBN#1 G993P1UF_SOP8
<21> ITP_DBRESET# DBR# DSTBN1# M24
B H_DBSY# H_DSTBN#2 B
<7> H_DBSY# E1 DBSY# DSTBN2# W24
H_DPSLP# B5 AD23 H_DSTBN#3 C94
<20> H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] <7>
H_DPRSTP# E5 G22 H_DSTBP#0 2.2U_0603_16V6K
<20,44> H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1 1 2
<7> H_DPWR# DPWR# DSTBP1#
AC2 MISC Y25 H_DSTBP#2
<44> H_PROCHOT# T48 PRDY# DSTBP2# H_DSTBP#3 +3VS C358
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