Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop B590 WISTRON LA480 lenovo_b590_wistron_la480_sch
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5 4 3 2 1
UMA & Optimus Schematics Document
D D
IVY Bridge(rPGA989)
C
Intel PCH(Panther Point) C
DY :NotInstalled
UMA:UMA platform installed
OPS:Optimus
B
HR:Huron River B
CR:Chief River
V: V-Series installed
Wistron Corporation
A 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C
Title
Cover Page
Size Document Number Rev
A4 SD
LA480
Date: Friday, January 06, 2012 Sheet 1 of 103
5 ##OnMainBoard
4 3 2 1
Block Diagram CPU DC/DC
INPUTS
TPS51640
OUTPUTS
42~43
VRAM
(UMA/Optimus co-lay) DCBATOUT
SYSTEM DC/DC
VCC_CORE
TPS51219 45
2GB/1GB/512MB4 LA480 LA580 INPUTS OUTPUTS
D 88,89,90,91
DCBATOUT 1D05V_VTT
D
Project Code 91.4TD01.001 91.4TE01.001
DDR3 SYSTEM DC/DC
800MHz Intel CPU PCB P/N 11264 11273 TPS51225 41
Revision SC SC INPUTS OUTPUTS
3D3V_AUX_S5
NVIDIA PCIe x 16
IVY Bridge DCBATOUT 5V_S5
3D3V_S5
DDRIII 1066/1333/1600 Channel A DDRIII Slot 0
(Discrete only) SYSTEM DC/DC
N13P-GL (V) 1066/1333/1600 14
DDRIII: 1066/1333/1600 MHz RT8207M 46
N13M-GE1 (B) INPUTS OUTPUTS
4,5,6,7,8,9,10
DDRIII 1066/1333/1600 Channel B DDRIII Slot 1 0D75V_S0
83.84,85,86,87
1066/1333/1600 15 DCBATOUT 1D5V_S3
DDR_VREF_S3
FDI x 4 x 2 SYSTEM DC/DC
HDMI DMI x 4 TPS51640 44
(UMA only) 71.08111.N03, IC PCIE CTRL RTL8111F-CGT QFN 48P
C 51
HDMI
INPUTS OUTPUTS C
GLAN DCBATOUT VCC_GFXCORE
LCD LVDS PCIE x 1
RJ45
49 REALTEK
CONN 59 VGA
RGB CRT
Intel RTL8111F 31
TPS51728 92
CRT INPUTS OUTPUTS
50 PCH PCIE x 1/USB2.0 x 1
Mini-Card DCBATOUT VGA_CORE
Bluetooth USB2.0 x 3 Panther Point WLAN 65
TI CHARGER
63 BQ24737 40
USB 3.0/2.0 ports (14) Mini-Card
SATA x 1/USB2.0 x 1 INPUTS OUTPUTS
ETHERNET (10/100/1000Mb) 66
CAMERA +DC_IN_S5
49 High Definition Audio +PBATT DCBATOUT
26
SATA ports (6) SYSTEM DC/DC
USB 3.0 x 2 USB x 2
Finger Print BD Finger Print 64 PCIE ports (8) RT8068A 47
LPC I/F INPUTS OUTPUTS
CardReader ACPI 1.1
SD/MMC+/MS/ USB 2.0 x 1 USB 2.0 x 2 USB x 2 3D3V_S5 1D8V_S0
B MS Pro/xD ALCOR B
AU6435B52
LDO
74 RT8207 46
17,18,19,20,21,22,23,24,25
AZALIA INPUTS
26 OUTPUTS
SATA x 2 HDD
56 5V_S5 0D75V_S0
PCB LAYER
SPI
(V only)
ODD
LPC Bus
Internal DMIC 56 L1:Top L5:VCC
Azalia
L2:GND L6:Signal
CODEC L3:Signal L7:GND
(B only) Analog DMIC
REALTEK Flash ROM LPC debug port L4:Signal L8:Signal
71
8MB 60
Combo ALC269Q-VC2
Jack 29
KBC SMBus
NUVOTON
NPCE885G 27
A
A
2CH SPEAKER
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
G-Sensor Touch Int. Thermal Fan Title
PAD KB EMC2103-2-AP 28 Block Diagram
(V only) 79 69 69 2528 Size Document Number Rev
A3 SD
LA480
Date: Friday, January 06, 2012 Sheet 2 of 103
5 4 3 2 1
PCH Strapping Chief River Schematic Checklist Rev0.72 Processor Strapping Chief River Schematic Checklist Rev0.72
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k CFG[2] PCI-Express Static 1: Normal Operation.
- 10-k weak pull-up resistor. Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
Lane Reversal 0:
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
D GNT2#/GPIO53 Mobile: Used as GPIO only 0 D
GNT1#/GPIO51 Pull-up resistors are not required on these signals. Enabled - An external Display Port device is
0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI function 2 disabled
Straps 11
Left floating, no pull-down required.
Disable Danbury: 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training 1
Disable Danbury: Leave floating (internal pull-down)
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Voltage Rails
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. POWER PLANE VOLTAGE DESCRIPTION
Platform design should provide appropriate pull-up or pull-down depending on ACTIVE IN
C
/GPIO[33] 5V_S0 5V C
the desired settings. If a jumper option is used to tie this signal to GND as 3D3V_S0 3.3V
required by the functional strap, the signal should be pulled low through a weak 1D8V_S0 1.8V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. 1D5V_S0 1.5V
1D05V_VTT 1.05V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal 1D0V_S0 1.0V S0 CPU Core Rail
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for VCCSA 0.9 - 0.675V Graphics Core Rail
strapping functions. 0D75V_S0 0.75V
VCC_CORE 0.35V to 1.5V
VCC_GFXCORE 0.4 to 1.25V
1D8V_VGA_S0 1.8V
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 3D3V_VGA_S0 3.3V
1V_VGA_S0 1V
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low(0) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
GPIO15 5V_USBX_S3 5V
confidentiality. High(1) - Intel ME Crypto Transport Layer Security (TLS) cipher 1D5V_S3 1.5V S3
suite with confidentiality. DDR_VREF_S3 0.75V
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. BT+ 6V-14.1V
Sampled at rising edge of RSMRST#. DCBATOUT 6V-14.1V
CRB has a 1-kohm pull-up on this signal to +3.3VA rail. 5V_S5 5V
5V_AUX_S5 5V All S states AC Brick Mode only
3D3V_S5 3.3V
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down 3D3V_AUX_S5 3.3V
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled. 1D05V_LAN 1.05V S0/M0, SX/M3 ON whenever iAMT is active
B B
Default = Do not connect (floating)
3D3V_M 3.3V
High(1) = Enables the internal VccVRM to have a clean supply for 1D05V_M 1.05V S0/M0, SX/M3, WOL_EN ON for iAMTLegacy WOL
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails. 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
SATA Table
3D3V_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell in G3 SATA
USB Table port9 is debug port and 3D3V_S5 in Sx
Pair Device
PCIe Routing Pair Device SMBus ADDRESSES 0 HDD1
0 USB3.0 ext port 1
LANE1 X Ref Des Chief River CRV
1 mSATA
1 USB3.0 ext port 2 I 2 C / SMBus Addresses
2 N/A
2 USB3.0 ext port 3 Device Address Hex Bus
LANE2 Mini Card2(WWAN) 3 N/A
3 USB3.0 ext port 4 EC SMBus 1 BAT_SCL/BAT_SDA
LANE3 Card Reader Battery
4 ODD
4 BLUETOOTH (USB1.1) BAT_SCL/BAT_SDA
CHARGER BAT_SCL/BAT_SDA 5 ESATA
LANE4 Mini Card1(WLAN) 5 Fingerprint (USB1.1)
6 X
EC SMBus 2 SML1_CLK/SML1_DATA
A
LANE5 X 7 X PCH SML1_CLK/SML1_DATA
A
eDP SML1_CLK/SML1_DATA
LANE6 Intel GBE LAN / LAN 8 Mini Card2 (WWAN) Wistron Corporation
9 USB ext. port 4 / E-SATA /USB CHARGER PCH SMBus PCH_SMBDATA/PCH_SMBCLK 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SO-DIMMA (SPD) PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
LANE7 X 10 CARD READER SO-DIMMB (SPD)
Digital Pot
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK Title
G-Sensor PCH_SMBDATA/PCH_SMBCLK
LANE8 Express Card 11 Mini Card1 (WLAN) MINI PCH_SMBDATA/PCH_SMBCLK Table of Content
12 CCD Size Document Number Rev
A3 SD
13 New Card LA480
Date: Friday, January 06, 2012 Sheet 3 of 103
5 4 3 2 1
5 4 3 2 1
SSID = CPU 01.00IVY.000 IVY BRIDGE ORCAD SYMBOL.
Signal Routing Guideline:
Note: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
Intel DMI supports both Lane PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap. 1D05V_VTT
CPU1A 1 OF 9 NOTE.
J22 PEG_IRCOMP_R R401 1 2
PEG_ICOMPI If PEG is not implemented, the RX&TX pairs can be left as No Connect
D 19 DMI_TXN[3:0]
DMI_TXN0 B27
SANDY PEG_ICOMPO J21
H22
24D9R2F-L-GP D
DMI_TXN1 DMI_RX#0 PEG_RCOMPO
B25 DMI_RX#1
DMI_TXN2 A25 DMI_RX#2 PEG_RXN[0..15] 83
DMI_TXN3 B24 K33 PEG_RXN15
DMI_RX#3 PEG_RX#0 PEG_RXN14
19 DMI_TXP[3:0] PEG_RX#1 M35
DMI_TXP0 B28 L34 PEG_RXN13
DMI_TXP1 DMI_RX0 PEG_RX#2 PEG_RXN12
B26 DMI_RX1 PEG_RX#3 J35
DMI
DMI_TXP2 A24 J32 PEG_RXN11
DMI_TXP3 DMI_RX2 PEG_RX#4 PEG_RXN10
B23 DMI_RX3 PEG_RX#5 H34
H31 PEG_RXN9
19 DMI_RXN[3:0] PEG_RX#6
DMI_RXN0 G21 G33 PEG_RXN8
DMI_RXN1 DMI_TX#0 PEG_RX#7 PEG_RXN7
E22 DMI_TX#1 PEG_RX#8 G30
DMI_RXN2 F21 F35 PEG_RXN6
DMI_RXN3 DMI_TX#2 PEG_RX#9 PEG_RXN5
D21 DMI_TX#3 PEG_RX#10 E34
E32 PEG_RXN4
19 DMI_RXP[3:0] PEG_RX#11
DMI_RXP0 G22 D33 PEG_RXN3
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
D22 DMI_TX1 PEG_RX#13 D31
PCI EXPRESS* - GRAPHICS
DMI_RXP2 F20 B33 PEG_RXN1
DMI_RXP3 DMI_TX2 PEG_RX#14 PEG_RXN0
C21 DMI_TX3 PEG_RX#15 C32
PEG_RXP[0..15] 83
J33 PEG_RXP15
PEG_RX0 PEG_RXP14
PEG_RX1 L35
K34 PEG_RXP13
19 FDI_TXN[7:0] PEG_RX2
FDI_TXN0 A21 H35 PEG_RXP12
FDI_TXN1 FDI0_TX#0 PEG_RX3 PEG_RXP11
Note: H19 FDI0_TX#1 PEG_RX4 H32
Intel FDI supports both Lane FDI_TXN2 E19 G34 PEG_RXP10
FDI_TXN3 FDI0_TX#2 PEG_RX5 PEG_RXP9
F18 G31
Intel(R) FDI
Reversal and polarity inversion FDI_TXN4 B21
FDI0_TX#3 PEG_RX6
F33 PEG_RXP8
but only at PCH side. This is FDI1_TX#0 PEG_RX7
C enabled via a soft strap.
FDI_TXN5
FDI_TXN6
C20
D18
FDI1_TX#1 PEG_RX8 F30
E35
PEG_RXP7
PEG_RXP6 C
FDI_TXN7 FDI1_TX#2 PEG_RX9 PEG_RXP5
E17 FDI1_TX#3 PEG_RX10 E33
F32 PEG_RXP4
PEG_RX11 PEG_RXP3
19 FDI_TXP[7:0] PEG_RX12 D34
FDI_TXP0 A22 E31 PEG_RXP2
FDI_TXP1 FDI0_TX0 PEG_RX13 PEG_RXP1
G19 FDI0_TX1 PEG_RX14 C33
FDI_TXP2 E20 B32 PEG_RXP0 PEG Static Lane Reversal
FDI0_TX2 PEG_RX15 PEG_TXN[0..15] 83
FDI_TXP3 G18
FDI_TXP4 FDI0_TX3 PEG_C_TXN15 C401 SCD22U10V2KX-1GP PEG_TXN15
FDI_TXP5
B20 FDI1_TX0 PEG_TX#0 M29
PEG_C_TXN14 C402
1 2 OPS SCD22U10V2KX-1GP PEG_TXN14
FDI_TXP6
C19 FDI1_TX1 PEG_TX#1 M32
PEG_C_TXN13 C403
1 2 OPS SCD22U10V2KX-1GP PEG_TXN13
FDI_TXP7
D19 FDI1_TX2 PEG_TX#2 M31
PEG_C_TXN12 C404
1 2 OPS SCD22U10V2KX-1GP PEG_TXN12
F17 FDI1_TX3 PEG_TX#3 L32
PEG_C_TXN11 C405
1 2 OPS SCD22U10V2KX-1GP PEG_TXN11
PEG_TX#4 L29
PEG_C_TXN10 C406
1 2 OPS SCD22U10V2KX-1GP PEG_TXN10
19 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#5 K31
PEG_C_TXN9 C407
1 2 OPS SCD22U10V2KX-1GP PEG_TXN9
19 FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#6 K28
PEG_C_TXN8 C408
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