Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop LENOVO G450 LA5751PR03_1029A
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A B C D E
1 1
Compal Confidential
Schematics Document
2 2
NIWE1
Arrandale
3 with Intel IBEX PEAK-M core logic 3
REV:0.3
4 4
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 1 of 51
A B C D E
A B C D E
Compal confidential POWER BD: CAP SENSOR BD: CARD READER BD:
File Name : POWER BTN VOLUME UP ENE UB6250/52
ZZZ1 NOVO BTN VOLUME DOWN HP JACK
POWER MANAGE BTN MUTE MIC JACK
14W_PCB_LA5751P VRAM 64*16 Intel AUDIO ENHANCE
DDR3*4 Arrandale BUTTON & LED
1 ZZZ page23 Clock Generator 1
HYN@ PCI-E X16 (UMA/DIS) RTM890N
page12
X76_H512
NVidia N11M-GE1 Socket-rPGA989
page19~23
37.5mm*37.5mm DDR3-SO-DIMM X2
level shift IC BANK 0, 1, 2, 3 page 10,11
page5~9
HDMI Dual Channel
CONN ASM1442 100MHz DDR3-800(1.5V) UP TO 8G
page25
2.7GT/s FDI *8 DMI *4 DDR3-1066(1.5V)
page24
CRT Connector 2Channel Speaker
page33
page26
2
LVDS Intel Ibex Peak M AZALIA Audio Codec Analog MIC_Int
2
page33
Connector page27 CONEXTAN
FCBGA 951 CX20671 page33
PCI Express
6*PCI-E BUS 25mm*25mm
Mini card Slot 1 14*USB2.0 CMOS Camera
page28
page27
PCI Express 6*SATA serial BlueTooth CONN
Mini card Slot 2 page 13~18 page37
page28
SPI ROM USB CONN X1(Right)
page37
BIOS page13 LPC BUS
3
SIM Card USB PORT X1(Left) 3
page37
page28 USB(WWAN)
RTL8103EL/8111DL
EC New Card X1
ENE KB926D Card Reader/Audio Jack SB
page28
10/100/1G LAN page34
page29 CONN
WWAN ENE UB6250/52 HP X 1+
page28 MS/MS MIC_Ext X1
pro/SD/SD
RJ45 CONN Int.KBD pro/mmc/XD
page30 page35 page38
EMC1403 SPI ROM ESATA HDD AND USB CONN
Thermal Sensor EC page36
SATA HDD CONN page37
page31
page32
4 Touch Pad SATA ODD CONN 4
page32
page35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/24 Deciphered Date 2008/04/ Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 2 of 51
A B C D E
A B C D E
DDR3 Voltage Rails
SMBUS Control Table
N10x NEW
WLAN Thermal Cap sensor CARD PCH
SOURCE RAM M2 BATT KE926 SODIMM CLK CHIP WWAN N10x board
+5VS Sensor
+3VS SMB_EC_CK1
power
+1.5VS SMB_EC_DA1
KB926 X V
+3VALW
X X X X X X X X X
plane +3VALW
+VCCP SMB_EC_CK2
1
+5VALW +1.5V +CPU_CORE SMB_EC_DA2
KB926 X X X X X X X X X X V 1
+3VALW +3VALW
+B +VGA_CORE SMBCLK
+3VALW +1.8VS SMBDATA
PCH V X X V V X X X X V X
+3VALW +3VALW +3VS +3VS +3VS
+0.75VS SML0CLK
State +1.05VS SML0DATA
PCH
+3VALW
X X X X X X X X X X X
SML1CLK
SML1DATA
PCH
+3VALW
X X V X X X +3VS
V X V
+3VS
X X
+3VALW
S0
O O O O
I2C / SMBUS ADDRESSING
S3
O O O X
2
S5 S4/AC DEVICE HEX ADDRESS 2
O O X X
DDR SO-DIMM 0 A0 10100000
S5 S4/ Battery only
O X X X DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010
S5 S4/AC & Battery
don't exist X X X X
@ FUNCTION
Structure Description NON-USE
45@ 45 BOM
BT@ Blue Tooth function
3G@ 3G function (WWAN)
CAP@ CAP Sensor function
CMOS@ CMOS CAMERA function PCIE PORT LIST USB PORT LIST
3
ESATA@ E-SATA function PORT DEVICE PORT DEVICE 3
HDMI@ HDMI function (UMA or DIS)
UMA_HDMI@ HDMI function (UMA only) 1 0 RIGHT SIDE
X76@ X76 BOM 2 WLAN 1 LEFT SIDE
100@ 10/100 LAN function 3 LAN 2 CMOS
GIGA@ GIGA LAN function 4 3G 3 LEFT SIDE
UMA@ UMA only (Arrandale) 5 NEW CARD 4 RIGHT SIDE
DIS@ DIS only (Arrandale) 6 5 CARD READER
7 6
8 7
8 WIRELESS
9
10 NEW CARD
11 BT
SKU 12
13 3G
Arrandale(dGPU) DIS@
4 4
DIS only
Arrandale(iGPU) UMA@
UMA only
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/24 Deciphered Date 2008/04/ Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 3 of 51
A B C D E
A B C D E
VGA and DDR3 Voltage Rails (N11x GPIO) Performance Mode P0 TDP at Tj = 102 C* (DDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.5V) (1.5V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 N/A N/A Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO1 IN - Hot plug detect for IFP link C N11M-GE1
64bit 14.02 2.16 TBD TBD 12.9 12.26 0.66 0.99 1.3 1.95 530 0.56 84 0.15 140 0.15 38 0.13
512MB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) DDR3
1 1
GPIO3 OUT H Panel Power Enable
GPIO5 GPIO6
GPIO4 OUT H Panel Back-Light On/Off (PWM)
GPU_VID0 GPU_VID1 VGA_CORE P-State
Device ID
GPIO5 OUT - GPU VID0 0 0 0.8V Deep P12
N11M-GE1/LP1 0 1 0.85V P8
GPIO6 OUT - GPU VID1 (40nm) 0x0A7D
1 1 1.03V P0
GPIO7 OUT N/A
GPIO8 I/O N/A
GPIO9 OUT N/A
GPIO10 OUT N/A
GPIO11 I/O - Reserve 10K pull low.
GPIO12 IN N/A
2
GPIO13 OUT N/A 2
GPIO14 OUT - Reserve 10K pull low.
GPIO15 IN N/A
GPIO16 OUT N/A
GPIO17 IN - PAD The ramp time for any rail must be more than 40us
Power Sequence
GPIO18 IN N/A
GPIO19 IN N/A
(+3VS) VDD33
PEX_VDD can ramp up any time
(1.05VS)PEX_VDD
tNVVDD
3 3
(+VGA_CORE) NVVDD
tNV-IFPAB_IOVDD
(1.8VS)IFPAB_IOVDD
tNV-FBVDDQ
(1.5VS) FBVDDQ
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/03/16 Deciphered Date 2010/03/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 4 of 51
A B C D E
5 4 3 2 1
DDR3 Compensation Signals
SM_RCOMP0 1 2
R567 100_0402_1%
SM_RCOMP1 1 2
R566 24.9_0402_1%
SM_RCOMP2 1 2
R565 130_0402_1%
Layout Note:Please these
D
Layout rule10mil width trace resistors near Processor D
length < 0.5", spacing 20mil
JCPU1B
20_0402_1% 1 R560 2COMP3 AT23 COMP3 CLK_CPU_BCLK
BCLK A16 CLK_CPU_BCLK <16> +VCCP
MISC
MISC
20_0402_1% 1 R558 2COMP2 AT24 COMP2 BCLK# B16 CLK_CPU_BCLK#
CLK_CPU_BCLK# <16>
49.9_0402_1% 1 R548 2COMP1 CLK_CPU_ITP PM_EXTTS#0
CLOCKS
G16 COMP1 BCLK_ITP AR30 T17 PAD 1 2
AT30 CLK_CPU_ITP# T18 PAD R561 10K_0402_5%
49.9_0402_1% BCLK_ITP#
1 R557 2COMP0 AT26 COMP0
PM_EXTTS#1 1 2
E16 CLK_EXP R562 10K_0402_5%
PEG_CLK CLK_EXP <14>
D16 CLK_EXP#
PEG_CLK# CLK_EXP# <14>
TP_SKTOCC# AH24 SKTOCC#
DPLL_REF_SSCLK A18 pins unused by
A17
+VCCP 2 1 H_CATERR# AK14
DPLL_REF_SSCLK# Clarksfield on the XDP_PREQ# R136 1 @ 2 51_0402_1%
CATERR#
THERMAL
THERMAL
49.9_0402_1% R163 rPGA989 Package
XDP_TMS R138 1 @ 2 51_0402_1%
<16> H_PECI
R564
1
0_0402_5%
2 H_PECI_ISO AT15 PECI
SM_DRAMRST# F6 SM_DRAMRST# 3 XDP_TDI R556 1 @ 2 51_0402_1%
AL1 SM_RCOMP0
SM_RCOMP[0]
+VCCP 2 R569 1 68_0402_5% SM_RCOMP[1] AM1 SM_RCOMP1 XDP_TDO R134 1 2 51_0402_5%
AN1 SM_RCOMP2
H_PROCHOT# SM_RCOMP[2]
<34,48> H_PROCHOT# AN26 PROCHOT#
AN15 PM_EXTTS#0 XDP_TCK R57 1 @ 2 51_0402_1%
PM_EXT_TS#[0]
DDR3
MISC
AP15 PM_EXTTS#1 1 2
PM_EXT_TS#[1] PM_EXTTS#1_R <10,11>
R563 0_0402_5% XDP_TRST# R133 1 2 51_0402_5%
H_THERMTRIP# AK15
<16> H_THERMTRIP# THERMTRIP#
AT28 XDP_PRDY# T19 PAD R137
C PRDY# XDP_PREQ# XDP_DBRESET# @ C
PREQ# AP27 1 2 1K_0402_5% +3VS
AN28 XDP_TCK
TCK
1 H_CPURST#_R XDP_TMS
+VCCP 2 AP26 RESET_OBS# TMS AP28
CHECK INTEL DOCUMENT #385422
PWR MANAGEMENT
PWR MANAGEMENT
68_0402_5% R135 AT27 XDP_TRST#
TRST#
Debug Port Design Guide Rev1.3
JTAG & BPM
<15> H_PM_SYNC 1 R187 2 H_PM_SYNC_R AL15 PM_SYNC TDI AT29 XDP_TDI
0_0402_5% AR27 XDP_TDO
TDO
TDI_M AR29
1 R190 2 VCCPWRGOOD_1 AN14 VCCPWRGOOD_1 TDO_M AP29 R555 2 1 0_0402_5%
0_0402_5%
AN25 XDP_DBRESET#
DBR#
<16> H_CPUPWRGD 1 R139 2 VCCPWRGOOD_0 AN27 VCCPWRGOOD_0
0_0402_5%
AJ22 XDP_BPM#0
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