Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop LENOVO Y470
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A B C D E
1 1
Compal Confidential
2 2
PIQY0 M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
nVIDIA N12P-GT
3 2010-12-30 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Wednesday, January 05, 2011 Sheet 1 of 63
A B C D E
A B C D E
ZZZ4 ZZZ5 ZZZ6 ZZZ7
Compal confidential ZZZ1 ZZZ2 ZZZ3
File Name : PIQY0 POWER & ALS BOARD
LS6881P LS6882P LS6883P LA6881P
DAZ@ DAZ@ DAZ@ DAZ@
DAZ0HA00100 X7625738L01
X761G@
X7625738L03
X762G@
CAP SENSOR & Slid bar
BOARD
1 Intel 1
nVIDIA N12P-GT
PCI-E X16 Sandy Bridge
VRAM 64*16
DDR3*8 Socket-rPGA988B
37.5mm*37.5mm DDR3-SO-DIMM X2
BANK 0, 1, 2, 3
HDMI Passive Dual Channel UP TO 8G
CONN level shift
100MHz FDI *8 DMI *4 DDR3-1066(1.5V)
2.7GT/s DDR3-1333(1.5V)
optimus 1.0
CRT Connector 2Channel Speaker
2 2
optimus 1.0 Array Digital MIC
LVDS Intel Audio Codec
AZALIA RealTek
Connector
Cougar Point ALC272/ALC5503
Audio Jacks
PCI Express USB(WiMAX)
Stereo
6*PCI-E BUS
Mini card Slot 1 PCI-E(WLAN) FCBGA 951 14*USB2.0
HeadPhone Output
WLAN/WiMAX Microphone Input
25mm*25mm CMOS Camera
PCI Express 6*SATA serial BlueTooth CONN
Mini card Slot 2 (port0,1
USB PORT 2.0 x2(Left)
SSD support SATA3)
LPC BUS
Option3.0 x2
USB3.0 SPI ROM
SATA(SSD)
BIOS WLAN/WiMAX
3 RENESAS 3
UPD720200
EC
ENE KB930 USB PORT 2.0 x1(Right)
Card Reader
Jmicro JMB389
Broadcom
BCM57781/57780
SD/MMC/MS/XD
10/100/1G LAN
Int.KBD
ESATA HDD AND USB CONN
WLAN/WiMAX Touch Pad SPI ROM (Right)
RJ45 CONN
SATA3.0 HDD CONN
Thermal Sensor SATA3.0 HDD (SSD)
4 4
EMC1403
SATA ODD CONN
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 05, 2011 Sheet 2 of 63
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Voltage Rails
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+5VS
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+3VS
power
plane +1.5VS S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VCCP
+5VALW +1.5V +CPU_CORE
+B +VGA_CORE Board ID / SKU ID Table for AD channel
+3VALW +GFX_CORE Vcc 3.3V +/- 5%
+1.8VS Ra/Rc/Re 100K +/- 5%
State +0.75VS Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.05VS 0 0 0 V 0 V 0 V
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
S0 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
O O O O
7 NC 2.500 V 3.300 V 3.300 V
2 2
S3
O O O X BOARD ID Table BOM Structure Table
S5 S4/AC
BTO Item BOM Structure
O O X X Board ID PCB Revision
UMA
0 0.1
S5 S4/ Battery only
UMA Only UMA_ONLY@
O X X X 1
Optimus OPTI@
2
S5 S4/AC & Battery
VRAM X76@
X X X X 3
don't exist HDMI HDMI@
4
Blue Tooth BT@
5
USB3.0 USB30@
elbaT lortnoC SUBMS 6
ESATA ESATA@
7
lamrehT USB Charger USB_CHG@
ECRUOS AGV TTAB NALW rosneS No USB Charger NO_CHG@
NAWW MMIDOS 039BK HCP
USB Port Table Unpop @
1KC_CE_BMS
1AD_CE_BMS 039BK
WLAV3+
X V
WLAV3+
X X X X X 3 External
Codec ALC272 272@
3 USB 2.0 USB 1.1 Port USB Port Codec ALC5503 5503@ 3
2KC_CE_BMS
2AD_CE_BMS 039BK
WLAV3+
X X X X X X V
SV3+ 0 USB/Cable (Right Side)
LAN 57781 57781@
UHCI0 LAN 57780 57780@
KLCBMS 1 USB Port (Right Side COMBO)
ATADBMS HCP
WLAV3+
X X X SV+
V3 SV+
V3 X X 2 USB/B (Left Side)
Ventura Feature VENTURA@
UHCI1 Camera CMOS@
KLC0LMS 3 USB/B (Left Side)
ATAD0LMS HCP
WLAV3+
X X X X X X X EHCI1
4
UHCI2
KLC1LMS 5 Camera
ATAD1LMS HCP
WLAV3+ SV+
V3 X SV+
V3 X X SV+
V3 X
UHCI3
6
VRAM BOM Config
X761G@: X7625738L01 Samsung 1GB
7
Sub: X7625738L02 Hynix 1GB
8
UHCI4 X762G@: X7625738L03 Samsung 2GB
EC SM Bus1 address EC SM Bus2 address 9 Mini Card(WLAN)
Sub: X7625738L04 Hynix 2GB
10
EHCI2 UHCI5
Device Address Device Address 11 GPU BOM Config
Smart Battery 0001 011X b 12 N12P SKU: OPTI@
Thermal Sensor EMC1403-2 1001_101xb UHCI6
13 Blue Tooth GS SKU: GS@
GT SKU: GT@
4 4
PCH SM Bus address
Device Address
DDR DIMM0 1001 000Xb
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title
DDR DIMM2 1001 010Xb
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
EMC
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Wednesday, January 05, 2011 Sheet 3 of 63
A B C D E
5 4 3 2 1
+3VS_VGA
+1.05VS_VGA
D tNVVDD >0 D
+VGA_CORE
tNV-IFPAB_IOVDD >0
+1.8VS_VGA
tNV-FBVDDQ >0
+1.5VS_VGA
1. The ramp rate for any rail must be more than 40us.
2. +VGA_CORE <= +3VS_VGA +0.5V
3. +1.5VS_VGA <= +3VS_VGA +0.5V
4. Optimus follows power sequencing rules
specified in discrete GPU design guide.
C C
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Wednesday, January 05, 2011 Sheet 4 of 63
5 4 3 2 1
5 4 3 2 1
D D
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+1.05VS impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
1
max length = 500 mils
R1
24.9_0402_1% - typical impedance = 14.5 mohms
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
<16> DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
<16> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 A25 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23>
<16> DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N15
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N14
PEG_RX#[1] M35
<16> DMI_CRX_PTX_P0 B28 L34 PCIE_CRX_GTX_N13
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12
<16> DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35 PEG Static Lane Reversal - CFG2 is for the 16x
DMI
A24 J32 PCIE_CRX_GTX_N11
<16> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4]
<16> DMI_CRX_PTX_P3 B23 H34 PCIE_CRX_GTX_N10
DMI_RX[3] PEG_RX#[5] PCIE_CRX_GTX_N9
PEG_RX#[6] H31 1: Normal Operation; Lane # definition matches
G21 G33 PCIE_CRX_GTX_N8 CFG2
<16> DMI_CTX_PRX_N0
E22
DMI_TX#[0] PEG_RX#[7]
G30 PCIE_CRX_GTX_N7 socket pin map definition
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PCIE_CRX_GTX_N6
<16> DMI_CTX_PRX_N2 F21 DMI_TX#[2] PEG_RX#[9] F35
D21 E34 PCIE_CRX_GTX_N5 0:Lane Reversed
<16>
<16>
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0 G22
DMI_TX#[3]
DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3 *
D22 D31 PCIE_CRX_GTX_N2
C <16> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PCIE_CRX_GTX_N1 C
PCI EXPRESS* - GRAPHICS
<16> DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33
C21 C32 PCIE_CRX_GTX_N0
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] <23>
J33 PCIE_CRX_GTX_P15
PEG_RX[0] PCIE_CRX_GTX_P14
PEG_RX[1] L35
K34 PCIE_CRX_GTX_P13
PEG_RX[2] PCIE_CRX_GTX_P12
<16> FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PCIE_CRX_GTX_P11
<16> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] PCIE_CRX_GTX_P9
F18 G31
Intel(R) FDI
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] PCIE_CRX_GTX_P8
<16> FDI_CTX_PRX_N4 B21 F33
FDI1_TX#[0] PEG_RX[7] PCIE_CRX_GTX_P7
<16> FDI_CTX_PRX_N5 C20 F30
FDI1_TX#[1] PEG_RX[8] PCIE_CRX_GTX_P6
<16> FDI_CTX_PRX_N6 D18 E35
FDI1_TX#[2] PEG_RX[9] PCIE_CRX_GTX_P5
<16> FDI_CTX_PRX_N7 E17 E33
FDI1_TX#[3] PEG_RX[10] PCIE_CRX_GTX_P4
F32
PEG_RX[11] PCIE_CRX_GTX_P3
D34
PEG_RX[12] PCIE_CRX_GTX_P2
<16> FDI_CTX_PRX_P0 A22 E31
FDI0_TX[0] PEG_RX[13] PCIE_CRX_GTX_P1
<16> FDI_CTX_PRX_P1 G19 C33
FDI0_TX[1] PEG_RX[14] PCIE_CRX_GTX_P0
<16> FDI_CTX_PRX_P2 E20 B32
FDI0_TX[2] PEG_RX[15]
<16> FDI_CTX_PRX_P3 G18 PCIE_CTX_GRX_N[0..15] <23>
FDI0_TX[3] PCIE_CTX_GRX_C_N15 C1 PCIE_CTX_GRX_N15
<16> FDI_CTX_PRX_P4 B20 M29 1 2 0.1U_0402_10V6K
FDI1_TX[0] PEG_TX#[0] PCIE_CTX_GRX_C_N14 C2 PCIE_CTX_GRX_N14
<16> FDI_CTX_PRX_P5 C19 M32 1 2 0.1U_0402_10V6K
FDI1_TX[1] PEG_TX#[1] PCIE_CTX_GRX_C_N13 C3 PCIE_CTX_GRX_N13
<16> FDI_CTX_PRX_P6 D19
FDI1_TX[2] PEG_TX#[2]
M31 1 [email protected]_0402_10V6K
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